TW201428900A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TW201428900A
TW201428900A TW102100084A TW102100084A TW201428900A TW 201428900 A TW201428900 A TW 201428900A TW 102100084 A TW102100084 A TW 102100084A TW 102100084 A TW102100084 A TW 102100084A TW 201428900 A TW201428900 A TW 201428900A
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TW
Taiwan
Prior art keywords
substrate body
metal layer
conductive
semiconductor package
carrier
Prior art date
Application number
TW102100084A
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English (en)
Inventor
黃富堂
柯俊吉
Original Assignee
矽品精密工業股份有限公司
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Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102100084A priority Critical patent/TW201428900A/zh
Priority to CN201310024271.6A priority patent/CN103915408A/zh
Priority to US13/872,494 priority patent/US20140183755A1/en
Publication of TW201428900A publication Critical patent/TW201428900A/zh

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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract

一種半導體封裝件及其製法，該半導體封裝件包括：承載件，係具有接置區及至少一接地墊；基板本體，係具有複數導電穿孔及相對之第一表面與第二表面，各該導電穿孔具有對應該第一表面與第二表面之第一端部及第二端部，該導電穿孔之第一端部係外露於該基板本體之第一表面，該基板本體並以該第二表面設置於該承載件之接置區上；金屬層，係形成於該基板本體之第一表面上，並外露出該導電穿孔之第一端部；導電體，係電性連接該金屬層與該承載件之接地墊；以及半導體元件，係設置於該基板本體上，並電性連接該導電穿孔之第一端部。藉此，本發明能具有電磁干擾屏蔽(EMI shielding)之效果，以避免該基板本體與該半導體元件所產生之電磁波或電性訊號互相干擾。

Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件及其製法，特別是指一種具有電磁干擾屏蔽之半導體封裝件及其製法。
隨著半導體之技術不斷地增長，愈來愈多的電子元件可以整合在一個半導體封裝件內，且隨著電子產品之輕薄短小的趨勢，半導體封裝件之體積亦愈來愈小，因而發展出立體(3D)封裝之技術，亦即將複數晶片安裝在同一半導體封裝件中。
同時，為了達到該些晶片互相堆疊之需求，因而發展出所謂的矽穿孔(Through Silicon Vias；TSV)之技術，亦即在矽基板中形成複數貫穿孔。藉此，可提高該半導體封裝件之處理速度，並大幅降低功率之損耗。
但是，當該些晶片中含有射頻(RF)晶片或通訊晶片時，該些晶片之間容易發生電磁波或電性訊號互相干擾的問題。
因此，如何克服上述習知技術的問題，實已成目前亟 欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，其包括：承載件，係具有接置區及至少一接地墊；基板本體，係具有複數導電穿孔及相對之第一表面與第二表面，各該導電穿孔具有對應該第一表面與第二表面之第一端部及第二端部，該導電穿孔之第一端部係外露於該基板本體之第一表面，該基板本體並以該第二表面設置於該承載件之接置區上；金屬層，係形成於該基板本體之第一表面上，並外露出該導電穿孔之第一端部；導電體，係電性連接該金屬層與該承載件之接地墊；以及半導體元件，係設置於該基板本體上，並電性連接該導電穿孔之第一端部。
本發明亦提供一種半導體封裝件之製法，其包括：提供一具有複數導電穿孔及相對之第一表面與第二表面之基板本體，各該導電穿孔具有對應該第一表面與第二表面之第一端部及第二端部，該導電穿孔之第一端部係外露於該基板本體之第一表面；於該基板本體之第一表面上形成一金屬層，該導電穿孔之第一端部係外露於該金屬層；將該基板本體以其第二表面設置於一具有至少一接地墊之承載件上；以及電性連接半導體元件與該導電穿孔之第一端部，並藉由至少一導電體電性連接該金屬層與該承載件之至少一接 地墊。
由上可知，本發明之半導體封裝件及其製法，主要是在基板本體之第一表面上形成金屬層，並將該基板本體設置於具有接地墊之承載件上，再藉由導電體電性連接該金屬層與該接地墊。藉此，本發明能具有電磁干擾屏蔽(EMI shielding)之效果，以避免該基板本體與該半導體元件所產生之電磁波或電性訊號互相干擾。
1‧‧‧半導體封裝件
10‧‧‧基板本體
10a‧‧‧第一表面
10b‧‧‧第二表面
101‧‧‧導電穿孔
102‧‧‧第一端部
103‧‧‧第二端部
104‧‧‧側面
11‧‧‧絕緣層
12‧‧‧導電材
13‧‧‧金屬層
131‧‧‧開孔
14‧‧‧黏著層
141‧‧‧承載件
15‧‧‧導電凸塊
16‧‧‧底膠
161‧‧‧側邊
162‧‧‧底膠
17‧‧‧承載件
17a‧‧‧頂面
17b‧‧‧底面
171‧‧‧第一接地墊
172‧‧‧第二接地墊
173‧‧‧導電穿孔
174‧‧‧接置區
18‧‧‧導電體
19‧‧‧半導體元件
191‧‧‧導電元件
20‧‧‧封裝膠體
AA‧‧‧切割線
第1A至1K圖係繪示本發明之第一實施例中半導體封裝件及其製法之剖視示意圖。
第1H’係繪示本發明第1H圖之俯視示意圖。
第1I’係繪示本發明第1I圖之俯視示意圖。
第1J’係繪示本發明第1J圖於另一態樣之俯視示意圖。
第2A至2C圖係繪示本發明之第二實施例中半導體封裝件及其製法之部分剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」、「表面」及「端部」等用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第1A至1K圖係繪示本發明之第一實施例中半導體封裝件及其製法之剖視示意圖，第1H’係繪示本發明第1H圖之俯視示意圖，第1I’係繪示本發明第1I圖之俯視示意圖，第1J’係繪示本發明第1J圖於另一態樣之俯視示意圖。
如第1A圖所示，提供一具有複數導電穿孔101及相對之第一表面10a與第二表面10b之基板本體10，各該導電穿孔101具有對應該第一表面10a與該第二表面10b之第一端部102及第二端部103，且該導電穿孔101之第一端部102外露於該基板本體10之第一表面10a。該導電穿孔101可為矽穿孔(TSV)或貫穿孔(vias)等，該基板本體10可為矽基板、中介板(interposer)或具有矽穿孔之晶片等。
如第1B圖所示，形成絕緣層11於該基板本體10之第一表面10a上，且該絕緣層11外露出該導電穿孔101之第一端部102。繼而，形成複數導電材12於該導電穿孔101之第一端部102上。該絕緣層11可為保護層(passivation layer)等，該導電材12可為金屬材料等。
如第1C圖所示，形成金屬層13於該基板本體10之第 一表面10a之絕緣層11上。該金屬層13具有複數開孔131，以外露出該導電穿孔101之第一端部102之導電材12。同時，該導電材12與該金屬層13之間具有間隙，以避免該導電材12接觸該金屬層13而接地。該金屬層13可為銅層等。
如第1D圖所示，形成黏著層14於該金屬層13上，且該黏著層14包覆該導電材12及該開孔131。接著，設置承載件141於該黏著層14上。
如第1E圖所示，利用研磨、切割或其他方式，自該第二表面10b薄化該基板本體10之厚度，以外露出該導電穿孔101之第二端部103。然後，自該第二表面10b形成複數導電凸塊15於該導電穿孔101之外露第二端部103上。
如第1F圖所示，分別移除該承載件141及該黏著層14，以外露出該導電材12、金屬層13與開孔131。
如第1G圖所示，沿著第1F圖之切割線AA一併切割該基板本體10、絕緣層11及金屬層13，以將該基板本體10、絕緣層11、導電材12、金屬層13及導電凸塊15所形成之結構分離為複數個結構體。
如第1H圖及第1H’圖所示，先將該基板本體10以其第二表面10b接置於承載件17之接置區174上，並藉由該導電凸塊15電性連接該導電穿孔101之第二端部103與該承載件17，再形成底膠16於該基板本體10之第二表面10b與該承載件17之接置區174間。或者，先形成底膠16於 該承載件17之頂面17a上，並將該基板本體10以其第二表面10b接置於該承載件17之接置區174上，再藉由該導電凸塊15電性連接該導電穿孔101之第二端部103與該承載件17。
在本實施例中，該承載件17係具有至少一第一接地墊171、第二接地墊172、導電穿孔173及相對之頂面17a與底面17b。該第一接地墊171與第二接地墊172係分別形成於該頂面17a及該底面17b上，該導電穿孔173係形成於該承載件17之內部、或貫穿該頂面17a與底面17b，並電性連接該第一接地墊171及該第二接地墊172。
如第1I圖及第1I’圖所示，藉由至少一導電體18電性連接該金屬層13與該承載件17之第一接地墊171。該導電體18可為導電膠，係自該金屬層13沿著該基板本體10之側面104及該底膠16之側邊161延伸至該承載件17之第一接地墊171。
如第1J圖所示，形成複數導電元件191於半導體元件19、或外露於該金屬層13之複數開孔131中之該導電材12上。接著，以覆晶方式將該半導體元件19接置於該基板本體10之第一表面10a上，而令該半導體元件19位於該金屬層13之上方，俾藉由該導電元件191電性連接該半導體元件19與外露於該開孔131中之導電材12。該導電元件191可為導電凸塊，該半導體元件19可為半導體晶片、射頻(RF)晶片或通訊晶片等。
如第1J’圖所示，該半導體元件19與該金屬層13之間 亦可形成底膠162，用以包覆該導電元件191及該開孔131。
如第1K圖所示，自第1J圖(或第1J’圖)中，形成封裝膠體20於該承載件17之頂面17a上，以包覆該基板本體10、絕緣層11、導電材12、金屬層13、導電體18與半導體元件19。
第2A圖至第2C圖係繪示本發明之第二實施例中半導體封裝件及其製法之部分剖視示意圖。第二實施例與上述第一實施例之半導體封裝件1之製法大致相同，其主要差異詳如下述：如第2A圖所示，以覆晶方式將半導體元件19接置於基板本體10之第一表面10a上，而令該半導體元件19位於金屬層13之上方，並藉由複數導電元件191電性連接該半導體元件19與外露於該金屬層13之複數開孔131中之導電材12。
如第2B圖所示，藉由至少一導電體18電性連接該金屬層13與承載件17之至少一第一接地墊171。該導電體18可為導電膠，係自該金屬層13沿著基板本體10之側面104及底膠16之側邊161延伸至該承載件17之至少一第一接地墊171。
如第2C圖所示，形成封裝膠體20於該承載件17之頂面17a上，以包覆該基板本體10、絕緣層11、導電材12、金屬層13、導電體18與半導體元件19。
關於第二實施例之半導體封裝件1之其餘製法，則同於上述第一實施例之第1A圖至第1H’圖所示者，故不再重 覆贅述。
本發明另提供一種半導體封裝件1，如第1K圖所示，該半導體封裝件1係包括承載件17、基板本體10、金屬層13、導電體18、半導體元件19以及封裝膠體20。
該承載件17具有至少一導電穿孔173、相對之頂面17a與底面17b，該頂面17a上定義有接置區174並具有形成於該接置區174外之至少一第一接地墊171，且該底面17b具有至少一第二接地墊172。
該基板本體10具有複數導電穿孔101及相對之第一表面10a與第二表面10b，各該導電穿孔101具有對應該第一表面10a與第二表面10b之第一端部102及第二端部103，該導電穿孔101之第一端部102係外露於該基板本體10之第一表面10a。
該基板本體10係藉其第二表面10b設置於該承載件17之接置區174上。該基板本體10可為矽基板、中介板或具有矽穿孔之晶片等，該導電穿孔101可為矽穿孔或貫穿孔等。
該金屬層13係形成於該基板本體10之第一表面10a上，並外露出該導電穿孔101之第一端部102。該金屬層13可為銅層等。
該導電體18係用以電性連接該金屬層13與該承載件17之第一接地墊171。
該半導體元件19係以覆晶方式設置於該金屬層13之上方，並電性連接該導電穿孔101之第一端部102。該半 導體元件19可為半導體晶片、射頻晶片或通訊晶片等。
該封裝膠體20係形成於該承載件17之頂面17a上，以包覆該基板本體10、金屬層13、導電體18與半導體元件19。
該半導體封裝件1可包括絕緣層11，係形成於該基板本體10之第一表面10a與該金屬層13之間，並外露出該導電穿孔101之第一端部102。該絕緣層11可為保護層等。
該半導體封裝件1可包括導電材12，係形成於該導電穿孔101之第一端部102上。該導電材12可為金屬材料等。
上述之金屬層13可具有複數開孔131，以外露出該導電材12，俾使該導電材12與該金屬層13之間形成有間隙，故能避免該導電材12接觸該金屬層13而接地。
該半導體封裝件1可包括複數導電凸塊15，該導電穿孔101貫穿該基板本體10之第一表面10a與第二表面10b，俾供該導電凸塊15分別形成於該導電穿孔101之第二端部103上。
該半導體封裝件1可包括底膠16，係形成於該承載件17之頂面17a上，用以包覆該導電凸塊15。上述之承載件17並電性連接該導電凸塊15之外露部分。
上述之導電體18可為導電膠，係自該金屬層13沿著該基板本體10之側面104及該底膠16之側邊161延伸至該承載件17之第一接地墊171。
該半導體封裝件1可包括複數導電元件191，係形成於該半導體元件19、或外露於該開孔131中之導電材12 上，以電性連接該半導體元件19與該導電材12。該導電元件191可為導電凸塊。
由上可知，本發明之半導體封裝件及其製法，主要是在基板本體之第一表面上形成金屬層(如銅層)，並在該基板本體之第二表面上設置具有接地墊之承載件，再藉由導電體(如導電膠)電性連接該金屬層與該接地墊。藉此，本發明能具有電磁干擾屏蔽之效果，以避免半導體元件(如射頻晶片)與基板本體(如另一晶片)所產生之電磁波或電性訊號互相干擾。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1‧‧‧半導體封裝件
10‧‧‧基板本體
10a‧‧‧第一表面
10b‧‧‧第二表面
101‧‧‧導電穿孔
102‧‧‧第一端部
103‧‧‧第二端部
104‧‧‧側面
11‧‧‧絕緣層
12‧‧‧導電材
13‧‧‧金屬層
131‧‧‧開孔
15‧‧‧導電凸塊
16‧‧‧底膠
161‧‧‧側邊
17‧‧‧承載件
17a‧‧‧頂面
17b‧‧‧底面
171‧‧‧第一接地墊
172‧‧‧第二接地墊
173‧‧‧導電穿孔
174‧‧‧接置區
18‧‧‧導電體
19‧‧‧半導體元件
191‧‧‧導電元件
20‧‧‧封裝膠體

Claims (15)

  1. 一種半導體封裝件，其包括：承載件，係具有接置區及至少一接地墊；基板本體，係具有複數導電穿孔及相對之第一表面與第二表面，各該導電穿孔具有對應該第一表面與第二表面之第一端部及第二端部，且該導電穿孔之第一端部外露於該基板本體之第一表面，該基板本體並以該第二表面設置於該承載件之接置區上；金屬層，係形成於該基板本體之第一表面上，並外露出該導電穿孔之第一端部；導電體，係電性連接該金屬層與該承載件之至少一接地墊；以及半導體元件，係設置於該基板本體上，並電性連接該導電穿孔之第一端部。
  2. 如申請專利範圍第1項所述之半導體封裝件，復包括絕緣層，係形成於該基板本體之第一表面與該金屬層之間，並外露出該導電穿孔之第一端部。
  3. 如申請專利範圍第1項所述之半導體封裝件，復包括複數導電材，係形成於該導電穿孔之第一端部上。
  4. 如申請專利範圍第3項所述之半導體封裝件，其中，該金屬層具有複數開孔，以外露出該導電材，俾使該導電材與該金屬層之間形成有間隙。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電穿孔貫穿該基板本體之第一表面與第二表面， 且該半導體封裝件復包括複數導電凸塊，係分別形成於該導電穿孔之第二端部上。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電體為導電膠，係自該金屬層沿著該基板本體之側面延伸至該承載件之接地墊。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該至少一接地墊係形成於該接置區外。
  8. 如申請專利範圍第1項所述之半導體封裝件，復包括封裝膠體，係形成於該承載件上，用以包覆該基板本體、金屬層、導電體及半導體元件。
  9. 一種半導體封裝件之製法，其包括：提供一具有複數導電穿孔及相對之第一表面與第二表面之基板本體，各該導電穿孔具有對應該第一表面與該第二表面之第一端部及第二端部，該導電穿孔之第一端部係外露於該基板本體之第一表面；於該基板本體之第一表面上形成一金屬層，該導電穿孔之第一端部係外露於該金屬層；將該基板本體以其第二表面設置於具有至少一接地墊之承載件上；以及電性連接半導體元件與該導電穿孔之第一端部，並藉由至少一導電體電性連接該金屬層與該承載件之至少一接地墊。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，具有該金屬層之基板本體之製備係包括： 形成絕緣層於該基板本體之第一表面上，且該絕緣層外露出該導電穿孔之第一端部；形成複數導電材於該導電穿孔之第一端部上；以及形成該金屬層於該絕緣層上，且該金屬層具有複數開孔以外露出該導電材。
  11. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該導電體為導電膠，係自該金屬層沿著該基板本體之側面延伸至該承載件之接地墊。
  12. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括自該第二表面薄化該基板本體之厚度，以外露出該導電穿孔之第二端部。
  13. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，係先藉由該導電體電性連接該金屬層與該承載件之接地墊，再於該基板本體之第一表面側電性連接該半導體元件。
  14. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，係先於該基板本體之第一表面側電性連接該半導體元件，再藉由該導電體電性連接該金屬層與該承載件之接地墊。
  15. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成封裝膠體於該承載件上，以包覆該基板本體、金屬層、導電體及半導體元件。
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