TWI812504B - 半導體封裝以及製造半導體封裝的方法 - Google Patents

半導體封裝以及製造半導體封裝的方法 Download PDF

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TWI812504B
TWI812504B TW111138934A TW111138934A TWI812504B TW I812504 B TWI812504 B TW I812504B TW 111138934 A TW111138934 A TW 111138934A TW 111138934 A TW111138934 A TW 111138934A TW I812504 B TWI812504 B TW I812504B
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interposer
printed circuit
semiconductor device
circuit board
conductive adhesive
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TW202331957A (zh
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陳俊瑋
駱彥彬
柯明吟
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香港商達發科技（香港）有限公司
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Abstract

一種半導體封裝包含印刷電路板、半導體裝置、中介層以及導電膠。印刷電路板具有至少一接地區域形成其上的上表面。半導體裝置具有至少一第一第一種類型接點形成其上的下表面。中介層設置於印刷電路板與半導體裝置之間。半導體裝置的下表面藉由導電膠而黏著至中介層的上表面，且導電膠會溢流超出中介層之上表面的邊緣而接觸於印刷電路板之上表面上的至少一接地區域。

Description

半導體封裝以及製造半導體封裝的方法
本發明係有關於半導體封裝，尤指一種透過溢流的導電膠來縮短回流路徑(return path)的半導體封裝以及相關的方法。
電流總是會從來源端流向負載端，再透過回流路徑返回至來源端，對於低頻來說，接地電流(ground current)會選擇最小電阻的路徑，對於高頻來說，接地電流會選擇最小阻抗(其包含電阻(resistive)及電抗(reactive)成分)的路徑。當交流電流通過回流路徑時，會在附近建立電場，使得整體的系統性能產生劣化，因此，回流路徑應該要適當處理以獲得更佳的訊號完整性(signal integrity)。
於第一種傳統設計中，打線接合製程(wire bonding process)用來將半導體裝置的接地連接至印刷電路板的接地，然而，這使得回流路徑被延長，進而造成效能劣化，此外，這也會增加印刷電路板上佈局區域的面積。於第二種傳統設計中，矽導通孔(through silicon via,TSV)方法被用來縮短回流路徑，然而，這是一個高成本的解決方案，主要是因為製程相當複雜。於第三種傳統設計中，可被使用的元件被侷限在那些可以直接連接至印刷電路板的接地的元件，此舉也降低了產品應用的選擇性。因此，需要一種創新的半導體封裝，其可採用低成本的解決方案來縮短回流路徑並且可適用於各種產品應用。
本發明的目的之一在於提出一種透過溢流的導電膠來縮短回流路徑的半導體封裝以及相關的方法。
在本發明的一個實施例中，揭露一種半導體封裝。該半導體封裝包含一印刷電路板、一半導體裝置、一中介層以及一導電膠。該印刷電路板具有至少一接地區域形成其上的一上表面。該半導體裝置具有至少一第一第一種類型接點形成其上的一下表面。該中介層位於該半導體裝置與該印刷電路板之間。該半導體裝置之該下表面透過該導電膠而黏著至該中介層的一上表面，以及該導電膠會溢流超出該中介層之該上表面的邊緣而接觸於該印刷電路板之該上表面上的該至少一接地區域。
在本發明的另一個實施例中，揭露一種製造一半導體封裝的方法，包含：將一中介層設置於一印刷電路板的上方，其中該印刷電路板具有至少一接地區域形成其上的一上表面；塗佈一導電膠至該中介層的一上表面，包含：允許該導電膠溢流超出該中介層之該上表面的邊緣，以接觸該印刷電路板之該上表面上的該至少一接地區域；以及透過該導電膠來將一半導體裝置堆疊在該中介層上，其中該半導體裝置具有至少一第一第一種類型接點形成其上的一下表面。
本案所揭示之解決方案可透過溢流的導電膠來使得半導體裝置的接地與印刷電路板的接地之間具有較短的回流路徑，此外，本案所揭示之解決方案是一個無需複雜矽導通孔製程的低成本解決方案。
100:半導體封裝
102:印刷電路板
104:矽中介層
106:光學裝置
108_1,108_2:導電膠
109:溢流區域
110,114,118:上表面
112:接地區域
116,120:下表面
122:第二種類型接點/p型接點/陽極
124,126:第一種類型接點/n型接點/陰極
128,130:打線
A,A’:切線
第1圖為本發明一實施例之半導體封裝的上視圖。
第2圖為第1圖所示之半導體封裝沿著切線A-A’的剖面圖。
第3圖為系統電源關閉的條件之下所獲得之量測結果的示意圖。
第4圖為系統電源開啟的條件之下所獲得之量測結果的示意圖。
第5圖為本發明一實施例之製造一半導體封裝的方法的流程圖。
在說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬技術領域具有通常知識者應可理解，硬體製造商可能會用不同的名詞來稱呼同一個元件，本說明書及申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及申請專利範圍當中所提及的“包含”及“包括”為一開放式的用語，故應解釋成“包含但不限定於”。此外，“耦接”或“耦合”一詞在此包含任何直接及間接的電性連接手段，因此，若文中描述一第一裝置耦接至一第二裝置，則代表該第一裝置可直接電性連接於該第二裝置，或者通過其它裝置和連接手段間接地電性連接至該第二裝置。
請一併參考第1圖與第2圖，第1圖為本發明一實施例之半導體封裝的上視圖，第2圖為第1圖所示之半導體封裝沿著切線A-A’的剖面圖。半導體封裝100可包含印刷電路板102、中介層(例如矽中介層(silicon interposer)104)、半導體裝置(例如光學裝置106)以及導電膠(其為包含導電成分的膠)108_1、108_2。印刷電路板102具有至少一接地區域(GND)112形成其上的上表面110，舉 例來說，接地區域112可作為接地平面(ground plane)。矽中介層104設置在印刷電路板102之上，舉例來說，但本發明並不以此為限，矽中介層104是用來協助安裝於矽中介層104上的複數個光子積體電路(photonic integrated circuit)(其可統稱為光學裝置106)的光學對準(optical alignment)，於本實施例中，矽中介層104可透過導電膠108_2而堆疊於印刷電路板102上，明確來說，矽中介層104的下表面116透過導電膠108_2而黏著至印刷電路板102的上表面110。
光學裝置106可具有一或多個第一種類型接點(first-type contact)與一或多個第二種類型接點(second-type contact)，舉例來說，第一種類型接點可以是指n型接點(n-contact)或陰極(cathode)，以及第二種類型接點可以是指p型接點(p-contact)或陽極(anode)，換言之，這些用詞”第一種類型接點”、”n型接點”與”陰極”可以互相替換，以及這些用詞”第二種類型接點”、”p型接點”與”陽極”可以互相替換。光學裝置106具有至少一第一種類型接點(第2圖中標記為”陰極”)126形成其上的下表面120。本實施例中，光學裝置106透過導電膠108_1而堆疊在矽中介層104上，明確來說，光學裝置106的下表面120透過導電膠108_1而黏著至矽中介層104的上表面114，如此一來，第一種類型接點126便會接觸導電膠108_1。此外，導電膠108_1會溢流超出矽中介層104之上表面114的邊緣而接觸於印刷電路板102之上表面110上的接地區域112，如此一來，第一種類型接點126便會透過導電膠108_1而電性連接至接地區域112，明確來說，於塗佈導電膠108_1至矽中介層104之上表面114的製程步驟中，導電膠108_1被允許溢出矽中介層104之上表面114的邊緣，如此一來，導電膠108_1便被延伸至位於矽中介層104外部的溢流區域109，並可接觸印刷電路板102上的接地區域112。因此，一條較短的回流路徑便可被建立於光學裝置106的第一種類型接點126與印刷電路板102的接地區域(例如接地平面)112之間，而不需要使用形成於矽中介層104 中的矽導通孔。
於一些實施例中，光學裝置106具有至少一第二種類型接點122與至少一第一種類型接點(第2圖標記為”陰極”)124形成其上的上表面118，如第1圖所示，光學裝置106可具有四個第二種類型接點122以及四個第一種類型接點124，其中每一第二種類型接點122透過打線(bonding wire)128而電性連接至形成於印刷電路板102之上表面110上的訊號走線(signal trace)，以及每一第一種類型接點124透過打線130而電性連接至形成於印刷電路板102之上表面110上的接地區域112。請注意，既然半導體裝置的接地(例如光學裝置的陰極)可以經由導電膠108_1所提供的回流路徑而被電性連接至印刷電路板的接地，則打線130可以根據實際設計需求而被省略。
相較於使用打線接合製程來將半導體裝置的接地(例如光學裝置的陰極)連接至印刷電路板的接地的傳統設計，本案所揭示之解決方案可使得半導體裝置的接地(例如光學裝置的陰極，像是光學裝置106的第一種類型接點126)與印刷電路板的接地之間(例如印刷電路板102的接地區域112)具有較短的回流路徑，如此可因為鄰近訊號之間較低的串音干擾(crosstalk)而得到較佳系統效能，換言之，藉由使用本案所揭示之解決方案來縮短回流路徑以得到鄰近訊號之間較低的串音干擾程度，則系統便可得到較佳的效能。無論系統電源是開啟還是關閉，透過溢流的導電膠來縮短回流路徑之半導體封裝的串音干擾程度總是會低於傳統設計的串音干擾程度。
第3圖為系統電源關閉的條件之下所獲得之量測結果的示意圖。傳統設計之串音干擾程度的量測結果由特性曲線CV1所呈現。半導體封裝100之串音 干擾程度的量測結果則由特性曲線CV2所呈現。半導體封裝100在電源關閉的狀態之下會量測到較低的串音干擾。
第4圖為系統電源開啟的條件之下所獲得之量測結果的示意圖。傳統設計之串音干擾程度的量測結果由特性曲線CV3所呈現。半導體封裝100之串音干擾程度的量測結果則由特性曲線CV4所呈現。半導體封裝100在電源開啟的狀態之下會量測到較低的串音干擾。
此外，相較於使用矽導通孔方法來縮短回流路徑的傳統設計，本案所揭示之解決方案採用導電膠溢流方法來縮短回流路徑，這允許位於光學裝置106與印刷電路板102之間的矽中介層104可以由不具有任何矽導通孔的矽中介層來加以實作，因此，本案所揭示之解決方案是一個無需複雜矽導通孔製程的低成本解決方案。
第5圖為本發明一實施例之製造一半導體封裝的方法的流程圖。假若可以得到大致上相同的結果，則步驟不一定要完全遵照第5圖所示之順序來執行。於步驟502，一中介層(例如矽中介層)被設置於一印刷電路板的上方，其中該印刷電路板具有至少一接地區域形成其上之一上表面。於步驟504，一導電膠被塗佈於該中介層之一上表面。於該導電膠被塗佈至該中介層之該上表面的製程步驟中，不禁止該導電膠溢流超出該中介層之該上表面的邊緣，換言之，該導電膠允許自由地朝向該印刷電路板之該上表面來流動，因此，該導電膠可以溢流超出該中介層之該上表面的邊緣，進而接觸於該印刷電路板之該上表面上的至少一接地區域。於步驟506，一半導體裝置(例如一光學裝置)透過該導電膠而被堆疊至該中介層上，其中該半導體裝置具有至少一第一種類型接點形 成其上之一下表面。於步驟508，一打線接合製程被執行，以將該半導體裝置(例如光學裝置)之一上表面上所形成的至少一第二種類型接點及/或至少一第一種類型接點連接至該印刷電路板。由於熟習技藝者於閱讀以上的說明書段落之後應可輕易瞭解本案所揭示之導電膠溢流方法的細節，為了簡潔起見，進一步的說明於此便不再贅述。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100:半導體封裝
102:印刷電路板
104:矽中介層
106:光學裝置
108_1,108_2:導電膠
109:溢流區域
110,114,118:上表面
112:接地區域
116,120:下表面
124,126:陰極
130:打線

Claims (8)

  1. 一種半導體封裝，包含：一印刷電路板，具有至少一接地區域形成其上的一上表面；一半導體裝置，具有至少一第一第一種類型接點形成其上的一下表面；一中介層，位於該半導體裝置與該印刷電路板之間；以及一導電膠，其中該半導體裝置之該下表面透過該導電膠而黏著至該中介層的一上表面，以及該導電膠會溢流超出該中介層之該上表面的邊緣而接觸於該印刷電路板之該上表面上的該至少一接地區域。
  2. 如請求項1所述之半導體封裝，其中該半導體裝置為一光學裝置。
  3. 如請求項1所述之半導體封裝，其中該半導體裝置具有至少一第二第一種類型接點形成其上的一上表面，以及該半導體封裝另包含：至少一打線，用以將該半導體裝置之該至少一第二第一種類型接點連接至該該印刷電路板之該至少一接地區域。
  4. 如請求項1所述之半導體封裝，其中該中介層為不具有任何矽導通孔之一矽中介層。
  5. 一種製造一半導體封裝的方法，包含：將一中介層設置於一印刷電路板的上方，其中該印刷電路板具有至少一接地區域形成其上的一上表面；塗佈一導電膠至該中介層的一上表面，包含：允許該導電膠溢流超出該中介層之該上表面的邊緣，以接觸該印刷電路 板之該上表面上的該至少一接地區域；以及透過該導電膠來將一半導體裝置堆疊在該中介層上，其中該半導體裝置具有至少一第一第一種類型接點形成其上的一下表面。
  6. 如請求項5所述之方法，其中該半導體裝置為一光學裝置。
  7. 如請求項5所述之方法，其中該半導體裝置具有至少一第二第一種類型接點形成其上的一上表面，以及該方法另包含：執行一打線接合製程，來將該半導體裝置之該至少一第二第一種類型接點連接至該該印刷電路板之該至少一接地區域。
  8. 如請求項5所述之方法，其中該中介層為不具有任何矽導通孔之一矽中介層。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200503210A (en) * 2003-07-15 2005-01-16 Siliconware Precision Industries Co Ltd Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof
TW200820389A (en) * 2006-10-18 2008-05-01 Advanced Semiconductor Eng A package and process for optoelectronic product are provided
US20090278244A1 (en) * 2008-05-12 2009-11-12 Texas Instruments Inc Ic device having low resistance tsv comprising ground connection
TW201428900A (zh) * 2013-01-03 2014-07-16 矽品精密工業股份有限公司 半導體封裝件及其製法
US20150061151A1 (en) * 2013-09-03 2015-03-05 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US20200395342A1 (en) * 2019-06-12 2020-12-17 Texas Instruments Incorporated Ic package with multiple dies
TW202123407A (zh) * 2019-12-12 2021-06-16 世界先進積體電路股份有限公司 半導體結構

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200503210A (en) * 2003-07-15 2005-01-16 Siliconware Precision Industries Co Ltd Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof
TW200820389A (en) * 2006-10-18 2008-05-01 Advanced Semiconductor Eng A package and process for optoelectronic product are provided
US20090278244A1 (en) * 2008-05-12 2009-11-12 Texas Instruments Inc Ic device having low resistance tsv comprising ground connection
TW201428900A (zh) * 2013-01-03 2014-07-16 矽品精密工業股份有限公司 半導體封裝件及其製法
US20150061151A1 (en) * 2013-09-03 2015-03-05 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US20200395342A1 (en) * 2019-06-12 2020-12-17 Texas Instruments Incorporated Ic package with multiple dies
TW202123407A (zh) * 2019-12-12 2021-06-16 世界先進積體電路股份有限公司 半導體結構

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