TW201605010A - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TW201605010A
TW201605010A TW103125448A TW103125448A TW201605010A TW 201605010 A TW201605010 A TW 201605010A TW 103125448 A TW103125448 A TW 103125448A TW 103125448 A TW103125448 A TW 103125448A TW 201605010 A TW201605010 A TW 201605010A
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Taiwan
Prior art keywords
shielding layer
package structure
package
layer
carrier
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TW103125448A
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English (en)
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TWI614870B (zh
Inventor
邱志賢
鍾興隆
張卓興
陳嘉揚
楊超雅
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矽品精密工業股份有限公司
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Priority to TW103125448A priority Critical patent/TWI614870B/zh
Priority to CN201410383922.5A priority patent/CN105304582B/zh
Priority to US14/463,999 priority patent/US9508656B2/en
Publication of TW201605010A publication Critical patent/TW201605010A/zh
Priority to US15/298,480 priority patent/US9899335B2/en
Application granted granted Critical
Publication of TWI614870B publication Critical patent/TWI614870B/zh

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Abstract

一種封裝結構，係包括：承載件、設於該承載件上之電子元件、包覆該電子元件之封裝層、形成於該封裝層上之一第一屏蔽層、以及形成於該第一屏蔽層上之至少一第二屏蔽層，且該第一屏蔽層與該第二屏蔽層係為不同材質，藉由在該封裝層上形成多層屏蔽層，以避免該電子元件受電磁波干擾。本發明復提供該封裝結構之製法。

Description

封裝結構及其製法
本發明係有關一種封裝結構，尤指一種具防電磁波干擾之封裝結構及其製法。
隨著電子產業的蓬勃發展，大部份的電子產品均朝向小型化及高速化的目標發展，尤其是通訊產業的發展已普遍運用整合於各類電子產品，例如行動電話(Cell phone)、膝上型電腦(laptop)等。然而上述之電子產品需使用高頻的射頻晶片，且射頻晶片可能相鄰設置數位積體電路、數位訊號處理器(Digital Signal Processor，簡稱DSP)或基頻晶片(BB,Base Band)，造成電磁干擾(Electromagnetic Interference，簡稱EMI)產生的現象，因此必需進行電磁屏蔽(Electromagnetic Shielding)處理。
習知避免EMI之射頻(Radio frequency，簡稱RF)模組，如第1A至1C圖所示，該射頻模組1係將複數射頻晶片11a,11b與非射頻式電子元件11電性連接在一封裝基板10上，再以係如環氧樹脂之封裝層13包覆各該射頻晶片11a,11b與該非射頻式電子元件11，並於該封裝層13上形 成一金屬薄膜14。該射頻模組1藉由該封裝層13保護該射頻晶片11a,11b、非射頻式電子元件11及封裝基板10，並避免外界水氣或污染物之侵害，且藉由該金屬薄膜14保護該些射頻晶片11a,11b免受外界EMI影響。
惟，習知射頻模組1之外圍雖可藉由包覆該金屬薄膜14以達到避免EMI之目的，但若射頻晶片11a,11b如為低頻元件，則單一金屬薄膜14作為屏障層係難以防止電磁干擾。
因此，如何克服習知技術之缺失，實為一重要課題。
為克服習知技術之種種缺失，本發明係提供一種封裝結構，係包括：一承載件；至少一電子元件，係設於該承載件上；封裝層，係包覆該電子元件；一第一屏蔽層，係形成於該封裝層上；以及至少一第二屏蔽層，係形成於該第一屏蔽層上，且該第一與第二屏蔽層係為不同材質所形成。
本發明復提供一種封裝結構之製法，係包括：提供一封裝體，該封裝體具有一承載件、設於該承載件上之至少一電子元件及包覆該電子元件之封裝層；形成一第一屏蔽層於該封裝層上；以及形成至少一第二屏蔽層於該第一屏蔽層上，且該第一屏蔽層與該第二屏蔽層係為不同材質所形成。
前述之製法中，當該封裝體具有複數該電子元件時，該封裝體定義有複數封裝單元，且各該封裝單元具有至少一該電子元件。因此，復包括先形成複數溝道於各該封裝 單元之間；再形成該第一屏蔽層於該封裝層上與各該溝道中；沿各該溝道進行切單製程，以分離各該封裝單元，且該第一屏蔽層保留於各該封裝單元上；以及之後形成該第二屏蔽層於該第一屏蔽層上。
前述之封裝結構及其製法中，該電子元件係為射頻晶片。
前述之封裝結構及其製法中，形成該第一屏蔽層之材質係為絕緣材或導電材，且形成該第二屏蔽層之材質係為導體材。
前述之封裝結構及其製法中，該溝道係貫穿該封裝層、或該溝道係延伸至該承載件內，例如，該第一屏蔽層復沿該溝道之表面形成、或該第一屏蔽層係填滿該溝道。因此，該第一屏蔽層復延伸至該承載件上，且該承載件之邊緣成為階梯部，而該第一屏蔽層復覆蓋該階梯部，使該第一屏蔽層對應該階梯部之處係呈現階梯狀、或該第一屏蔽層之側表面齊平該承載件之側表面。
由上可知，本發明之封裝結構及其製法，係藉由該封裝層上形成第一與第二屏蔽層之複數屏蔽層，以提升屏蔽功效，故可避免該電子元件受外部電磁波干擾之問題。
1‧‧‧射頻模組
10‧‧‧封裝基板
11‧‧‧非射頻式電子元件
11a,11b‧‧‧射頻晶片
13,23‧‧‧封裝層
14‧‧‧金屬薄膜
2,2’,3,3’,4,5‧‧‧封裝結構
2a,4a‧‧‧封裝體
2b‧‧‧封裝單元
20,40‧‧‧承載件
20a‧‧‧上表面
20b‧‧‧下表面
20c,23c,24a,40c‧‧‧側表面
200‧‧‧電性接觸墊
201‧‧‧絕緣保護層
21,41,51‧‧‧電子元件
210‧‧‧銲線
22,22’‧‧‧階梯部
23a‧‧‧第一表面
23b‧‧‧第二表面
24,24’‧‧‧第一屏蔽層
25,55‧‧‧第二屏蔽層
230,330‧‧‧溝道
410‧‧‧銲球
第1A至1C圖係為習知射頻模組之製法之剖面示意圖；第2A至2F圖係為本發明封裝結構之製法之第一實施例之剖面示意圖；其中，第2D’圖係為第2D圖之另一實施例，第2F’圖係為第2F圖之另一實施例； 第3A至3B圖係為本發明封裝結構之製法之第二實施例之剖面示意圖；其中，第3B’圖係為第3B圖之另一實施例；第4A至4B圖係為本發明封裝結構之製法之第三實施例之剖面示意圖；以及第5圖係為本發明封裝結構之製法之第四實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明封裝結構之製法之第一實施例之剖面示意圖。於本實施例中，所述之封裝結構2係可 發出電磁波者，例如為射頻(Radio frequency,RF)模組。
如第2A圖所示，提供一具有上表面20a及下表面20b之承載件20，再接置複數電子元件21於該承載件20之上表面20a上。
所述之承載件20之上表面20a具有線路層與絕緣保護層201，該線路層包含複數外露於該絕緣保護層201之電性接觸墊200。於本實施例中，該承載件20之種類繁多，例如，該承載件20之內部可包含介電層(圖略)、接地部(圖略)與內部線路(圖略)，且該內部線路可選擇性地電性連接該電性接觸墊200，因而該承載件20之構造並無特別限制。
所述之電子元件21係為射頻晶片或其它半導體晶片，例如：藍芽晶片或Wi-Fi(Wireless Fidelity)晶片。於本實施例中，該些電子元件21係為藍芽晶片或Wi-Fi晶片，且亦可於該承載件20之上表面20a上設置其它無影響電磁波干擾之電子元件(圖略)。
再者，該電子元件21係為打線式晶片，即藉由複數銲線210對應電性連接該承載件20之電性接觸墊200。
如第2B圖所示，形成一封裝層23於該承載件20之上表面20a上，以包覆各該電子元件21，藉以形成一封裝體2a。
於本實施例中，該封裝層23係例如為封裝膠體，其具有相對之第一表面23a及第二表面23b，且該封裝層23以其第二表面23b結合至該承載件20之上表面20a。
再者，各該電子元件21並未外露於該封裝層23之第一表面23a。
又，該封裝體2a定義有複數封裝單元2b，且各該封裝單元2b具有至少一該電子元件21。
如第2C圖所示，形成複數溝道230於各該封裝單元2b之間，以令該承載件20之部分上表面20a外露於該些溝道230。
於本實施例中，該溝道230係貫穿該封裝層23而未延伸至該承載件20之內部。
如第2D圖所示，形成第一屏蔽層24於該封裝層23之第一表面23a上。
於本實施例中，該第一屏蔽層24復沿該溝道230內之封裝層23之表面形成。
於其它實施例中，如第2D’圖所示，該第一屏蔽層24’係填滿該溝道230。
再者，形成該第一屏蔽層24之材質係為絕緣材或導電材，且其材質不同於該封裝層23之材質。
如第2E圖所示，沿該溝道230進行切單製程，以分離各該封裝單元2b，且該第一屏蔽層24保留於各該封裝單元2b上。
於本實施例中，該承載件20之邊緣係與該封裝層23構成階梯部22，使該第一屏蔽層24對應該階梯部22之處呈現階梯狀。
如第2F圖所示，形成一第二屏蔽層25於該第一屏蔽 層24與該承載件20之側表面20c上，以形成該封裝結構2，且形成該第一屏蔽層24之材質不同於形成該第二屏蔽層25之材質。
於本實施例中，形成該第二屏蔽層25之材質係為導體材，且其係以化學鍍膜的方式形成，如濺鍍(sputtering)，亦可藉由塗佈(coating)方式形成。
再者，形成該第二屏蔽層25之材質係例如銅(Cu)、鎳(Ni)、鐵(Fe)或鋁(Al)等。
又，該第二屏蔽層25可選擇性地電性連接該承載件20之接地部(因該接地部外露於該承載件20之側表面20c)。
另外，若接續第2D’圖之製程，係製作出如第2F圖所示之封裝結構2’，且該第一屏蔽層24’之側表面24a係齊平該承載件20之側表面20c。
第3A至3B圖係為本發明封裝結構之製法之第二實施例之剖面示意圖。本實施例與第一實施例之差異在於溝道之深度，其它製程大致相同。
如第3A圖所示，形成複數溝道330於各該封裝單元2b之間，且該溝道330係貫穿該封裝層23並延伸至該承載件20之內部。
如第3B及3B’圖所示，可參考第2D至2F圖所述之製程，以製成另一態樣之封裝結構3,3’。
於本實施例中，該承載件20之邊緣係成為階梯部22’，且該封裝層23未形成於該承載件20之邊緣上，使該 承載件20之邊緣伸出該封裝層23之側表面23c。
第4A至4B圖係為本發明封裝結構4之製法之第三實施例之剖面示意圖。本實施例與上述實施例之差異在於未形成溝道，其它製程大致相同。
如第4A圖所示，提供一封裝體4a，該封裝體4a具有一承載件40、設於該承載件40上之一電子元件41及包覆該電子元件21之封裝層23。
於本實施例中，該電子元件41為覆晶式晶片，即藉由複數銲球410對應電性連接至該承載件40之電性接觸墊200。
如第4B圖所示，形成一第一屏蔽層24於該封裝層23上，再形成一第二屏蔽層25於該第一屏蔽層24上。
於本實施例中，該承載件40之側表面40c齊平該封裝層23之側表面23c，即該承載件40之邊緣未伸出該封裝層23之側表面23c。
第5圖係為本發明封裝結構5之製法之第四實施例之剖面示意圖。本實施例與上述實施例之差異在於電子元件之數量與第二屏蔽層之數量，其它製程大致相同。
如第5圖所示，該封裝結構5具有複數電子元件51與複數第二屏蔽層55。
於本實施例中，各該第二屏蔽層55之材質可不相同，且相鄰之各第二屏蔽層55之材質不會相同。
本發明之製法藉由在該封裝層23外形成該第一屏蔽層24,24’與該第二屏蔽層25,55以作為電磁波屏障(EMI Shielding)，以防止該電子元件21,41,51受外部電磁波干擾，例如，防止藍芽晶片的訊號受干擾。
再者，若該電子元件21,41,51為低頻元件，則多層屏障(shielding)之結構能提供較好的防電磁干擾效果。
本發明復提供一種封裝結構2,2’,3,3’,4,5，係包括：一承載件20,40、至少一電子元件21,41,51、封裝層23、一第一屏蔽層24,24’、以及至少一第二屏蔽層25,55。
所述之封裝結構2,2’,3,3’,4,5係為射頻模組。
所述之承載件20,40係具有複數電性接觸墊200。
所述之電子元件21,41,51係設於該承載件20,40上且電性連接該些電性接觸墊200。於一實施例中，該電子元件21,41,51係為射頻晶片，例如，藍芽晶片或Wi-Fi晶片。
所述之封裝層23係設於該承載件20,40上，以包覆該電子元件21,41,51。
所述之第一屏蔽層24,24’係形成於該封裝層23上，且形成該第一屏蔽層24,24’之材質係為絕緣材。
所述之第二屏蔽層25,55係形成於該第一屏蔽層24,24’上，且形成該第一屏蔽層24,24’之材質不同於形成該第二屏蔽層25,55之材質，例如，形成該第二屏蔽層25,55之材質係為導體材。
於一實施例中，該第一屏蔽層25,55復延伸至該承載件20,40上。
於一實施例中，該承載件20,40之邊緣成為階梯部22,22’。因此，該第一屏蔽層24復覆蓋該階梯部22,22’， 且該第一屏蔽層24對應該階梯部22,22’之處係呈現階梯狀；或者，該第一屏蔽層24’復覆蓋該階梯部，且該第一屏蔽層24’之側表面24a齊平該承載件20之側表面20c。
綜上所述，本發明之封裝結構及其製法，主要藉由在該封裝層外形成多層不同材質之屏蔽層之設計，以避免該電子元件受外部電磁波干擾之問題。
再者，若該電子元件為低頻元件，則多層屏障結構能提供較好的防電磁干擾效果。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝結構
20‧‧‧承載件
20c‧‧‧側表面
21‧‧‧電子元件
23‧‧‧封裝層
24‧‧‧第一屏蔽層
25‧‧‧第二屏蔽層

Claims (18)

  1. 一種封裝結構，係包括：一承載件；至少一電子元件，係設於該承載件上；封裝層，係包覆該電子元件；一第一屏蔽層，係形成於該封裝層上；以及至少一第二屏蔽層，係形成於該第一屏蔽層上，且該第一屏蔽層與該第二屏蔽層係為不同材質所形成。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件係為射頻晶片。
  3. 如申請專利範圍第1項所述之封裝結構，其中，形成該第一屏蔽層之材質係為絕緣材或導電材。
  4. 如申請專利範圍第1項所述之封裝結構，其中，形成該第二屏蔽層之材質係為導體材。
  5. 如申請專利範圍第1項所述之封裝結構，其中，該第一屏蔽層復延伸至該承載件上。
  6. 如申請專利範圍第1項所述之封裝結構，其中，該承載件之邊緣成為階梯部。
  7. 如申請專利範圍第6項所述之封裝結構，其中，該第一屏蔽層復覆蓋該階梯部，且該第一屏蔽層對應該階梯部之處係呈現階梯狀。
  8. 如申請專利範圍第6項所述之封裝結構，其中，該第一屏蔽層復覆蓋該階梯部，且該第一屏蔽層之側表面 齊平該承載件之側表面。
  9. 一種封裝結構之製法，係包括：提供一封裝體，該封裝體具有一承載件、設於該承載件上之至少一電子元件及包覆該電子元件之封裝層；形成一第一屏蔽層於該封裝層上；以及形成至少一第二屏蔽層於該第一屏蔽層上，且該第一屏蔽層與該第二屏蔽層係為不同材質所形成。
  10. 如申請專利範圍第9項所述之封裝結構之製法，其中，該電子元件係為射頻晶片。
  11. 如申請專利範圍第9項所述之封裝結構之製法，其中，形成該第一屏蔽層之材質係為絕緣材或導電材。
  12. 如申請專利範圍第9項所述之封裝結構之製法，其中，形成該第二屏蔽層之材質係為導體材。
  13. 如申請專利範圍第9項所述之封裝結構之製法，其中，當該封裝體具有複數該電子元件時，該封裝體定義有複數封裝單元，且各該封裝單元具有至少一該電子元件。
  14. 如申請專利範圍第13項所述之封裝結構之製法，復包括：先形成複數溝道於各該封裝單元之間；再形成該第一屏蔽層於該封裝層上與各該溝道中；沿各該溝道進行切單製程，以分離各該封裝單 元，且該第一屏蔽層保留於各該封裝單元上；以及之後形成該第二屏蔽層於該第一屏蔽層上。
  15. 如申請專利範圍第14項所述之封裝結構之製法，其中，該溝道係貫穿該封裝層。
  16. 如申請專利範圍第15項所述之封裝結構之製法，其中，該溝道係延伸至該承載件內。
  17. 如申請專利範圍第14項所述之封裝結構之製法，其中，該第一屏蔽層復沿該溝道之表面形成。
  18. 如申請專利範圍第14項所述之封裝結構之製法，其中，該第一屏蔽層係填滿該溝道。
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