TW201340261A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201340261A
TW201340261A TW102101672A TW102101672A TW201340261A TW 201340261 A TW201340261 A TW 201340261A TW 102101672 A TW102101672 A TW 102101672A TW 102101672 A TW102101672 A TW 102101672A TW 201340261 A TW201340261 A TW 201340261A
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conductor
substrate
cutting
resin layer
semiconductor device
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TW102101672A
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Tsutomu Fujita
Yuusuke Takano
Masatoshi Kawato
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Toshiba Kk
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/3025—Electromagnetic shielding

Abstract

本發明可簡便地使屏蔽層與基板GND導通，且謀求屏蔽效果之提高及製造成本之降低。本發明之半導體裝置之製造方法包含：在基板10上搭載複數個半導體晶片20，且沿著包含切割線之晶片周邊部，形成上表面之高度較基板表面更高之導電體30之步驟；以樹脂層40被覆各半導體晶片20及導電體30之步驟；沿著切割線半切割樹脂層40，且使導電體30之上表面露出之步驟；以導電材料被覆藉由半切割而露出之導電體30及樹脂層40之步驟；及在切割線上切割上述基板10、上述導電體30、及導電材料40，而切出各個裝置之步驟。

Description

半導體裝置及其製造方法
本發明之實施形態係關於一種具有屏蔽功能之半導體裝置及其製造方法。
本專利申請案享有以日本專利申請案第2012-61142號(申請日期：2012年3月16日)為基礎申請案之優先權。該基礎申請案之全部內容以引用之方式併入本申請案中。
在使用於通訊機器等之半導體裝置中，為抑制向外部之無用電磁波之洩漏，使用具有屏蔽功能之半導體裝置。該半導體裝置以以屏蔽層覆蓋樹脂封裝之半導體晶片之方式構成，屏蔽層連接於基板GND。
然而，在該種之半導體裝置中，需要用以連接屏蔽層與基板GND之新步驟，從而製造成本增大。再者，屏蔽層與基板GND之連接不充分之情形較多，在該情形下有無法獲得充分之屏蔽效果之問題。
發明所欲解決之問題為提供一種可簡便地使屏蔽層與基板GND導通之半導體裝置及其製造方法。
實施形態之半導體裝置之製造方法包含：在基板上搭載複數個 半導體晶片，且沿著包含切割線之晶片周邊部，形成上表面之高度較基板表面更高之導電體之步驟；以樹脂層被覆上述各半導體晶片及上述導電體之步驟；沿著上述切割線半切割上述樹脂層，且使上述導電體之上表面露出之步驟；以導電材料被覆藉由上述半切割而露出之上述導電體及上述樹脂層之步驟；及在上述切割線上切割上述基板、上述導電體、及導電材料，而切出各個裝置之步驟。
10‧‧‧配線基板
11‧‧‧黏接劑
12‧‧‧導線
13‧‧‧表面配線
14‧‧‧電極墊
15‧‧‧貫通通道
16‧‧‧絕緣膜
17‧‧‧絕緣膜
20‧‧‧半導體晶片
30‧‧‧導電體
40‧‧‧樹脂層
50‧‧‧屏蔽層
圖1係顯示實施形態之半導體裝置之概略構成之剖面圖。
圖2(a)~(d)係顯示實施形態之半導體裝置之製造步驟之剖面圖。
圖3係顯示實施形態之半導體裝置之切割前之狀態之俯視圖。
以下，就實施形態之半導體裝置及其製造方法，一面參照圖式一面進行說明。
圖1係顯示實施形態之半導體裝置之概略構成之剖面圖。
配線基板10上，經由黏接劑11安裝有半導體晶片20。配線基板10之表面側，形成有以半導體晶片20與接線12連接之配線13。於配線基板10之背面側配置有複數個電極墊14，該等之電極墊14經由貫通通道15連接於表面側之配線13。
於配線基板10之上表面之周邊部，以包圍半導體晶片20之方式設置有導電體30。該導電體30可形成為較基板10上之半導體晶片20以外之部分更高。再者，導電體30直接連接於表面側之配線13而設置，且經由配線13連接於基板GND。
於配線基板10之上表面部，以除導電體30之上表面以外而被覆半導體晶片20及配線13等之方式以樹脂層40封裝。且，以覆蓋樹脂層40之方式設置有使用導電膏形成之屏蔽層50。該屏蔽層50直接連接於導電體30之上表面，且與基板GND電性連接。另，圖中之16、17表示 絕緣膜。
若為如此之構成，則由於設置有屏蔽層50，故可抑制無用之電磁波洩漏至外部。且，由於以沿著基板10之周邊包圍晶片20之方式設置有導電體30，故屏蔽層50與導電體30之接觸面積變大，從而可充分減小該等之接觸電阻，且可提高屏蔽層50與導電體30之密著性。藉此，可使屏蔽效果大幅提高。
接著，就本實施形態之半導體裝置之製造方法，參照圖2進行說明。
首先，如圖2(a)所示，在配線基板10上安裝有複數個半導體晶片20，且在包含切割區域之裝置周邊部形成導電體30。該導電體30之高度充分高於基板10上之半導體晶片20以外之其他之部分。又，導電體30經由配線13與基板GND電性連接。接著，以覆蓋半導體晶片20、導電體30、及配線13等之方式，以樹脂層40被覆於基板10上。
此處，導電體30如圖3之俯視圖所示，以包圍各個晶片區域之周邊之方式設置，且一部分與基板GND連接。導電體30既可為塗布導電性膏後使其硬化者，亦可為以焊接或電鍍形成者。再者，亦可以濺鍍形成。
接著，如圖2(b)所示，在切割線上利用刀片60半切割樹脂層40直至導電體30露出。此處，刀片60之寬度設為較導電體30之寬度更大者。再者，刀片60雖一直前進至接觸導電體30之位置，但稍微切割到導電體30亦無問題。
接著，如圖2(c)所示，以被覆藉由半切割而露出之導電體30之上表面及樹脂層40之方式塗布導電性膏，且以屏蔽層50覆蓋樹脂層及導電體30之表面。此時，屏蔽層50直接接觸於連接於基板GND之導電體30。其後對導電性膏進行加熱處理，若為例如如環氧系銀膏般之熱硬化性之導電性膏則進行硬化，若為例如焊膏則進行回焊。
接著，如圖2(d)所示，在切割線上切割屏蔽層50、導電體30、及配線基板10，而切出各個裝置。此時使用之刀片為較導電體30之寬度更窄者。藉此，導電體30在鄰接之晶片間分離為一方與另一方。
如此在本實施形態中，在切割區域中預先設置導電體30，以樹脂封裝後之半切割使導電體30之表面露出，在該狀態下進行用以形成屏蔽層之導電膏之塗布，藉此，可使屏蔽層50直接接觸於導電體30。且，藉由最終之切割切出各個裝置時，亦由於導電體30殘留於各個裝置之每一個，故可獲得屏蔽層50與導電體30之電性連接，且可將屏蔽層50電性連接於基板GND。
因此，如先前說明般，可使屏蔽層50之屏蔽效果大幅提高。又，藉由將導電體30之高度設為較基板10上之半導體晶片20以外之部分更高，亦可減緩半切割時之切口精度之優點。
(變化例)
另，本發明並非限定於上述之實施形態者。
在實施形態中，雖遍及基板之周邊整體形成有導電體，但導電體未必需要包圍晶片周邊整體，亦可為一部分中斷者。例如，亦可為沿著切割線分別設置於4邊者。再者，只要為沿著切割線設置者即可，可為連續亦可中斷。
又，作為搭載半導體晶片之基板，並非限於在絕緣板之表面或背面形成有配線之配線基板，亦可使用導線架。再者，作為形成屏蔽層之導電性膏，可使用銀膏、銅膏、焊膏等。再者，並非限於導電性膏者，亦可以電鍍或濺鍍形成屏蔽層。
又，在實施形態中，雖根據晶片面積之關係將導電體之寬度設為較屏蔽層之厚度更窄，但在晶片面積綽綽有餘之情形下可設為較屏蔽層之厚度更寬。即，亦可將導電體之寬度設為較半切割時之刀片之厚度更厚。
雖說明了本發明之若干個實施形態，但該等之實施形態係作為例子而提示者，並非意圖限定發明之範圍。該等實施形態可在其他之各種形態下實施，且在不脫離發明之要旨之範圍內，可進行各種省略、置換、更改。該等實施形態或其變化乃含在發明之範圍或要旨內，且同樣地含在與申請專利範圍中記載之發明及其均等之範圍內者。
10‧‧‧配線基板
20‧‧‧半導體晶片
30‧‧‧導電體
40‧‧‧樹脂層
50‧‧‧屏蔽層
60‧‧‧刀片

Claims (5)

  1. 一種半導體裝置，其特徵為包含：搭載於基板上之半導體晶片；沿著上述基板之周邊部之至少一部分設置於該基板上之導電體；以不覆蓋上述導電體之上表面之至少一部分，而覆蓋上述基板之上部及上述半導體晶片之方式設置之樹脂層；及以覆蓋上述樹脂層之方式設置，且直接連接於上述導電體之上表面之屏蔽層；且上述導電體以包圍上述半導體晶片之周邊之方式設置；上述導電體之高度設定為較上述基板上之上述半導體晶片以外之部分更高。
  2. 一種半導體裝置，其特徵為包含：搭載於基板上之半導體晶片；沿著上述基板之周邊部之至少一部分設置於該基板上之導電體；以不覆蓋上述導電體之上表面之至少一部分，而覆蓋上述基板之上部及上述半導體晶片之方式設置之樹脂層；及以覆蓋上述樹脂層之方式設置，且直接連接於上述導電體之上表面之屏蔽層。
  3. 如請求項2之半導體裝置，其中上述導電體之高度設定為較上述基板上之上述半導體晶片以外之部分更高。
  4. 一種半導體裝置之製造方法，其特徵為包含： 在基板上搭載複數個半導體晶片，且沿著包含切割線之晶片周邊部，形成上表面之高度較基板表面更高之導電體之步驟；以樹脂層被覆上述各半導體晶片及上述導電體之步驟；沿著上述切割線半切割上述樹脂層，且使上述導電體之上表面露出之步驟；以導電材料被覆藉由上述半切割而露出之上述導電體及上述樹脂層之步驟；及在上述切割線上切割上述基板、上述導電體、及上述導電材料，而切出各個裝置之步驟。
  5. 如請求項4之半導體裝置之製造方法，其中在上述半切割步驟中使用較上述導電體之寬度更寬之刀片，在切出上述裝置之步驟中使用較上述導電體之寬度更窄之刀片。
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