CN102468194A - 半导体器件封装方法及半导体器件封装 - Google Patents
半导体器件封装方法及半导体器件封装 Download PDFInfo
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Abstract
本发明披露了一种分立半导体器件封装(100),包括:引线框部(10),引线框部(10)包括凹部(14),所述凹部(14)具有实质上等于分立半导体器件(20)的厚度的深度,其中引线框部的与凹部相邻的凸出部限定了第一接触区(12);在凹部中的分立半导体器件(20),其中分立半导体器件的暴露表面(22)限定了第二接触区;保护层(30),覆盖引线框部和分立半导体器件,但不覆盖第一接触区和第二接触区;以及覆盖第一接触区和第二接触区的相应的镀层(40)。本发明还披露了一种制造这种封装的方法和一种包含这种封装的载体。
Description
技术领域
本发明涉及一种例如二极管的分立半导体器件的封装方法。
本发明进一步涉及一种通过这种方法获得的分立半导体器件。
背景技术
例如二极管的分立半导体器件在上市时典型地设置在封装中。这种封装保护分立半导体器件免受意外损坏,并提供接触(contact),以例如通过将分立半导体器件安装到印刷电路板上(PCB),将分立半导体器件集成到更大电子设备上。在已知的封装方法中,由于当前没有制造方法能以直接并且节省成本的方式在封装级别再生产小尺寸分立半导体器件,所以封装接触典型地是分立半导体器件接触的扇形展开(fan-out),即具有较大的面积。
包含分立半导体器件在内的半导体器件的不断微型化导致对应的封装尺寸也必须微型化。然而这不是微不足道的,因为封装接触的扇形展开给出了封装尺寸的下限。例如,对于二极管封装,难以将封装微型化到超过0.6mm×0.3mm×0.3mm的尺寸。这种封装通称为0603封装。这种下限主要是由封装接触的扇形展开尺寸来决定的。因此,需要一种封装方法,其能够以相对直接并且节省成本的方式促进分立半导体器件特别是二极管封装的进一步微型化。
发明内容
本发明旨在提供一种制造分立半导体器件封装的方法,该方法能够促进比0603封装更小的封装的制造。
本发明还旨在提供利用这种方法获得的分立半导体器件封装。
根据本发明的一方面,提供了一种制造分立半导体器件封装的方法,该方法包括:提供引线框;在引线框中形成凹部(recess),所述凹部具有实质上等于分立半导体器件厚度的深度,其中引线框的与凹部相邻的凸出部(raised portion)限定了第一接触区;将分立半导体器件放置在凹部中,其中分立半导体器件的有源侧面向下,分立半导体器件的暴露表面限定了第二接触区;将生成的产品模制(mold)在保护层中,使得包括第一接触区和第二接触区的表面暴露;以及用相应的镀层(plating layer)覆盖暴露的第一接触区和第二接触区。
通过确保凹部的深度接近于要放置在凹部中的分立半导体器件的厚度,可以制造非常紧凑的减小了尺寸的封装。通过以下操作可以进一步促进封装尺寸的减小:对封装进行部分模制,并在暴露的接触区上提供可软焊的(solderable)镀层,使得这些接触区可以用于将封装附着到合适的载体上而不需要接触区扇形展开,从而进一步减小封装的形状系数(form factor)。
可以通过冲压或刻蚀形成凹部,在必要时可以结合使用平坦化(flattening)步骤,以确保凹部具有合适的深度。
这种分立半导体器件的有源侧面向下放置,即,面向凹部表面。这便于使第二接触区和载体之间的接触在分立半导体封装的侧面上延伸,而在有源侧面向上的情况下,使第二接触区和载体之间的接触在分立半导体封装的侧面上延伸是不可能的,因为在接触在封装侧面上延伸的情况下,这种布置可能导致电短路。
在实施例中,将分立半导体器件放置在凹部中的步骤包括:使用导电固定剂(fixating agent)将放置的分立半导体器件与引线框互连。导电固定剂例如可以是导电粘合胶(adhesive paste)或导电晶片背涂层(wafer back coating)。可以使用非常薄的固定剂层来实现这种固定技术,从而进一步有助于限制封装的总尺寸。
在另一实施例中,所述放置步骤包括:将分立半导体器件放置在凹部中,其中分立半导体器件的有源侧向下。
有利地,刻蚀凹部的步骤包括:刻蚀引线框中的多个凹部,其中引线框的与每个凹部相邻的凸出部限定各自的第一接触区;将分立半导体器件放置在凹部中的步骤包括:在每个凹部中放置分立半导体器件,分立半导体器件的暴露表面限定了相应的第二接触区;所述方法还包括:将引线框分离成各个独立的的分立半导体器件封装。从而,可以基于单个引线框形成多个封装。
优选地,分立半导体器件的厚度与凹部的深度之间的差值小于0.1mm。这确保有效地将第一和第二接触区安装到平坦表面上。附加地或可选地,模制步骤可以用于消除凹部的深度和分立半导体器件的厚度之间的任何差异。
在另一实施例中,将生成的产品模制在保护层中的步骤包括:用保护箔(protective foil)覆盖第一接触区和第二接触区。这确保了接触区不会被模制材料(molding material)污染。在模制步骤中,例如利用标准的引线框胶带(tape),来防止引线框的背侧(即容纳分立半导体器件的有源侧的那一侧)被模制材料覆盖。
根据本发明的另一方面,提供了一种分立半导体器件封装,包括:引线框部,所述引线框部包括凹部,所述凹部具有实质上等于分立半导体器件厚度的深度,其中引线框部的与凹部相邻的凸出部限定了第一接触区;在凹部中的分立半导体器件,其中分立半导体器件的暴露表面限定了第二接触区;保护层,覆盖所述引线框部和分立半导体器件,但不覆盖第一接触区和第二接触区;以及覆盖第一接触区和第二接触区的相应的镀层。
这种封装可以制造得比当前可能的封装尺寸更小,从而有助于进一步微型化这种封装。
在实施例中,在施加保护性的模塑料(protective moldingcompound)后,用保护性的电绝缘层覆盖与包括第一接触和第二接触的表面相对的表面。可以采用漆、胶带(tape)、箔等形成电绝缘层。
在实施例中,相应的镀层分别盖住(cap)封装的相应的端面。这种结构具有的优点是,将接触区与相应的载体接触互连的焊剂可以垂直地延伸到这些镀盖(plating cap)上,从而改善了分立半导体器件封装和载体之间的接触质量。
根据本发明的另一方面,提供了一种载体,包括:第一载体接触和第二载体接触,所述载体还包括根据本发明实施例的分立半导体器件封装,其中第一载体接触通过相应的焊剂部导电连接到第一接触区,第二载体接触通过相应的焊剂部导电连接到第二接触区。这种载体例如可以是电子设备、印刷电路板、多芯片模块等等。
附图说明
通过非限制性示例并参照附图更详细地描述本发明的实施例,其中:
图1-3示意性描述了根据本发明实施例的方法多个阶段;
图4示意性描述了根据本发明实施例的完成的封装;
图5-11示意性描述了根据本发明另一实施例的方法多个阶段;
图12-13示意性描述了根据本发明另一实施例的方法多个阶段;以及
图14示意性描述了包括根据本发明实施例的分立半导体器件封装的载体。
具体实施方式
应该理解,所述附图仅仅是示意性的并且不按比例绘制。还应该理解,在所有附图中使用的相同的附图标记用于表示相同或类似的部件。
如图1所示,提供合适的引线框10,例如,诸如方形扁平无引线(QFN,quad flat no leads)或MCD引线框之类的无引线载体,其中例如通过冲压或以任何合适刻蚀方法(etching recipe)的刻蚀来提供凹部14,从而提供引线框10,其中第一接触部12被限定为与凹部14相邻。凹部14的深度等于或接近于要放置在凹部14中的分立半导体器件的厚度。例如可以通过将刻蚀或冲压步骤与随后的平坦化步骤相结合,来实现期望的凹部深度。在优选实施例中,分立半导体器件的厚度与凹部14的深度之间的差值小于0.1mm。更优选地,分立半导体器件的厚度与凹部深度相同,以至于分立半导体器件的暴露表面与第一接触部12的表面区域处于相同平面内。
为了清楚起见,图1描述了包括单个凹部14和单个接触部12的引线框10。但是,应该理解,在优选实施例中引线框10包括由凹部14和相邻的接触部12组成的阵列,使得可以基于单个引线框10形成多个封装。
下一步骤中,将分立半导体器件20放置在凹部14中。在图2中示出了这一点。分立半导体器件20具有限定第二接触区的接触表面22。如前所述,接触表面22优选地与第一接触部12的表面处于同一平面内。分立半导体器件20可以任何合适的方式与引线框10导电互连。例如,可以利用导电粘合胶或晶片背涂层形成该导电互连。如果将分立半导体器件20以其有源侧朝下的方式放置在引线框10上,这意味着要把晶片背涂层施加在分立半导体器件20的晶片顶侧。
在这个阶段,应注意到分立半导体器件20可以是任何合适的半导体器件。特别地,分立半导体器件20可以是分立二极管,当然也可以等效的应用其他的分立器件,例如晶体管。形成分立半导体器件20的晶片材料可以是任何合适的半导体材料,例如硅、SiGe等等。
优选地,分立半导体器件20的包括封密环在内的有源区保持小于0.2mm,以使得总的封装宽度限制在0.2mm。
下一步骤中,如图3所示,利用保护性树脂对生成的结构进行模制,该树脂包围引线框10和放置在引线框10上的分立半导体器件20。但是暴露出第一接触表面22和第二接触表面22。可以用任何适当的方式实现这一点,例如通过用箔覆盖这些接触表面以避免这些接触表面被保护性树脂覆盖。在模制步骤之后,可以简单地去除箔以暴露出第一接触表面12和第二接触表面22。可以使用任何适当的保护性树脂,例如环氧模塑料(epoxy molding compound)。
在将引线框10分离成各个独立的分立半导体封装之前,将保护性的电绝缘层32施加到引线框的背侧,如图3所示。这将分立半导体器件20的有源侧电绝缘,从而在将封装安装到载体上时,降低在载体和分立半导体器件20的有源侧之间发生短路的风险。特别地,第一接触表面12和分立半导体器件20通过引线框10连接,第一接触表面12与第二接触表面22之间仅通过IC的功能部件(例如二极管功能部件)连接,IC的剩余部件需要与第一接触表面12绝缘,这是电绝缘层32的用途。
在这个阶段,引线框10可以用任何适当的方式分离成独立化的(individualized)分立半导体封装,例如通过划(dicing)、切(cutting)或锯(sawing)。这一点没有被明确的示出。在独立化之后,如图4所示,为分离的分立半导体封装的接触表面12和22提供可软焊的镀层40,以最终完成分离的分立半导体器件封装100。可以用任何适当的方式的施加镀层40,例如可以使用滚镀(barrel plating)或者备选地无电镀(electroless plating)。
在图4中,仅作为非限制性示例,分立半导体器件20的第二接触表面22仅部分地被镀层40覆盖。应该理解,也可以利用镀层40覆盖整个接触表面22。这典型地由分立半导体器件20的尺寸决定。
可以采用多种适当的方式实施借助附图1-3描述的工艺步骤,下面借助附图5-12给出这些方式的非限制性示例。
图5示出了在前述具有凸出接触部12的引线框10上放置管芯20。引线框10可以包括引线框胶带31以将引线框的底部电绝缘。在将管芯20放置在引线框10上之后,可以利用保护性树脂30对得到的结构进行模制,以使得第一接触表面12和第二接触表面22保持暴露。优选地,模制步骤是借助于箔的模制步骤,其中,在模制过程中利用箔(未示出)来保护第一接触表面12和第二接触表面22,以避免这些接触表面被污染。在模制步骤后,引线框胶带31可以被去除并替换为如图3所示的电绝缘层32,例如Lintec Corporation,Japan销售的胶带,从而将引线框的底部电绝缘。
从前面的内容可以看出,可以对工艺流程进行多种变型。
在第一非限制性示例中,可以如图7所示将引线框10分成条带(strip)34。可以用任何适当的方式实现这一点,例如采用划、锯、激光切割等等。如图8示意性所示,可以将条带34顺序堆叠(应该理解,为了清楚示出的目的,条带34示出为彼此分开;实际上这些条带34是以彼此物理接触的形式堆叠的),然后将种子层(seed layer)36喷涂(sputter)到要被镀的表面上,如图9所示。可以将任何适当的金属用于这种种子层。在实施例中,在形成种子层之前,可以对用于容纳该种子层的表面进行例如等离子刻蚀,以增强种子层与表面的粘合。如图10所示,工艺继续进行到镀接触(contact plating)步骤,以形成侧面接触40,然后将条带分成各个独立的分立半导体器件封装100,如图11所示。应该理解,镀接触步骤也可以覆盖第一接触区12和第二接触区22,例如如图10所示的。
在第二非限制性示例中,如图12所示,工艺可以从图6开始继续进行,其中将引线框10和安装的管芯20分成独立组件50,然后如图13所示将这些组件放置在框60中。可以利用支撑胶带70来支撑框60,以改善独立组件50的固定。在将组件放置在框60中之后,将导电粘剂施加到要被镀的独立组件50的表面,然后执行镀接触步骤,从而最终形成分立半导体器件封装100。可以采用这种方式对组件50的两个侧面进行镀敷。
应该理解,这种镀敷工艺例如在例如多层片式电容器(chipcapacitor)或薄膜电阻等无源组件的生产中是已知。合适的镀敷材料包括锡、银、金属合金以及层堆叠(例如niAu涂复层(niAu finish)、NiPdAu)等。
返回图4时,注意图4描述了分立半导体器件封装100的优选实施例,其中镀层40盖住了封装的端部。将借助图14更详细地的描述这一点。但是,应该理解,镀层40不必须完全覆盖住封装100的端部。备选实施例,例如以下实施例也同样是可行的:镀层40仅覆盖相应的表面12和22的实施例也是可行的。
需要指出的是,利用上述方法可以制造出尺寸不超过0.4×0.2×0.2mm(长度×宽度×高度)的分立半导体器件封装100。但是,应该理解在不偏离本发明情况下,也可以实现更小尺寸和更大尺寸的封装。
传统上,将分立半导体器件封装例如沿着顶部/底部接触方向安装在诸如PCB之类的载体上,其中底部接触直接接合到载体,顶部接触是线接合接触(wire bonding contact),用于将顶部接触线接合到载体。提供线接合接触需要最小面积,该最小面积防止封装尺寸的减小超出特定的尺寸。
不同的是,通过将线接合接触替换为在分立半导体器件20和引线框10之间的导电粘合层,促进了这种封装在载体200(例如图14所示的PCB)上的侧向安装(sideway mounting),同时可软焊的镀层40提供了从封装100到外界的接触。载体200具有第一接触210和第二接触220,利用焊剂150将分立半导体器件封装100焊接到第一接触210和第二接触220上。通过提供镀层40作为分立半导体器件封装100的端部上的盖子(cap),使得焊剂150能够从相应的接触210和220垂直地延伸。分立半导体器件封装100的侧向安装允许将该封装应用到已被设计为容纳更大形状系数组件(例如0603二极管封装)的PCB上。
应注意到,上述实施例用于示例性说明而不是限制本发明,在不偏离所附权利要求的范围的情况下,本领域的熟练技术人员能够设计许多可选的实施例。在这些权利要求中,括号中的任何附图标记不应解释为限制该权利要求。术语“包括”不排除除了那些列举在权利要求中的元件或步骤之外的其他元件或步骤。在元件之前的术语“一”或“一种”不排除存在多个这种元件。可以利用包含多个不同元件的硬件来实现本发明。在列举了多个装置的设备权利要求中,这些装置中的若干装置可以由同一硬件来实施。在彼此不同的从属权利要求中所记载特定的措施不代表不能有利地使用这些措施的组合。
Claims (15)
1.一种制造分立半导体器件封装(100)的方法,包括:
提供引线框(10);
在引线框中形成凹部(14),所述凹部具有实质上等于分立半导体器件厚度的深度,其中引线框的与凹部相邻的凸出部限定了第一接触区(12);
将分立半导体器件(20)放置在凹部中,其中分立半导体器件(20)的有源区面向下,分立半导体器件的暴露表面(22)限定了第二接触区;
将生成的产品模制在保护层(30)中,使得包括第一接触区和第二接触区的表面暴露;
用保护性电绝缘层覆盖与包含第一接触区和第二接触区的表面相对的表面;以及
用相应的镀层(40)覆盖暴露的第一接触区和第二接触区。
2.根据权利要求1所述的方法,其中将分立半导体器件(20)放置在凹部(14)中的步骤包括:使用导电固定剂将放置的分立半导体器件与引线框(10)互连。
3.根据权利要求2所述的方法,其中导电固定剂是导电粘合胶或导电晶片背涂层。
4.根据权利要求1-3中任一项所述的方法,其中形成凹部的步骤是通过刻蚀或冲压来执行的。
5.根据权利要求1-4中任一项所述的方法,其中:
刻蚀凹部(14)的步骤包括:在引线框(10)中刻蚀多个凹部,其中引线框的与每个凹部相邻的凸出部限定了相应的第一接触区(12);并且
将分立半导体器件(20)放置在凹部(14)中的步骤包括:在每个凹部中放置分立半导体器件,分立半导体器件的暴露表面(22)限定了相应的第二接触区;
所述方法还包括:将引线框(10)分离成各个独立的分立半导体器件封装。
6.根据权利要求1-5中任一项所述的方法,分立半导体器件(20)的厚度与凹部(14)的深度之间的差值小于0.1mm。
7.根据权利要求1-6中任一项所述的方法,其中将生成的产品模制在保护层(30)中的步骤包括:用保护箔覆盖第一接触区(12)和第二接触区(22),以防止模制材料形成在第一接触区(12)和第二接触区(22)上。
8.根据权利要求1-7中任一项所述的方法,其中引线框(10)是方形扁平无引线QFN引线框。
9.一种分立半导体器件封装(100),包括:
引线框部(10),包括凹部(14),所述凹部(14)具有实质上等于分立半导体器件(20)厚度的深度,其中引线框部的与凹部相邻的凸出部限定了第一接触区(12);
在凹部中的分立半导体器件(20),其中分立半导体器件的暴露表面(22)限定了第二接触区;
保护层(30),覆盖所述引线框部和分立半导体器件,但不覆盖第一接触区和第二接触区;
另一保护绝缘层,在与包括第一接触区和第二接触区的表面相对的表面上;和
覆盖第一接触区和第二接触区的相应的镀层(40)。
10.根据权利要求9所述的分立半导体器件封装(100),其中分立半导体器件(20)通过导电固定剂与引线框部(10)互连。
11.根据权利要求10所述的分立半导体器件封装(100),其中导电固定剂是导电粘合胶、导电晶片背涂层或焊接互连。
12.根据权利要求9-11任一项所述的分立半导体器件封装(100),其中分立半导体器件(20)以其有源侧向下的方式放置在所述凹部(14)中。
13.根据权利要求9-12中任一项所述的分立半导体器件封装(100),其中分立半导体器件(20)的厚度与凹部(14)的深度之间的差值小于0.1mm。
14.根据权利要求9-13中任一项所述的分立半导体器件封装(100),其中相应的镀层(40)分别盖住分立半导体器件封装的相应的端面。
15.一种载体(200),包括:
第一载体接触(210)和第二载体接触(220),所述载体还包括根据权利要求9-14中任一项所述的分立半导体器件封装(100),其中第一载体接触通过相应的焊剂部(150)导电地连接到第一接触区,第二载体接触通过相应的焊剂部(150)导电地连接到第二接触区。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465553A (zh) * | 2014-01-10 | 2015-03-25 | 立昌先进科技股份有限公司 | 一种小型化表面黏着型二极体封装元件及其制法 |
CN104637914A (zh) * | 2015-02-28 | 2015-05-20 | 立昌先进科技股份有限公司 | 多功能表面黏着型电子组件及其制法 |
TWI651830B (zh) * | 2015-02-17 | 2019-02-21 | 立昌先進科技股份有限公司 | 多功能小型化表面黏著型電子元件及其製法 |
CN117542821A (zh) * | 2016-06-12 | 2024-02-09 | 安世有限公司 | 半导体器件及用于半导体器件的引线框 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2669936B1 (en) | 2012-06-01 | 2018-02-14 | Nexperia B.V. | Discrete semiconductor device package and manufacturing method |
EP3065172A1 (en) | 2015-03-06 | 2016-09-07 | Nxp B.V. | Semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6262489B1 (en) * | 1999-11-08 | 2001-07-17 | Delphi Technologies, Inc. | Flip chip with backside electrical contact and assembly and method therefor |
JP3730469B2 (ja) * | 2000-01-21 | 2006-01-05 | 新電元工業株式会社 | 樹脂封止型半導体装置及びその製造方法 |
US20060197187A1 (en) * | 2005-01-28 | 2006-09-07 | Infineon Technologies Ag | Semiconductor device and method for producing same |
US7166496B1 (en) * | 2005-08-17 | 2007-01-23 | Ciclon Semiconductor Device Corp. | Method of making a packaged semiconductor device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5814884C1 (en) * | 1996-10-24 | 2002-01-29 | Int Rectifier Corp | Commonly housed diverse semiconductor die |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
TWI250406B (en) * | 2000-03-22 | 2006-03-01 | Int Rectifier Corp | Gate driver multi-chip module |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US20050029666A1 (en) * | 2001-08-31 | 2005-02-10 | Yasutoshi Kurihara | Semiconductor device structural body and electronic device |
US6891256B2 (en) * | 2001-10-22 | 2005-05-10 | Fairchild Semiconductor Corporation | Thin, thermally enhanced flip chip in a leaded molded package |
US6946740B2 (en) * | 2002-07-15 | 2005-09-20 | International Rectifier Corporation | High power MCM package |
US6835580B1 (en) * | 2003-06-26 | 2004-12-28 | Semiconductor Components Industries, L.L.C. | Direct chip attach structure and method |
US7944031B2 (en) * | 2008-11-24 | 2011-05-17 | Fairchild Semiconductor Corporation | Leadframe-based chip scale semiconductor packages |
EP2669936B1 (en) * | 2012-06-01 | 2018-02-14 | Nexperia B.V. | Discrete semiconductor device package and manufacturing method |
-
2010
- 2010-11-12 EP EP10191081A patent/EP2453476A1/en not_active Withdrawn
-
2011
- 2011-11-10 US US13/294,126 patent/US20120286410A1/en not_active Abandoned
- 2011-11-11 CN CN2011103584133A patent/CN102468194A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6262489B1 (en) * | 1999-11-08 | 2001-07-17 | Delphi Technologies, Inc. | Flip chip with backside electrical contact and assembly and method therefor |
JP3730469B2 (ja) * | 2000-01-21 | 2006-01-05 | 新電元工業株式会社 | 樹脂封止型半導体装置及びその製造方法 |
US20060197187A1 (en) * | 2005-01-28 | 2006-09-07 | Infineon Technologies Ag | Semiconductor device and method for producing same |
US7166496B1 (en) * | 2005-08-17 | 2007-01-23 | Ciclon Semiconductor Device Corp. | Method of making a packaged semiconductor device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465553A (zh) * | 2014-01-10 | 2015-03-25 | 立昌先进科技股份有限公司 | 一种小型化表面黏着型二极体封装元件及其制法 |
CN104465553B (zh) * | 2014-01-10 | 2017-07-11 | 立昌先进科技股份有限公司 | 一种小型化表面黏着型二极体封装元件及其制法 |
TWI651830B (zh) * | 2015-02-17 | 2019-02-21 | 立昌先進科技股份有限公司 | 多功能小型化表面黏著型電子元件及其製法 |
CN104637914A (zh) * | 2015-02-28 | 2015-05-20 | 立昌先进科技股份有限公司 | 多功能表面黏着型电子组件及其制法 |
CN104637914B (zh) * | 2015-02-28 | 2018-02-13 | 立昌先进科技股份有限公司 | 多功能表面黏着型电子组件及其制法 |
CN117542821A (zh) * | 2016-06-12 | 2024-02-09 | 安世有限公司 | 半导体器件及用于半导体器件的引线框 |
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