CN104465553B - 一种小型化表面黏着型二极体封装元件及其制法 - Google Patents

一种小型化表面黏着型二极体封装元件及其制法 Download PDF

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CN104465553B
CN104465553B CN201410840628.2A CN201410840628A CN104465553B CN 104465553 B CN104465553 B CN 104465553B CN 201410840628 A CN201410840628 A CN 201410840628A CN 104465553 B CN104465553 B CN 104465553B
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diode
wiring board
crystal grain
electrode
diode crystal
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CN104465553A (zh
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连清宏
黄兴祥
黄兴材
许鸿宗
陈逸伟
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SFI Electronics Technology Inc
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SFI Electronics Technology Inc
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Abstract

本发明公开一种小型化表面黏着型二极体封装元件及其制法，使用底面设有一正电极及一负电极的二极体晶粒，且以线路板取代现有导线架进行封装及运用光耦合元件(CCD)影像定位技术进行植晶及固晶，不但制程简单及成本低帘，且适用于制成愈来愈小型化的电子元件外，还解决及突破小型化二极体晶粒使用导线架进行封装所导致的安装精度问题，所制成的小型化表面黏着型(SMD)二极体封装元件，可稳定表现小型化二极体晶粒的原有特性，没有失真或失效的问题。

Description

一种小型化表面黏着型二极体封装元件及其制法
技术领域
本发明涉及一种表面黏着型二极体封装元件，尤指一种使用线路板取代习知导线架进行封装的小型化表面黏着型二极体封装元件及其制法。
背景技术
现有技术中的IC或半导体封装元件(下文泛称电子元件)，在封装制程中必须使用导线架固定IC或半导体晶片(下文泛称半导体晶粒)，而且半导体晶粒与导线架间必须使用铅锡膏联结金线或铜线形成电性联结，再使用环氧树脂(或称封装胶)进行封胶。
完成封装后，导线架一方面成为半导体晶粒的导电内电极，另一方面也从电子元件两端(或底部)延伸出来而形成外引脚(或接触点)，进而成为电子元件连结在印刷电路板上的外电极，以成就将半导体晶粒的内部功能传输至外部衔接的电路板。
据此，导线架是半导体晶粒在封装制程中完成封装的关键性元件，要封装不同型式、不同功能或/及不同用途的半导体晶粒，就需要使用及设计不同形式的导线架进行封装。
为因应IC制程技术微小化的趋势，电子资讯产品已走向轻薄短小，电子元件尺寸愈来愈小型化，连带影响电子元件连结在印刷电路板上的技术，也从插件式演进成表面黏着式(以下简称SMD)。以使用PN型二极体晶粒制成的小型化SMD电子元件而言，如果仍旧承袭现有导线架的封装模式，在封装制程中，除有不易将小型化二极体晶粒准确安装到导线架上的缺点外，也经常发生安装失误偏离固定位置，导致有安装精度上的问题，更导致封装后的小型化电子元件的使用特性易失真、甚至失效。
所以，现有技术中的导线架封装方式，已不适用且不利于对小型化二极体晶粒进行封装。
发明内容
有鉴于此，为改进SMD电子元件的现有封装制程，本发明揭露一种小型化表面黏着型(SMD)二极体封装元件的新颖制法，尤其是使用线路板取代现有导线架进行封装，且应用感光耦合元件(CCD)影像定位技术将小型化二极体晶粒精确定位到线路板上，可解决及突破小型化二极体晶粒使用导线架进行封装所导致的安装精度问题，而且，所制成的小型化表面黏着型(SMD)二极体封装元件，可稳定表现小型化二极体晶粒的原有特性，没有失真或失效的问题，适用于制成愈来愈小型化的电子元件。
本发明的二极体晶粒，优选的基本构造，是底面设有一正电极及一负电极的二极体晶粒，或是于顶面再设有一正电极及/或一负电极的二极体晶粒。
本发明的小型化SMD二极体封装元件，优选是只使用单颗二极体晶粒，且制成长度(L)介于0.4～1.0mm、宽度(W)介于0.2～0.5mm及厚度(T)介于0.2～0.5mm的晶片型二极体封装元件。
作为优选实施例，第一种小型化SMD二极体封装元件的结构特征，包括：
一颗二极体晶粒，其底面设有一正电极及一负电极；
一片底部线路板，其板面上设有两个线路电极，且与所述二极体晶粒底面的正电极及负电极分别构成电性连接；
一个封胶体，与所述底部线路板构成一体化结构，将所述二极体晶粒及所述两个线路电极包裹在内，并且保持所述两个线路电极的一端各自延伸到该封胶体的其中一侧端面表面；及
两个外端电极，各自包覆于由所述封胶体及所述底部线路板共同构成一体化结构的其中一侧端面，且与所对应的线路电极构成电性连接。
作为优选实施例，第二种小型化SMD二极体封装元件的结构特征，具备第一种小型化SMD二极体封装元件的基本构造外，再于所述封胶体的上面进一步包括一片上盖板，其中，所述外端电极各自包覆于由所述上盖板、所述封胶体及所述底部线路板三者共同构成一体化结构的其中一侧端面，且与所对应的线路电极构成电性连接。
作为优选实施例，第三种或第四种小型化SMD二极体封装元件的结构特征，类同第一种小型化SMD二极体封装元件的基本构造，使用底面设有一正电极及一负电极、且顶面设有一正电极及/或一负电极的二极体晶粒取代，且进一步包括一片顶部线路板，以陶瓷板、塑胶板、复合材料板或具散热特性的散热板制成于其板面上设有一个或两个线路电极，且与其对应的所述二极体晶粒顶面的正电极及/或负电极构成电性连接；其中，所述外端电极各自包覆于由所述顶部线路板、所述封胶体及所述底部线路板三者共同构成一体化结构的其中一侧端面，且所述封胶体包裹所述二极体晶粒及所述底部线路板及所述顶部线路板的线路电极在内，并且保持每个所述线路电极的一端延伸到该封胶体的其中一侧端面表面与所对应的外端电极构成电性连接。
本发明的另一种小型化SMD二极体封装元件，是使用两颗或两颗以上二极体晶粒形成阵列布置，再使用单颗二极体晶粒的封装结构进行封装外，且制成长度(L)介于1.0～2.4mm、宽度(W)介于0.5～1.0mm且厚度(T)介于0.4～0.8mm的阵列型二极体封装元件。
本发明的另一主要目的在于提供一种小型化表面黏着型二极体封装元件的制法，不使用含铅锡膏的有铅制程，且适用于制成不具外引脚的小型化SMD二极体封装元件。
本发明的小型化表面黏着型二极体封装元件的制法，应用于制成所述第一种或第二种小型化SMD二极体封装元件时，包括以下步骤：
1)预制底面设有一正电极及一负电极的二极体晶粒；
2)预制板面设有薄膜或厚膜线路阵列的底部线路板；
3)对所述底部线路板的每个薄膜或厚膜线路的两端印上、沾上或点上无铅导电膏；
4)以所述底部线路板的薄膜或厚膜线路阵列中的既相邻又间隔的两个薄膜或厚膜线路的端部作为预定连接端点，通过无铅导电膏的联结，运用CCD影像定位将所述二极体晶粒的正电极及负电极连接到所述底部线路板的预定连接端点；
5)对完成固晶的底部线路板表面实施整面绝缘材料封装；
6)视需要与否，选择性进行此步骤：对所述绝缘材料的固化表面涂布一层黏着层再覆盖上一片上盖板；
7)取得切割后拥有两个预留线路电极的二极体封装元件半成品；
8)以涂布、沾银或薄膜制程，对二极体封装元件半成品的两侧端部制作与所对应的线路电极分别构成电性连接的外端电极，以制得所述小型化表面黏着型二极体封装元件。
本发明的小型化表面黏着型二极体封装元件的制法，应用于制成所述第三种或第四种小型化SMD二极体封装元件时，包括以下步骤：
1)预制底面设有一正电极及一负电极、且顶面设有一正电极及/或一负电极的二极体晶粒；
2)预制板面设有薄膜或厚膜线路阵列的底部线路板及顶部线路板；
3)对所述底部线路板的每个薄膜或厚膜线路的两端印上、沾上或点上无铅导电膏；
4)以所述底部线路板的薄膜或厚膜线路阵列中的既相邻又间隔的两个薄膜或厚膜线路的端部作为预定连接端点，通过无铅导电膏的联结，运用CCD影像定位将所述二极体晶粒底面的正电极及负电极连接到所述底部线路板的预定连接端点；
5)对所述二极体晶粒顶面的正电极及/或负电极印上、沾上或点上无铅导电膏；
6)对所述顶部线路板的薄膜或厚膜线路阵列中的每个薄膜或厚膜线路选定预定连接端点，通过步骤5)的无铅导电膏的联结，将所述顶部线路板的预定连接端点连接到与其对应的所述二极体晶粒顶面的正电极及/或负电极；
7)对完成固晶且介于所述底部线路板及所述顶部线路板之间的空间实施绝缘材料封装；
8)取得切割后拥有三个或四个预留线路电极的二极体封装元件半成品；
9)以涂布、沾银或薄膜制程，对二极体封装元件半成品的两侧端部制作与所对应的线路电极分别构成电性连接的外端电极，以制得所述小型化表面黏着型二极体封装元件。
作为优选实施例，所述二极体晶粒选自瞬态电压抑制二极体晶粒(TVS Diodedie)、萧基特二极体晶粒(Schottky Diodes die)、开关二极体晶粒(Switch Diode die)、齐纳二极晶粒体(Zener Diode die)或整流二极体晶粒(Rectifiers Diode die)的其中一种。
作为优选实施例，所述晶片型二极体封装元件或所述阵列型二极体封装元件，为瞬态电压抑制二极体、萧基特二极体、开关二极体、齐纳二极体或整流二极体的其中一种。
作为优选实施例，所述封胶体为陶瓷材料或塑胶材料。
作为优选实施例，所述底部线路板及顶部线路板是以陶瓷板、塑胶板、复合材料板或具散热特性的散热板制成，
作为优选实施例，所述外端电极的材料为银(Ag)、金(Au)、铜(Cu)、镍(Ni)、钯(Pd)或铂(Pt)单一或两种以上成分或其金属合金，且以涂布、沾覆、蒸镀薄膜或溅镀薄膜制程制成。
本发明的晶片型或阵列型二极体封装元件及其制法，具有以下有益效果：
1.与现有技术中的封装制程不同，不使用现有导线架进行封装，节省成本及制程简单；
2.在封装制程中，首创使用底面设有一正电极及一负电极的二极体晶粒，且使用(底部)线路板取代现有导线架进行封装；
3.运用CCD影像定位技术进行植晶及固晶，可解决及突破小型化二极体晶粒使用导线架进行封装所导致的安装精度问题，且适用于制成愈来愈小型化的电子元件。
附图说明
图1为本发明的晶片型二极体封装元件放大图。
图2为本发明的阵列型二极体封装元件放大图。
图3为本发明的晶片型或阵列型二极体封装元件在封装制程中使用底部线路板取代现有导线架进行二极体晶粒封装前的电极电性连接示意图。
图4为本发明的第一种或第二种晶片型或阵列型二极体封装元件的制造流程图。
图5为本发明的第一种晶片型或阵列型二极体封装元件在制程中从半成品到成品的剖面说明图。
图6为本发明的第二种晶片型或阵列型二极体封装元件在制程中从半成品到成品的剖面说明图。
图7为本发明的第三种或第四种晶片型或阵列型二极体封装元件的制造流程图。
图8为本发明的第三种晶片型或阵列型二极体封装元件在制程中从半成品到成品的剖面说明图。
图9为本发明的第四种晶片型或阵列型二极体封装元件在制程中从半成品到成品的剖面说明图。
附图标记说明：
10 二极体封装元件或晶片型二极体封装元件
20 阵列型二极体封装元件
30 二极体晶粒
31 下电极
32 上电极
40 无铅导电膏
45 黏着层
50 底部线路板
53 上盖板
55 薄膜或厚膜线路
56a、56b 线路电极
60 顶部线路板
65 薄膜或厚膜线路
66a、66b 线路电极
70 绝缘材料
73 切割线
75 封胶体
80a 外端电极
80b 外端电极
具体实施方式
本发明的小型化表面黏着型(SMD)二极体封装元件，特点在于不使用现有导线架，也没有从导线架延伸出来的外引脚，且具备半导体二极体特性。为简洁说明，本发明的小型化SMD二极体封装元件，下文将简称为二极体封装元件。
如图1及图5所示，本发明的第一种二极体封装元件10，两端具有外端电极，其基本构造，包括单颗二极体晶粒30、一片底部线路板50、两个线路电极56a及56b、一个封胶体75及两个外端电极80a及80b。
其中，所述二极体晶粒30的底面，设有两个下电极31，分别构成所述二极体晶粒30进行电性连接的正、负电极；所述线路电极56a及56b是对应所述二极体晶粒30的两个下电极31而设于该底部线路板50的板面上，且与所述二极体晶粒30的两个下电极51分别构成电性连接；所述封胶体75附着在所述底部线路板50上面，与所述底部线路板50构成一体化结构，将所述二极体晶粒30及所述线路电极56a及56b包裹在内，且保持所述线路电极56a及56b的一端各自延伸到该封胶体75的其中一侧端面表面；以及，所述外端电极80a及80b各自包覆于由所述封胶体75及所述底部线路板50共同构成一体化结构的其中一侧端面，且与所对应的线路电极56a及56b分别构成电性连接。
如图6所示，本发明的第二种二极体封装元件10，除了具备第一种二极体封装元件10的基本构造外，进一步包括一片上盖板53，且附着在所述封胶体75上面，与所述封胶体75及所述底部线路板50共同构成一体化结构，其中，所述外端电极80a及80b各自包覆于由所述上盖板53、所述封胶体75及所述底部线路板50三者共同构成一体化结构的其中一侧端面，且与所对应的线路电极56a及56b分别构成电性连接。
如图8所示，本发明的第三种二极体封装元件10，是使用具备三个电极以增加电流流通能力的二极体晶粒30，且进一步包括一片顶部线路板60；其基本构造，包括单颗二极体晶粒30、一片底部线路板50、二个线路电极56a及56b、一片顶部线路板60、一个线路电极66a、一个封胶体75及二个外端电极80a及80b。
其中，所述二极体晶粒30的底面，设有两个下电极31，分别构成所述二极体晶粒30进行电性连接的正、负电极，所述二极体晶粒30的顶面，设有一个上电极32，构成为增加电流流通能力的正电极或负电极；所述线路电极56a及56b是对应所述二极体晶粒30的两个下电极31而设于该底部线路板50的板面上，且与所述二极体晶粒30的两个下电极51分别构成电性连接；所述线路电极66a是对应所述二极体晶粒30的上电极32而设于该顶部线路板60的板面上，且与所述二极体晶粒30的上电极32构成电性连接；所述封胶体75充实地附着在所述底部线路板50及所述顶部线路板60的中间，与所述底部线路板50及所述顶部线路板60共同构成一体化结构，将所述二极体晶粒30、所述线路电极56a、56b及66a包裹在内，且保持所述线路电极56a、56b及66a的一端各自延伸到该封胶体75的其中一侧端面表面；以及，所述外端电极80a及80b各自包覆于由所述底部线路板50、所述封胶体75及所述顶部线路板60三者共同构成一体化结构的其中一侧端面，且与所对应的线路电极56a、56b及66a分别构成电性连接。
如图9所示，本发明的第四种二极体封装元件10，除了使用具备四个电极以增加电流流通能力的二极体晶粒30外，具备第三种二极体封装元件10的基本构造，包括单颗二极体晶粒30、一片底部线路板50、两个线路电极56a及56b、一片顶部线路板60、两个线路电极66a及66b、一个封胶体75及两个外端电极80a及80b。
其中，所述二极体晶粒30的底面，设有两个下电极31，分别构成所述二极体晶粒30进行电性连接的正、负电极，所述二极体晶粒30的顶面，设有两个上电极32，分别构成为增加电流流通能力的正电极及负电极；所述线路电极66a及66b是对应所述二极体晶粒30的两个上电极32而设于该顶部线路板60的板面上，且与所述二极体晶粒30的两个上电极32分别构成电性连接；而所述外端电极80a及80b各自包覆于由所述底部线路板50、所述封胶体75及所述顶部线路板60三者共同构成一体化结构的其中一侧端面，且与所对应的线路电极56a、56b、66a及66b分别构成电性连接。
以上四种二极体封装元件10都只使用单颗二极体晶粒30，本文定义为晶片型二极体封装元件10。
本发明的二极体封装元件10的另一种具体实施例，如图2所示，是使用二颗以上(包含二颗)二极体晶粒30(图未绘)且封装成二极体封装元件20，本文定义为阵列型二极体封装元件20，其基本构造，包括以所述封胶体75包裹二颗以上具备二个电极至四个电极的二极体晶粒30，且所述底部线路板50的板面上设有对应每颗二极体晶粒30的两个下电极31的线路电极56a及56b，与每颗二极体晶粒30的两个下电极31分别构成电性连接之外，且每颗二极体晶粒30各自对应的两个外端电极80a及80b，亦与所述线路电极56a及56b分别构成电性连接。
同理，所述阵列型二极体封装元件20有使用所述顶部线路板60时，所述顶部线路板60的板面上设有对应每颗二极体晶粒30的上电极32的线路电极66a或/及66b，与每颗二极体晶粒30的上电极32构成电性连接之外，且每颗二极体晶粒30各自对应的两个外端电极80a及80b，亦与所述线路电极66a或/及66b分别构成电性连接。
根据前面所述，本发明的晶片型二极体封装元件10或阵列型二极体封装元件20，为瞬态电压抑制二极体(TVS Diode)、萧基特二极体(Schottky Diodes)、开关二极体(Switch Diode)、齐纳二极体(Zener Diode)或整流二极体(Rectifiers Diode)的其中一种，但不限于此。
本发明的小型化SMD二极体封装元件制法(下文简称SMD二极体元件制法)，与现有技术中的SMD二极体封装元件的封装制程不同，适用于制作小型化的SMD二极体封装元件的关键技术，如图3所示，包括：
1.在封装制程中，使用底部线路板50取代现有导线架进行封装；
2.所述底部线路板50的板面上设有许多间隔分开且配置成阵列排列的薄膜或厚膜线路55(下文简称为薄膜或厚膜线路阵列)；
3.运用CCD影像定位技术进行点胶，对所述底部线路板50的每个薄膜或厚膜线路55的两端，精准地印上、沾上或点上无铅导电膏40；
4.运用CCD影像定位技术进行植晶及固晶，小型化的二极体晶粒30底面的正、负电极，可精确定位到所述底部线路板50上面彼此间隔且相邻的两个薄膜或厚膜线路55的端部，且通过涂布在相同定点位置的无铅导电膏40的联结，与所对应的彼此间隔且相邻的两个薄膜或厚膜线路55构成不会发生短路的电性连接。
配合图4及图5所示，本发明的SMD二极体元件制法，应用于制作本发明的第一种二极体封装元件10，其步骤包括：
1.预制底面设有(正、负电极)两个下电极31的二极体晶粒30；
2.预制板面设有薄膜或厚膜线路55阵列的底部线路板50；
3.运用CCD影像定位对所述底部线路板50的每个薄膜或厚膜线路55的两端印上、沾上或点上无铅导电膏40；
4.以所述底部线路板50上面彼此间隔且相邻的两个薄膜或厚膜线路55的端部作为预定连接端点，通过无铅导电膏40的联结，运用CCD影像定位将二极体晶粒30的两个下电极31连接到所述底部线路板50的预定连接端点；
5.对完成固晶的底部线路板50表面实施整面绝缘材料70封装；
6.运用CCD影像定位切割线73，对完成封装的二极体晶粒30进行切割，取得由原本彼此间隔且相邻的薄膜或厚膜线路55构成切割后拥有两个预留线路电极56a及56b的二极体封装元件半成品；
7.以涂布、沾银或薄膜制程，对二极体封装元件半成品的两侧端部制作外端电极80a及80b，且与所对应的线路电极56a及56b分别构成电性连接，使成品产生半导体二极体特性，即制得本发明的第一种二极体封装元件10。
配合图4及图6所示，本发明的SMD二极体元件制法，应用于制作本发明的第二种二极体封装元件10，其步骤包括：
1.预制底面设有(正、负电极)两个下电极31的二极体晶粒30；
2.预制板面设有薄膜或厚膜线路55阵列的底部线路板50；
3.运用CCD影像定位对所述底部线路板50的每个薄膜或厚膜线路55的两端印上、沾上或点上无铅导电膏40；
4.以所述底部线路板50上面彼此间隔且相邻的两个薄膜或厚膜线路55的端部作为预定连接端点，通过无铅导电膏40的联结，运用CCD影像定位将二极体晶粒30的两个下电极31连接到所述底部线路板50的预定连接端点；
5.对完成固晶的底部线路板50表面实施整面绝缘材料70封装；
6.对绝缘材料70的固化表面涂布一层黏着层45再覆盖上一片上盖板53；
7.运用CCD影像定位切割线73，对完成封装的二极体晶粒30进行切割，取得由原本彼此间隔且相邻的薄膜或厚膜线路55构成切割后拥有两个预留线路电极56a及56b的二极体封装元件半成品；
8.以涂布、沾银或薄膜制程，对二极体封装元件半成品的两侧端部制作外端电极80a及80b，且与所对应的线路电极56a及56b分别构成电性连接，使成品产生半导体二极体特性，即制得本发明的第二种二极体封装元件10。
配合图7及图8所示，本发明的SMD二极体元件制法，应用于制作本发明的第三种二极体封装元件10，其步骤包括：
1.预制底面设有(正、负电极)两个下电极31及顶面设有(正电极或负电极)一个上电极32的二极体晶粒30；
2.预制板面设有薄膜或厚膜线路55阵列的底部线路板50及板面设有薄膜或厚膜线路65阵列的顶部线路板60；
3.运用CCD影像定位对所述底部线路板50的每个薄膜或厚膜线路55的两端印上、沾上或点上无铅导电膏40；
4.以所述底部线路板50上面彼此间隔且相邻的两个薄膜或厚膜线路55的端部作为预定连接端点，通过无铅导电膏40的联结，运用CCD影像定位将二极体晶粒30的两个下电极31连接到所述底部线路板50的预定连接端点；
5.运用CCD影像定位对所述二极体晶粒30的上电极32印上、沾上或点上无铅导电膏40；
6.以所述顶部线路板60的薄膜或厚膜线路65作为预定连接端点，通过无铅导电膏40的联结，运用CCD影像定位将所述顶部线路板60的预定连接端点连接到二极体晶粒30的上电极32；
7.对完成固晶且介于底部线路板50及顶部线路板60之间的空间实施绝缘材料70封装；
8.运用CCD影像定位切割线73，对完成封装的二极体晶粒30进行切割，取得切割后拥有三个预留线路电极56a、56b及66a的二极体封装元件半成品；
9.以涂布、沾银或薄膜制程，对二极体封装元件半成品的两侧端部制作外端电极80a及80b，且与所对应的线路电极56a、56b及66a分别构成电性连接，使成品产生半导体二极体特性，即制得本发明的第三种二极体封装元件10。
配合图7及图9所示，本发明的SMD二极体元件制法，应用于制作本发明的第四种二极体封装元件10，其步骤包括：
1.预制底面设有(正、负电极)两个下电极31及顶面设有(正、负电极)两个上电极32的二极体晶粒30；
2.预制板面设有薄膜或厚膜线路55阵列的底部线路板50及板面设有薄膜或厚膜线路65阵列的顶部线路板60；
3.运用CCD影像定位对所述底部线路板50的每个薄膜或厚膜线路55的两端印上、沾上或点上无铅导电膏40；
4.以所述底部线路板50上面彼此间隔且相邻的两个薄膜或厚膜线路55的端部作为预定连接端点，通过无铅导电膏40的联结，运用CCD影像定位将二极体晶粒30的两个下电极31连接到所述底部线路板50的预定连接端点；
5.运用CCD影像定位对所述二极体晶粒30的两个上电极32分别印上、沾上或点上无铅导电膏40；
6.以所述顶部线路板60上面彼此间隔且相邻的两个薄膜或厚膜线路65的端部作为预定连接端点，通过无铅导电膏40的联结，运用CCD影像定位将所述顶部线路板60的预定连接端点分别连接到二极体晶粒30的两个上电极32；
7.对完成固晶且介于底部线路板50及顶部线路板60之间的空间实施绝缘材料70封装；
8.运用CCD影像定位切割线73，对完成封装的二极体晶粒30进行切割，取得切割后拥有四个预留线路电极56a、56b、66a及66b的二极体封装元件半成品；
9.以涂布、沾银或薄膜制程，对二极体封装元件半成品的两侧端部制作外端电极80a及80b，且与所对应的线路电极56a、56b、66a及66b分别构成电性连接，使成品产生半导体二极体特性，即制得本发明的第四种二极体封装元件10。
在本发明的SMD二极体元件制法中或其制品，所述二极体晶粒30可选自瞬态电压抑制二极体晶粒、萧基特二极体晶粒、开关二极体晶粒、齐纳二极体晶粒或整流二极体晶粒的其中一种，但不限于此。
在本发明的SMD二极体元件制法中或其制品，所述绝缘材料70或所述二极体封装元件10制品的封胶体75，可为陶瓷材料或塑胶材料，优选为使用环氧树脂。
在本发明的SMD二极体元件制法中或其制品，所述底部线路板50(或所述顶部线路板60)是选用陶瓷板、塑胶板、复合材料板或具散热特性的散热板制成，其中，所述陶瓷板可选用氧化铝板或氮化铝板；所述塑胶板可选用PE板、PP板、PC板、聚亚酰胺板或工程塑胶制成的平板；所述复合材料板可选用碳纤板或玻纤板。
如图3所示，所述底部线路板50(或所述顶部线路板60)的板面上，使用薄膜或厚膜印刷技术在板面上形成及设有分开配置(或阵列排列)的薄膜或厚膜线路55(或65)，且所述薄膜或厚膜线路55或65具备导电特性，其用途将构成本发明的二极体封装元件10的内电极。
在本发明的SMD二极体元件制法中或其制品，所述外端电极80a及80b是以涂布、沾覆、蒸镀薄膜或溅镀薄膜制制作，其材质可选自银(Ag)、金(Au)、铜(Cu)、镍(Ni)、钯(Pd)或铂(Pt)单一成分或其两种成上以上混合，或是其金属合金，但不此为限。
在本发明的SMD二极体元件制法中，所述无铅导电膏40的成分，选自含银(Ag)、锡(Sn)、铜(Cu)、金(Au)、镍(Ni)、钯(Pd)或铂(Pt)单一成分或其两种成上以上混合。
根据前面所述，本发明的SMD二极体元件制法，可解决及突破小型化二极体晶粒使用导线架进行封装所导致的安装精度问题，可应用于制作小型化SMD二极体封装元件，尤其是适用于制成如图1所示的长度(L)介于0.4～1.0mm、宽度(W)介于0.2～0.5mm且厚度(T)介于0.2～0.5mm的晶片型二极体封装元件10，优选为适用于制成尺寸规格如表1所示的晶片型二极体封装元件10。
表1
本发明的SMD二极体元件制法，也适用于制成如图2所示的长度(L)介于1.0～2.4mm、宽度(W)介于0.5～1.0mm且厚度(T)介于0.4～0.8mm的阵列型二极体封装元件20，优选为适用于制成尺寸规格如表2所示的阵列型二极体封装元件20。
表2
除此之外，本发明的SMD二极体元件制法，不使用含铅锡膏的有铅制程，可满足国际上各项环保要求。

Claims (4)

1.一种小型化表面黏着型二极体封装元件，为长度介于0.4～1.0mm、宽度介于0.2～0.5mm及厚度介于0.2～0.5mm的晶片型二极体封装元件，其特征在于，包括：
一颗二极体晶粒，其底面设有一正电极及一负电极，其顶面设有一上电极，且选自瞬态电压抑制二极体晶粒、肖特基二极体晶粒、开关二极体晶粒、齐纳二极体晶粒或整流二极体晶粒的其中一种；
一片底部线路板，以陶瓷板、塑胶板、复合材料板或具散热特性的散热板制成；其板面上设有两个线路电极，各自设于所述底部线路板的板面上，且与所述二极体晶粒底面的正电极及负电极分别构成电性连接；
一片顶部线路板，以陶瓷板、塑胶板、复合材料板或具散热特性的散热板制成；其板面上设有一个线路电极，且与所述二极体晶粒顶面的上电极构成电性连接；
一个封胶体，以陶瓷材料或塑胶材料制成，与所述底部线路板及所述顶部线路板共同构成一体化结构，以包裹所述二极体晶粒、所述底部线路板的二个线路电极及所述顶部线路板的线路电极，且保持所述底部线路板的二个线路电极及所述顶部线路板的线路电极的一端各自延伸到该封胶体的其中一侧端面表面；及
两个外端电极，以银、金、铜、镍、钯或铂单一或两种以上成分或其金属合金制成，且各自包覆于由所述封胶体、所述底部线路板及所述顶部线路板三者共同构成一体化结构的其中一侧端面，且与所对应的线路电极构成电性连接。
2.根据权利要求1所述的一种小型化表面黏着型二极体封装元件，其特征在于，所述二极体晶粒以底面设有一正电极、一负电极及顶面设有一正电极及一负电极的二极体晶粒取代，所述顶部线路板以板面上设有二个独立线路电极的顶部线路板取代，且所述顶部线路板的二个独立线路电极各自与所述二极体晶粒顶面的正电极、负电极分别构成电性连接；其中，所述外端电极各自包覆于由所述顶部线路板、所述封胶体及所述底部线路板三者共同构成一体化结构的其中一侧端面，且所述封胶体进一步包裹所述顶部线路板的二个独立线路电极在内，并且保持所述二个独立线路电极的一端各自延伸到该封胶体的其中一侧端面表面与所对应的外端电极构成电性连接。
3.一种小型化表面黏着型二极体封装元件，包含权利要求1或2的二极体晶粒及其封装结构，且以两颗或两颗以上所述二极体晶粒制成长度(L)介于1.0～2.4mm、宽度(W)介于0.5～1.0mm且厚度(T)介于0.4～0.8mm的阵列型二极体封装元件。
4.一种小型化表面黏着型二极体封装元件的制法，用于制成权利要求1或2的小型化表面黏着型二极体封装元件，其特征在于，包括以下步骤：
1)预制底面设有一正电极及一负电极、且顶面设有一正电极及/或一负电极的瞬态电压抑制二极体晶粒、肖特基二极体晶粒、开关二极体晶粒、齐纳二极体晶粒或整流二极体晶粒的其中一种；
2)以陶瓷板、塑胶板、复合材料板或具散热特性的散热板，预制板面设有薄膜或厚膜线路阵列的底部线路板及顶部线路板；
3)对所述底部线路板的每个薄膜或厚膜线路的两端印上、沾上或点上无铅导电膏；
4)以所述底部线路板的薄膜或厚膜线路阵列中的既相邻又间隔的两个薄膜或厚膜线路的端部作为预定连接端点，通过无铅导电膏的联结，运用CCD影像定位将所述二极体晶粒底面的正电极及负电极连接到所述底部线路板的预定连接端点；
5)对所述二极体晶粒顶面的正电极及/或负电极印上、沾上或点上无铅导电膏；
6)对所述顶部线路板的薄膜或厚膜线路阵列中的每个薄膜或厚膜线路选定预定连接端点，通过步骤5)的无铅导电膏的联结，将所述顶部线路板的预定连接端点连接到与其对应的所述二极体晶粒顶面的正电极及/或负电极；
7)对完成固晶且介于所述底部线路板及所述顶部线路板之间的空间实施绝缘材料封装；
8)进行切割及取得切割后拥有三个或四个预留线路电极的二极体封装元件半成品；
9)以涂布、沾银或薄膜制程，对二极体封装元件半成品的两侧端部制作与所对应的线路电极分别构成电性连接的外端电极，以制得所述小型化表面黏着型二极体封装元件。
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