TWI719517B - 一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法 - Google Patents

一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法 Download PDF

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TWI719517B
TWI719517B TW108122494A TW108122494A TWI719517B TW I719517 B TWI719517 B TW I719517B TW 108122494 A TW108122494 A TW 108122494A TW 108122494 A TW108122494 A TW 108122494A TW I719517 B TWI719517 B TW I719517B
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film
electrode
glue
die
packaging
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TW108122494A
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TW202101611A (zh
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連清宏
邱承賢
黃興材
黃興祥
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立昌先進科技股份有限公司
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Priority to TW108122494A priority Critical patent/TWI719517B/zh
Priority to JP2019132350A priority patent/JP7017192B2/ja
Priority to KR1020190090832A priority patent/KR20210002379A/ko
Priority to CN201910699977.XA priority patent/CN112151390A/zh
Priority to EP19189694.3A priority patent/EP3758061A1/en
Priority to US16/537,000 priority patent/US20200411470A1/en
Publication of TW202101611A publication Critical patent/TW202101611A/zh
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Publication of TWI719517B publication Critical patent/TWI719517B/zh

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Abstract

本發明係為一種貼片式(SMD型)單顆小尺寸及陣列型(Array Type)之晶片 半導體元件新封裝方法，利用線路板雙面連通設計方式將雙面線路板的內外層預留兩或多個連接端點，並利用鑽孔和電鍍之製程方式將內外層之線路作一連結，內層兩或多個連接端點作為內電極與半導體晶粒連結用，外層兩或多個連接端點作為外電極供SMT焊接時使用。

Description

一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝 方法
本案係關於一種晶片半導體封裝的新製作方法，尤指一種貼片式單顆小尺寸及陣列型之晶片半導體封裝的新製作方法。
半導體封裝之習知技術為導線架以環氧樹脂100封裝後，於晶片兩端留下外引腳101，方便後續焊接製程，因為製程及應用面的不同，外引腳的形式各有不同，如圖一所示。
本發明提供一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含正電極及負電極的晶粒，且提供含薄膜或厚膜雙面線路的線路板，雙面之該線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接；以烘烤方式將導電膠連接該晶粒之正電極及負電極與薄膜或厚膜雙面線路，以淋膜、塗佈、刮刀..等方法，於表面佈上整面的絕緣封裝材料，並進行絕緣封裝材料熟化處理；於該晶粒之外的位置進行切割，即可形成無外引腳的封裝結構，即完成單顆小尺寸晶片型半導體的製作；以及依據晶粒設計方式，製作成正向、反向或雙向的晶片型半導體元件。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方 法，其中該晶粒具有一上電極一下電極、一上電極二下電極、二上電極一下電極、二下電極、一上電極多下電極或多上電極一下電極…等。
本發明提供一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含提供含正電極及負電極的晶粒，且提供含薄膜或厚膜雙面線路的線路板，雙面之該線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接；利用烘烤方式將導電膠連接該晶粒之正電極及負電極與該薄膜或厚膜雙面線路的線路板；以及於上蓋板表面塗佈一層黏著劑，以連接該上蓋板與該晶粒，且以灌注方法，於內部填滿絕緣封裝材料，並進行絕緣封裝材料熟化處理。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該上蓋板為陶瓷板(例如：氧化鋁板、氮化鋁板..等)、塑膠板(例如：PE、PP、PC、聚亞醯胺、工程塑膠..等)、複合材料板(例如：碳纖板、玻纖板..等)..等，亦可黏貼散熱板，以增加散熱性能。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中含薄膜或厚膜雙面線路的該線路板更包含雙面連通設計的陣列式外電極。
本發明提供一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含三電極的晶粒，且提供含薄膜或厚膜雙面線路的至少二線路板；利用烘烤方式使用導電膠連接該晶粒之三電極與該薄膜或厚膜線路；以及以灌注方式，填充絕緣封裝材料，並進行絕緣封裝材料熟化處理。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中封裝之該貼片式單顆小尺寸及陣列型之晶片半導體元件具有電流方向一進二出或正向加接地引出、反向加接地引出及雙向+接地引出之型式。
本發明提供一種貼片式單顆小尺寸及陣列型之晶片半導體元件之 封裝方法，包含：提供含正電極及負電極的晶粒，且提供含薄膜或厚膜雙面線路的至少二線路板；利用烘烤方式將導電膠連接該晶粒之正電極及負電極與該薄膜或厚膜線路；以灌注方法，內部填滿絕緣封裝材料，並進行絕緣封裝材料熟化處理；切割後以塗佈、沾銀、薄膜製程等方式製作單邊端電極，使單邊端電極與預留電極接點進行連通，即完成單顆小尺寸晶片半導體的製作；以及進行電鍍製程以製成單顆SMD型半導體晶片元件。
本發明提供一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含三電極的晶粒，且提供含薄膜或厚膜雙面線路的至少二線路板；利用烘烤方式使用導電膠連接該晶粒之三電極與該薄膜或厚膜線路；以及以灌注方法，於內部填滿絕緣封裝材料，並進行絕緣封裝材料熟化處理；切割後以塗佈、沾銀、薄膜製程等方式製作兩端端電極，使兩端端電極與預留電極接點進行連通，即完成單顆小尺寸三電極晶片半導體的製作；以及進行電鍍製程以製成單顆SMD型半導體晶片元件。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中含薄膜或厚膜雙面線路的該線路板更包含雙面連通設計的陣列式外電極，且該線路板單面更具有連通製成的兩端水平引出電極，切割後以塗佈、沾銀、薄膜製程等方式製作兩端電極，使兩端電極與預留電極接點進行連通。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該晶片之規格包含：
Figure 108122494-A0305-02-0005-1
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該晶片種類包含TVS二極體、蕭特基二極體、開關二極體、齊納二極體、整流二極體及晶體管...等，但不限於此六種半導體晶粒，舉凡半導體晶粒植晶製程皆適用。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該線路板係將薄膜或厚膜線路製作於陶瓷板(例如：氧化鋁板、氮化鋁板..等)、塑膠板(例如：PE、PP、PC、聚亞醯胺、工程塑膠..等)及複合材料板(例如：碳纖板、玻纖板..等)..等，亦可印刷於散熱板上，以增加散熱性能。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該導電膠係各式導電膠(例如：銀膠、銀鈀膠、鈀膠、白金膠、銅膠、鎳膠、鋁膠、錫膠及錫鉛膠..等)連接半導體晶粒與印刷線路。可使用無鉛導電膠(例如：銀膠、銀鈀膠、鈀膠、白金膠、銅膠、鎳膠、鋁膠及錫膠..等)，以取代習知的有鉛錫膏，以製作出無鉛化半導體封裝產品。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該絕緣封裝材料係以淋膜、塗佈、刮刀、灌注…等方法覆蓋該晶粒、導電膠及內部線路板，達到保護晶粒電性及物性特性之功能。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該晶粒依據半導體晶粒設計方式，可製作成正向、反向或雙向的晶片型半導體元件，設計方式可為一進一出或一進二出。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該端電極係以電鍍製程或採用免電鍍即有焊性之端電極材料(例如：Ag、Au、Pd、Pt、Ag/Pd合金、Ag/Pt合金…等)，使該端電極具有焊錫性，以製成貼片式單顆小尺寸及陣列型之晶片半導體元件。
本發明的貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該薄膜線路板材料係利用薄膜製程製作(例如：濺鍍、蒸鍍、化鍍、黃光、顯影、蝕刻..等)。厚膜線路可用印刷方式製作。
100:環氧樹脂
101:外引腳
200:線路板
201:薄膜或厚膜雙面線路
210:半導體晶粒
211:正電極
212:負電極
221:導電膠
222:導電膠
230:絕緣封裝材料
290:位置
300:線路板
301:薄膜或厚膜雙面線路
310:半導體晶粒
311:正電極
312:負電極
321:導電膠
322:導電膠
330:絕緣封裝材料
340:黏著劑
350:上蓋板
390:位置
400:線路板
401:薄膜或厚膜雙面線路
402:薄膜或厚膜雙面線路
410:半導體晶粒
411:電極
412:電極
413:接地引出
421:導電膠
422:導電膠
430:絕緣封裝材料
440:導電膠
450:線路板
490:位置
500:線路板
501:薄膜或厚膜雙面線路
502:薄膜或厚膜單面線路
521:導電膠
522:導電膠
530:絕緣封裝材料
550:線路板
590:位置
600:線路板
601:薄膜或厚膜雙面線路
602:薄膜或厚膜單面線路
610:晶粒
611:電極
612:電極
613:電極
621:導電膠
622:導電膠
623:導電膠
630:絕緣封裝材料
650:線路板
690:位置
791:陣列式外電極
792:陣列式外電極
793:陣列式外電極
891:陣列式外電極
892:陣列式外電極
893:陣列式外電極
894:電極
895:電極
896:電極
897:兩端電極
898:兩端電極
899:兩端電極
第1圖為先前技術單獨使用線路板雙面連通設計製作單顆小尺寸晶片型半導體的封裝與製作方法的示意圖。
第2A至2C圖為本發明一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法的實施例之一示意圖。
第3A至3C圖為本發明一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法的實施例二之示意圖。
第4A至4C圖為本發明一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法的實施例三之示意圖。
第5A至5D圖為本發明一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法的實施例四之示意圖。
第6A至6D圖為本發明一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法的實施例五之示意圖。
第7A圖為本發明一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法的實施例六之示意圖。
第8A圖為本發明一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法的實施例七之示意圖。
為充分瞭解本發明之目的、特徵及功效，茲藉由下述具體之實施例，並配合所附之圖式，對本發明做一詳細說明，說明如後：本發明係單獨使用線路板雙面連通設計或同時使用線路板單面連通設計及線路板雙面連通設計進行半導體晶粒與電極的連接，可將線路以薄膜或厚膜印刷..等技術，製作於陶瓷板(例如：氧化鋁板、氮化鋁板..等)、塑膠板(例如：PE、PP、PC、聚亞醯胺、工程塑膠..等)、複合材料板(例如：碳纖板、玻纖板..等)..等，線路板單面連通設計則是在單面線路板上預留兩或多個連接端點並將電路以水平的方式引出至側邊；線路板雙面連通設計為在雙面線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，內層線路作為內電極與半導體晶粒連結使用，外層線路作為外電極與SMT板子連結使用。
將兩或多個連接端點上點上無鉛導電膏(例如：銀膠、銀鈀膠、鈀膠、白金膠、銅膠、鎳膠、鋁膠、錫膠..等)，並於導電膠上置放半導體晶粒，點膠 與植晶步驟均以CCD方式定位，可將半導體晶粒準確的置放於預留的電極上，連接半導體晶粒與薄膜或厚膜線路，半導體晶粒兩或多個電極可與預留內電極接點進行連通，可滿足單顆小尺寸半導體晶粒的封裝(例如：01005、0201、0402..等小尺寸之半導體晶粒的封裝)或陣列型半導體晶粒的封裝(例如：0204、0306、0405、0508、0510、0612..等陣列型之晶片半導體晶粒的封裝)。
以淋膜、塗佈、刮刀、灌注..等方法，於表面佈上整面的絕緣封裝材料，其中淋膜與塗佈絕緣封裝材料的方式，可於淋膜數次後累積一定之絕緣封裝材料厚度，而刮刀與灌注絕緣封裝材料的方式，可於刮刀與灌注1~2次後，即可累積一定之絕緣封裝材料厚度。進行絕緣封裝材料熟化處理後，即可進行切割，若單獨使用線路板雙面連通設計，切割後即完成之封裝產品即製成貼片式單顆小尺寸或陣列型半導體元件。若同時使用線路板單面連通設計及線路板雙面連通設計，切割後需再經過塗佈、沾銀、薄膜製程等方式將線路板單面連通設計之側邊引出的內電極連通至外電極，電鍍後即製成貼片式單顆小尺寸或陣列型半導體元件。
實施例一：單獨使用線路板雙面連通設計製作單顆小尺寸晶片型半導體的封裝與製作方法：(1)如圖二A所示，線路板200上含薄膜或厚膜雙面線路201，在雙面線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，半導體晶粒210含正負兩電極211及212，利用烘烤方式將導電膠221與222連接半導體晶粒之正負電極(211與212)及薄膜或厚膜雙面線路(201)，以淋膜、塗佈、刮刀..等方法，於表面佈上整面的絕緣封裝材料230，並進行絕緣封裝材料熟化處理。(2)其中薄膜線路板材料可利用薄膜製程製作(例如：濺鍍、蒸鍍、化鍍、黃光、顯影、蝕刻..等)。厚膜線路可用印刷方式製作。(3)於290位置進行切割，即可形成無外引腳的封裝結構，即完成單顆小尺寸(例如：01005、0201、0402..等)晶片型半導體的製作，製成單顆SMD型半導體元件， 如圖二B所示。(4)依據晶粒設計方式，可製作成正向、反向或雙向的晶片型半導體元件，如圖二C所示。
實施例二：單獨使用線路板雙面連通設計製作含蓋板單顆小尺寸晶片型半導體的封裝與製作方法：(1)如圖三A所示，線路板300上含薄膜或厚膜雙面線路301，在雙面線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，半導體晶粒310含正負兩電極311及312，利用烘烤方式將導電膠321與322連接半導體晶粒之正負電極(311與312)及薄膜或厚膜線路(301)。(2)於上蓋板350表面塗佈一層黏著劑340，以連接上蓋板350與半導體晶粒310，上蓋板為陶瓷板(例如：氧化鋁板、氮化鋁板..等)、塑膠板(例如：PE、PP、PC、聚亞醯胺、工程塑膠..等)、複合材料板(例如：碳纖板、玻纖板..等)..等，亦可黏貼散熱板，以增加散熱性能。(3)以灌注方法，於內部填滿絕緣封裝材料330，並進行絕緣封裝材料熟化處理。(4)於位置390進行切割，即可形成無外引腳的封裝結構。如圖三B所示。(5)依據晶粒設計方式，可製作成正向、反向或雙向的晶片型半導體元件，如圖三C所示。
實施例三：單獨使用線路板雙面連通設計製作單顆小尺寸晶片三電極型半導體的封裝與製作方法：(1)如圖四A所示，線路板400上含薄膜或厚膜雙面線路401，在雙面線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，線路板450上含薄膜或厚膜雙面線路402，在雙面線路板上預留一或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，半導體晶粒410含正負兩電極411、412及接地引出413，利用烘烤方式將導電膠421、422及440連接半導體晶粒之三電極(411、412及413)及薄膜或厚膜雙面線路(401、402)。(2)以灌注方法，於內部佈上絕緣封裝材料430，並進行絕緣封裝材料熟化處理。(3)於位置490進行切割，即可形成無外引腳的封裝結構。如圖四B所示。(4)依據晶粒設計方式，可製作成正向+接地引出、反向+接地引出及雙向+接地引出或電流一進二出的晶片型半導體元件，如圖四C所示。
實施例四：同時使用線路板單面連通設計及線路板雙面連通設計製作單顆小尺寸晶片型半導體的封裝與製作方法：(1)如圖五A所示，線路板500上含薄膜或厚膜雙面線路501，在雙面線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，線路板550上含薄膜或厚膜單面線路502，半導體晶粒510含正負兩電極511及512，利用烘烤方式將導電膠521及522連接半導體晶粒之負電極(511及512)及薄膜或厚膜雙面線路(501)及薄膜或厚膜單面線路502)。(2)以灌注方法，於內部佈上整面的絕緣封裝材料530，並進行絕緣封裝材料熟化處理。(3)於590位置進行切割，即可形成一個無外引腳及一個外引腳的封裝結構。如圖五B所示。(4)依據晶粒設計方式，可製作成正向、反向或雙向的晶片型半導體元件，如圖五C所示。(5)以塗佈、沾銀、薄膜製程等方式將線路板單面連通設計之側邊引出的內電極連通至外電極，電鍍後即製成單顆小尺寸(例如：01005、0201、0402..等)晶片型半導體SMD型半導體晶片。如圖五D所示。
實施例五：同時使用線路板單面連通設計及線路板雙面連通設計製作單顆小尺寸三電極型半導體的封裝與製作方法：(1)如圖六A所示，線路板600上含薄膜或厚膜雙面線路601，在雙面線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，線路板650上含薄膜或厚膜單面線路602，半導體晶粒610含三電極611、612及613，利用烘烤方式使用導電膠621、622與623連接半導體晶粒之三電極(611、612與613)及薄膜或厚膜雙面線路(601)及薄膜或厚膜單面線路602)。(2)以灌注方式，填充絕緣封裝材料630， 並進行絕緣封裝材料熟化處理。(3)於位置690進行切割，即可形成一個無外引腳及二個外引腳的封裝結構。如圖六B所示。(4)依據晶粒設計方式，可製作成三電極型晶片型半導體元件，如圖六C所示。此設計方式具有正向+接地引出、反向+接地引出及雙向+接地引出或電流方向一進兩出的晶片型半導體元件。(5)以塗佈、沾銀、薄膜製程等方式製作兩端電極，使兩端電極與預留電極接點進行連通，即完成單顆小尺寸(例如：01005、0201、0402..等)晶片型半導體的封裝。並於電鍍製程後，製成單顆SMD型半導體元件。如圖六D所示。
實施例六：單獨使用線路板雙面連通設計製作陣列型晶片型半導體的封裝與製作方法：(1)在雙面線路板上內外層陣列多個連接端點，利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，可製成2 X 2(791)、2 X 3(792)、2 X 4(793)…等等陣列式外電極。(2)以實施例一或二的方式進行封裝，即完成陣列型(例如：0204、0306、0405、0508..等)晶片半導體的製作，如圖七A所示。
實施例七：同時使用線路板單面連通設計及線路板雙面連通設計製作陣列型晶片半導體的封裝與製作方法：(1)線路板雙面連通設計為在雙面線路板內外層陣列多個連接端點，利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接，可製成2 X 2(891)、2 X 3(892)、2 X 4(893)…等等陣列式外電極。線路板單面連通設計為在單面線路板將內層電路以水平的方式引出至側邊如894、895、896。(2)以實施例五的方式進行封裝，切割後以塗佈、沾銀、薄膜製程等方式製作兩端電極，使兩端電極與預留電極接點進行連通如897、898、899，並於電鍍製程後即完成陣列型(例如：0204、0306、0405、0508..等)之晶片半導體的製作，如圖八A所示。
綜上所述，本發明可提供數種用於貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法。
本發明在上文中已以較佳實施例揭露，然熟習本項技術者應理解的是，該實施例僅用於描繪本發明，而不應解讀為限制本發明之範圍。應注意的是，舉凡與該實施例等效之變化與置換，均應設為涵蓋於本發明之範疇內。因此，本發明之保護範圍當以申請專利範圍所界定者為準。
200:線路板
201:薄膜或厚膜雙面線路
210:半導體晶粒
211:正電極
212:負電極
221:導電膠
222:導電膠
230:絕緣封裝材料
290:位置

Claims (17)

  1. 一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含正電極及負電極的晶粒，且提供含薄膜或厚膜雙面線路的線路板，雙面之該線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接；以烘烤方式將導電膠連接該晶粒之正電極及負電極與薄膜或厚膜雙面線路，以淋膜、塗佈、刮刀之其中一種方法，於表面佈上整面的絕緣封裝材料，並進行絕緣封裝材料熟化處理；於該晶粒之外的位置進行切割，即可形成無外引腳的封裝結構，即完成單顆小尺寸晶片型半導體的製作；以及依據晶粒設計方式，製作成正向、反向或雙向的晶片型半導體元件。
  2. 如申請專利範圍第1項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該晶粒具有一上電極一下電極、一上電極二下電極、二上電極一下電極、二下電極、一上電極多下電極或多上電極一下電極之至少一者。
  3. 一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含正電極及負電極的晶粒，且提供含薄膜或厚膜雙面線路的線路板，雙面之該線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接；利用烘烤方式將導電膠連接該晶粒之正電極及負電極與該薄膜或厚膜雙面線路的線路板；以及於上蓋板表面塗佈一層黏著劑，以連接該上蓋板與該晶粒，且以灌注方法，於內部填滿絕緣封裝材料，並進行絕緣封裝材料熟化處理。
  4. 如申請專利範圍第3項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該上蓋板為陶瓷板(氧化鋁板、氮化鋁板之至少一者)、塑膠板(PE、PP、PC、聚亞醯胺、工程塑膠之至少一者)或複合材料板(碳纖板、玻纖板之至少一者)，亦可黏貼散熱板，以增加散熱性能。
  5. 如申請專利範圍第1或3項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中含薄膜或厚膜雙面線路的該線路板更包含雙面連通設計的陣列式外電極。
  6. 一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含三電極的晶粒，且提供含薄膜或厚膜雙面線路的至少二線路板；利用烘烤方式使用導電膠連接該晶粒之三電極與該薄膜或厚膜線路；以及以灌注方式，填充絕緣封裝材料，並進行絕緣封裝材料熟化處理；其中，封裝之該貼片式單顆小尺寸及陣列型之晶片半導體元件具有電流方向一進二出或正向加接地引出、反向加接地引出及雙向+接地引出之型式。
  7. 一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含正電極及負電極的晶粒，且提供含薄膜或厚膜雙面線路的至少一線路板及含薄膜或厚膜單面線路的至少一線路板，雙面之該線路板上預留兩或多個連接端點，再利用鑽孔和電鍍的製程方法將上下兩面電路垂直方式連接；利用烘烤方式將導電膠連接該晶粒之正電極及負電極與該薄膜或厚膜線路；以灌注方法，內部填滿絕緣封裝材料，並進行絕緣封裝材料熟化處理；切割後以塗佈、沾銀、薄膜製程等方式製作單邊端電極，使單邊端電極與預留電極接點進行連通，即完成單顆小尺寸晶片半導體的製作；以及進行電鍍製程以製成單顆SMD型半導體晶片元件。
  8. 一種貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，包含：提供含三電極的晶粒，且提供含薄膜或厚膜雙面線路的至少二線路 板，且該線路板單面更具有連通製成的兩端水平引出電極；利用烘烤方式使用導電膠連接該晶粒之三電極與該薄膜或厚膜線路；以及以灌注方法，於內部填滿絕緣封裝材料，並進行絕緣封裝材料熟化處理；切割後以塗佈、沾銀、薄膜製程等方式製作兩端電極，使兩端電極與預留電極接點進行連通，即完成單顆小尺寸三電極晶片半導體的製作；以及進行電鍍製程以製成單顆SMD型半導體晶片元件。
  9. 如申請專利範圍第8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中含薄膜或厚膜雙面線路的該線路板更包含雙面連通設計的陣列式外電極。
  10. 如申請專利範圍第1、3、6、7或8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該晶片之規格包含：a.單顆01005型，2個端電極數量，長0.4mm寬0.2mm厚0.2mm，其厚度可微調；b.單顆0201型，≦3個端電極數量，長0.6mm寬0.3mm厚0.3mm，其厚度可微調；c.單顆0402，≦3個端電極數量，長1.0mm寬0.5mm厚0.5mm，其厚度可微調；d.Array Type 0204，4個端電極數量，長1.0mm寬0.5mm厚0.3mm，其厚度可微調；e.Array Type 0306，4個端電極數量，長1.6mm寬0.8mm厚0.4mm，其厚度可微調；f.Array Type 0405，4個端電極數量，長1.3mm寬1.0mm厚0.4mm，其厚度可微調；g.Array Type 0508，4個端電極數量，長2.0mm寬1.3mm厚0.5mm，其厚度可微調；h.Array Type 0510，4個端電極數量，長2.5mm寬1.3mm厚0.5mm，其厚度可微調；i.Array Type 0612，4個端電極數量，長3.0mm寬1.5mm厚0.6mm，其厚度可微調。
  11. 如申請專利範圍第1或3項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該晶片種類包含TVS二極體、蕭特基二極體、 開關二極體、齊納二極體、整流二極體及晶體管之其中一種，但不限於此六種半導體晶粒，舉凡半導體晶粒植晶製程皆適用。
  12. 如申請專利範圍第1、3、6、7或8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該線路板係將薄膜或厚膜線路製作於陶瓷板(氧化鋁板、氮化鋁板之至少一者)、塑膠板(PE、PP、PC、聚亞醯胺、工程塑膠之至少一者)或複合材料板(碳纖板、玻纖板之至少一者)，亦可印刷於散熱板上，以增加散熱性能。
  13. 如申請專利範圍第1、3、6、7或8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該導電膠係各式導電膠(銀膠、銀鈀膠、鈀膠、白金膠、銅膠、鎳膠、鋁膠、錫膠及錫鉛膠之至少一者)連接半導體晶粒與印刷線路，可使用無鉛導電膠(銀膠、銀鈀膠、鈀膠、白金膠、銅膠、鎳膠、鋁膠及錫膠之至少一者)，以取代習知的有鉛錫膏，以製作出無鉛化半導體封裝產品。
  14. 如申請專利範圍第1、3、6、7或8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該絕緣封裝材料係以淋膜、塗佈、刮刀、灌注之至少一種方法覆蓋該晶粒、導電膠及內部線路板，達到保護晶粒電性及物性特性之功能。
  15. 如申請專利範圍第1、3、6、7或8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該晶粒依據半導體晶粒設計方式，可製作成正向、反向或雙向的晶片型半導體元件，設計方式可為一進一出或一進二出。
  16. 如申請專利範圍第7或8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該端電極係以電鍍製程或採用免電鍍即有焊 性之端電極材料(Ag、Au、Pd、Pt、Ag/Pd合金、Ag/Pt合金之至少一者)，使該端電極具有焊錫性，以製成貼片式單顆小尺寸及陣列型之晶片半導體元件。
  17. 如申請專利範圍第1、3、6、7或8項所述貼片式單顆小尺寸及陣列型之晶片半導體元件之封裝方法，其中該薄膜線路板材料係利用薄膜製程製作(濺鍍、蒸鍍、化鍍、黃光、顯影、蝕刻之至少一者)，厚膜線路可用印刷方式製作。
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