TWI261902B - Chip with embedded passive components and method of manufacturing the same proposed - Google Patents

Abstract

A chip with embedded passive components and method of manufacturing the same proposed. The chip carrier include a core layer, a plurality of conductive traces formed on the core layer and an isolation layer applied over the conductive traces, so as to allow at least a passive component to embed in the chip carrier, and to be electrically connected to the conductive traces. In order to embed the passive component, opening penetrating the chip carrier is formed with at least an the chip carrier, the passive component is then disposed in the opening and electrically connected to the conductive traces via solder material. As the passive component is embedded in the chip carrier to carry a chip can be reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a wafer carrier and a method of fabricating the same, and more particularly to integrating a passive component into a thin semiconductor package to improve the electrical properties of the package and avoiding the semiconductor package structure. A wafer carrier that cannot be further thinned due to the height of the passive component and a method of manufacturing the same. [Prior Art] In the trend of high-performance and high-speed electronic information products, it is necessary to integrate passive components such as capacitors, resistors or inductors on semiconductor packages to enhance or stabilize the electrical functions of electronic products. However, as electronic products gradually move toward a trend toward thinning, in order to meet the demand for thinning, the thickness of passive components must also be gradually reduced with the semiconductor device. Therefore, how to set a sufficient number of passive components in a semiconductor package structure with a limited thickness In order to meet the product design requirements, and will not affect the layout of the substrate circuit (Routing) is a problem that the semiconductor industry needs to solve. Taking a ball grid array (BGA) semiconductor as an example, such a solder ball (Solder Ball) implanted on the bottom surface of the substrate provides a structure in which a semiconductor wafer is electrically connected to an external device such as a printed circuit board (PCB). Compared with the conventional semiconductor device based on the lead frame, the former has more input/output terminals in the same unit area to accommodate more passive components composed of electronic circuits and electronic components. And most semiconductor wafers. However, regardless of the semiconductor device based on the ball grid array or the conventional lead frame, when packaging, as shown in Figures 1 (A) and 1 (B)

1

17205 Shi Xipin.ptd Page 7 1261902, Zhe, Ming 'Shiming, B US. As shown in the case of 5,9 0 6,7 0 0, a plurality of passive components 3 are first fixed to a wafer carrier 2, and USU 0 6, 7 0 0 shown in the first (: B) diagram. For example, the wafer carrier 2 is provided with a plurality of conductive traces 6 and leads (not shown) for electrically connecting the wafer carrier 2 to the outside; and then being bonded by a semiconductor wafer. On the wafer carrier 2, a plurality of bonding wires 5 are used to electrically connect the semiconductor wafer 4 and the wafer carrier 2, and finally the semiconductor wafer 4 and the plurality of bonding wires 5 are coated with an encapsulant. The packaging process of the semiconductor device 1 is completed. However, in this packaging process, the passive component 3 is disposed outside the bonding wire region, and although the layout of the bonding wire is not affected, the bulk of the overall package is too large. The application of the US Pat. In terms of position, this will obviously limit the number of passive components 3 disposed, occupying the space of the wafer carrier 2, making the size of the semiconductor device 1 difficult to reduce, and also reducing the flexibility of the layout of the wafer carrier 2, and also avoiding the bonding wires. The occurrence of a short circuit in contact with a passive component is more detrimental to the trend of high integration of the semiconductor device 1. Moreover, taking the passive component of the 0 0 0 2 type wafer currently used in the BGA semiconductor package as an example, the passive component has a size of about 1.0 cm (mm) (length) X 0 · 5 cm (width) X 0. 5 Cm (height). However, as electronic products are thinned, the overall thickness of thin semiconductor packages tends to be less than 1 cm. If the height of the solder ball is 0.4 cm, the thickness of the encapsulant above the substrate is almost only 0.5 cm. Therefore, when the passive component of the 02-4 chip is soldered to the top of the substrate by the conventional pad bonding technology, the passive component is tinned. The thickness of the cream (0.7 cm) will exceed

Π205石夕品.ptd Page 8 1261902 V. Description of invention (3) The thickness of the encapsulated colloid (0 · 5 cm) is not applicable. Therefore, in order to meet the needs of electrical integration of thin semiconductor packages, the industry must use smaller passive components, such as the 0 2 0 1 chip passive components, but the cost of the 0 2 0 passive components is higher, and the substrate layout and The precision requirements of the pad design must be increased and are not economical. Therefore, it has become an urgent task in the industry to develop a wafer carrier suitable for carrying the current passive component of the 504 wafer and conforming to the thinning trend of the overall thickness of the semiconductor package. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a wafer carrier that can be embedded in a passive component and a method of manufacturing the same, which can reduce the height of the passive component after it is placed in the semiconductor package beyond the height of the wafer carrier. In conjunction with the thinning trend of electronic products, wafer-type passive components that can enhance electrical properties are integrated into thin semiconductor packages. Another object of the present invention is to provide a wafer carrier that can be embedded in a passive component and a method of fabricating the same, which can thin the overall thickness of the semiconductor package to meet the light and short development orientation of today's electronic information products. For the above purposes, the present invention provides a chip carrier that can be embedded in a passive component, the surface of which is coupled with at least one passive component such as a resistor, a capacitor or an inductor. The carrier member includes a core layer having at least one through portion for at least a portion of the passive component embedded therein and disposed therein; a plurality of conductive traces formed on the core layer, the conductive trace The exposed end portion and the passive component are electrically connected by a solder joint

17205石夕品.ptd Page 9 1261902 V. Description of the invention (4); and an insulating layer applied over the core layer, the insulating layer is applied to the conductive traces to form a plurality of openings, The through portion is exposed. The method for fabricating the wafer carrier of the passive component of the present invention is to first form a core layer having at least one through portion formed thereon; a plurality of conductive traces are formed on the core layer and the conductive traces are adjacent to each other Forming a plurality of conductive trace ends at the through portion; laying an insulating layer on the core layer and the conductive trace, the insulating layer having a plurality of openings to expose the core layer through portion and the conductive trace end; The core layer is connected to a passive component, wherein at least a portion of the passive component is embedded and disposed therein; and a solder is applied between the passive component and the insulating layer to expose the passive component to the insulating layer. An electrical connection relationship is formed between the ends of the conductive traces. The wafer carrier of the present invention forms a penetrating portion on the core layer for providing passive component placement, so that after the passive component is embedded in the penetrating portion, at least a portion of the passive component can be hidden into the penetrating portion, that is, when the passive component is immersed The thickness of the colloid is 0.5 mm, and the thickness of the solder is 0. 3 mm, and the height of the solder is 0. 7 mm, the thickness of the colloid at 0.5 mm will be Can accommodate this passive component, because 0.5 mm > (0.77 - 0 · 3) mm, and reduce the height of the passive component exposed to the wafer carrier, therefore, when the 0 4 0 2 wafer passive component (thickness About 0.5 cm) When a thin semiconductor package having an overall thickness of less than 1 cm is embedded, at least a portion of the passive component is received in the through portion, thereby reducing the orientation of the passive component to expose the wafer carrier, so that the degree is about 〇. 5 Dong Qi's 0 4 0 2 chip passive components can also be integrated into a thin semiconductor package with an overall thickness of less than 1 cm, eliminating the need for costly 0 2 0 1 chip passive components.

17205 .品.ptd Page 10 1261902 V. Description of invention (5) The packaging cost of moving components, and in line with the research and development orientation of today's electronic products. [Embodiment] The embodiments of the present invention will be described by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention in any way. 2 is a side elevational view of a preferred embodiment of a wafer carrier embedding a passive component of the present invention, the wafer carrier being a substrate 7 suitable for use in a ball grid array package type, and the present invention is dual The layer substrate is described as an example. The substrate 7 includes a core layer 8 having at least one through portion 9 for at least a portion of a passive component 3 embedded therein and disposed therein; a plurality of conductive traces formed on the core layer 8 The conductive trace 1 1 is electrically connected to the passive component 3 by a solder 15; and a layer is applied over the core layer 8 for covering the core layer 8 and the conductive traces. The solder resist layer 12 of the line 1 1 is applied to the conductive trace 1 1 to form a plurality of openings 14 , and the through portion 9 is exposed. Taking the two-layer substrate of the present invention as an example, as shown in FIG. 2, the material of the core layer 8 is selected from materials such as FR4 resin, glass resin, BT resin, epoxy resin, polyacetamide or cyanide. Formed with an upper surface 80 and a relative

17205 Product.ptd Page 11 1261902 One by one... One.......................................j

V. Inventive Note i6 :) I 1 lower surface 8 1, the upper surface 80 and the lower surface 8 1 are respectively patterned with a plurality of conductive traces 1 1 ' and the anger layer 8 is near the center A chip receiving area 16 is disposed; at least one through portion 9 is formed on the core layer outside the wafer receiving area 16 , and the lower end of the through portion 9 is in contact with the solder resist layer 12 2, thereby receiving the passive component 3 The through portion 9 is formed with a conductive trace end portion 1 3 a, 1 3 b exposing the solder resist layer 12 2 corresponding to the opening portion of the solder resist layer 12 . Therefore, after the passive component 3 such as the 0 4 0 2 chip resistor, the 0 0 2 2 chip capacitor or the 0 04 2 chip inductor is embedded in the core layer 8 through portion 9, the electrical connection end 3 of the passive component 3 0 and the end of the conductive traces 1 3 a, 1 3 b exposing the solder resist layer 12 can be electrically connected to each other by being attached by the solder 15 . The following is a detailed description of the detailed fabrication flow of the wafer carrier in which the passive component can be embedded in the present embodiment, from the third (A) to the third (E). As shown in FIG. 3(A), a core layer 8 having an upper surface 80 and an opposite lower surface 181 is provided, and the material is selected from the group consisting of FR 4 resin, glass resin, and BT. The core layer 8 is made of at least one penetrating portion 9 and the size of the penetrating portion 9 is slightly larger than that of the passive component 3 to be accommodated. Has a preset size. As shown in the third (B) and third (C) diagrams, a copper foil 10 (C 〇pper F 〇i 1) is applied to the lower surface 80, 8 1 of the core layer 8, respectively. After the steps of shadowing, exposure, and etching, the copper foil 10 is patterned to form a plurality of four conductive traces 11. As shown in FIG. 3(D), the surface of the core layer 8 is 80, 8 1 and the conductive trace 1 1 is made of an insulating material such as polyamidamine or epoxy resin. a solder resist layer 12, the solder resist layer 12 has a plurality of

17205石夕品.ptd Page 12 1261902 V. Description of the Invention (7) | The conductive trace 1 1 and the opening 14 of the core layer 8 through portion 9 are exposed, and the conductive trace end 1 around the through portion 9 3 a τ 1 3 b also exposes the solder resist layer 1 2 opening 14 for surface adhesion (SMT) to solder the passive component 3 in a subsequent process. As shown in FIG. 3(E), a passive element 3 such as a 0 4 0 2 type chip resistor, a 0 0 0 2 type chip capacitor or a 0 4 0 2 type chip inductor is placed in the core layer 8 through portion 9, And filling the through portion 9 with a solder 15 and attaching to the electrical connection end 30 of the passive component 3 and the exposed conductive trace end 1 3 a, 1 3 b of the solder resist layer 1 2, The passive component 3 is electrically connected to the conductive trace 11 by the solder 15 . Therefore, compared with the conventional substrate, the wafer carrier of the present invention has a through portion in the substrate core layer to accommodate the passive component, and at least a portion of the passive component can be hidden into the through portion to reduce the exposed component of the passive component. The height, as shown in Fig. 4, causes the 0 4 0 2 wafer passive component 3 having a height of 0.5 cm to be embedded inside the substrate 7 and can increase the distance between the top of the passive component 3 and the top surface of the cavity 17 I, to integrate thin semiconductor packages with an overall thickness of less than 1 centimeter, without the use of the more expensive 0 2 0 1 passive components. The wafer carrier of the present invention forms a penetrating portion on the core layer that provides a passive component, such that after the passive component is embedded in the penetrating portion, at least a portion of the passive component can be hidden into the penetrating portion, and the passive component is exposed to be exposed. φ The height of the wafer carrier reduces the height of the wafer carrier exposed by the passive component, so that the passive component of the 0 4 0 2 chip having a height of about 0.5 cm can also be integrated into a thin semiconductor package having an overall thickness of less than 1 cm. No need to use the costly 0 2 0 1 chip passive component, 俾 reduce the passive component seal

Π205石夕品.ptd Page 13 1261902

]7205石夕品.ptd Page 14 1261902 Simple description of the drawing [Simple description of the diagram] The first (A) to the first (C) diagram is a schematic layout of the wafer carrier that can be embedded in the passive component; 2 is a cross-sectional view of a wafer carrier in which a passive component can be embedded in the present invention, and a passive component embedded in a top view of the through portion; FIGS. 3(A) to 3(E) are diagrams in which the passive component can be embedded in the present invention. A schematic diagram of the overall fabrication flow of the wafer carrier; and FIG. 4 is a schematic cross-sectional view of the wafer carrier of the present invention. 1 semiconductor device 10 copper foil 11,6 conductive trace 12 solder resist layer 13a, 13b conductive trace end 14 opening 15 solder 16 wafer preset 2 wafer carrier 3 passive component 30 electrical connection 4 semiconductor wafer 5 bonding wire 7 Substrate 8 core layer 80 layer upper surface 81 core layer lower surface 9 through portion 17 cavity top surface I between the passive component and the top surface of the cavity

17205 Shi Xipin.ptd Page 15

Claims (1)

1261902 VI. φ Patent Range 1. A wafer carrier manufacturing method capable of embedding a passive component, comprising the steps of: forming a core layer having at least one penetration portion formed thereon; forming a plurality of conductive traces on the core layer a wire, and the conductive trace is formed with a plurality of conductive trace ends adjacent to the through portion; an insulating layer is disposed on the core layer and the conductive trace to make the core layer penetrating portion and the conductive trace end Exposed to the insulating layer; a passive component is embedded in the through portion, at least a portion of the passive component is embedded in the core layer penetration portion and disposed therein; and a through portion embedded with the passive component is coated The solder is used to form an electrical connection between the passive component and the end of the conductive trace. 2. The wafer carrier manufacturing method according to claim 1, wherein the driven component is a type 104 chip capacitor. 3. The wafer carrier manufacturing method of claim 1, wherein the driven component is a 104-type chip resistor. 4. The wafer carrier manufacturing method of claim 1, wherein the driven component is a 104-type chip inductor. 5. The wafer carrier manufacturing method of claim 1, wherein the wafer carrier is a ball grid array substrate. 6. The method according to claim 1, wherein the core layer is made of a material selected from the group consisting of FR4 resin, glass resin, enamel resin, epoxy resin, polyethyleneamine or cyanide. 7. The method of claim 1, wherein the size of the through portion is slightly larger than the size of the passive component. [7205] Shi Xipin. ptd Page 16 1261902 6. Patent application scope 8. The wafer carrier manufacturing method of claim 1, wherein the insulating layer is a solder resist layer. 9. The wafer carrier manufacturing method of claim 8, wherein the solder resist layer material comprises a polymethyleneamine. The wafer carrier manufacturing method of claim 8, wherein the solder resist layer material comprises an epoxy resin. 1 1. A wafer carrier embedding a passive component, comprising: a core layer having at least one through portion for at least a portion of a passive component embedded therein and disposed therein; a majority of the core layer is formed a conductive trace, the conductive trace and the passive component are electrically connected by a solder; and an insulating layer applied to the core layer and the conductive trace, the insulating layer corresponding to the through portion An opening is formed to expose a portion of the conductive traces around the core through portion and the through portion. The wafer carrier of claim 11, wherein the passive component is a 104-type wafer capacitor. The wafer carrier of claim 11, wherein the passive component is a type 104 chip resistor. The wafer carrier of claim 11, wherein the passive component is a 104-type chip inductor. The wafer carrier of claim 11, wherein the wafer carrier is a ball grid array substrate. 1 6. The wafer carrier of claim 11, wherein the core layer ]7205石夕品.ptd Page 17 1261902 VI. Patent application range It is made of FR4 resin, glass resin, BT resin, epoxy resin, polyethyleneamine or cyanide. The wafer carrier of claim 11, wherein the through portion is slightly larger than the size of the passive component. The wafer carrier of claim 11, wherein the insulating layer is a solder resist layer. The wafer carrier of claim 18, wherein the solder resist layer material comprises a polymethyleneamine. The wafer carrier of claim 18, wherein the solder resist layer material comprises an epoxy resin. ]7205 石夕品.ptd第18页