JP2004200665A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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JP2004200665A
JP2004200665A JP2003394813A JP2003394813A JP2004200665A JP 2004200665 A JP2004200665 A JP 2004200665A JP 2003394813 A JP2003394813 A JP 2003394813A JP 2003394813 A JP2003394813 A JP 2003394813A JP 2004200665 A JP2004200665 A JP 2004200665A
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semiconductor device
passive component
semiconductor element
semiconductor
adhesive layer
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JP2004200665A6 (en
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Hitoshi Kawaguchi
均 川口
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J-SIP WALTON KK
Ibiden Co Ltd
Disco Corp
Toppan Inc
Resonac Corp
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J-SIP WALTON KK
Ibiden Co Ltd
Hitachi Chemical Co Ltd
Toppan Printing Co Ltd
Disco Abrasive Systems Ltd
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Priority to JP2003394813A priority Critical patent/JP2004200665A/en
Publication of JP2004200665A publication Critical patent/JP2004200665A/en
Publication of JP2004200665A6 publication Critical patent/JP2004200665A6/en
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for miniaturizing a semiconductor device containing a semiconductor element and a passive part. <P>SOLUTION: A semiconductor element 104 is mounted on an interposer 105, and a passive part 102 is mounted on them via an adhesive layer 114. The passive part 102 and the semiconductor element 104 are connected with an electrode pad on the interposer 105 via bonding wires 109 and 107. The adhesive layer 114 is formed into the nearly same size as that of the adhesive surface of the passive part 102. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

本発明は、半導体装置およびその製造方法に関する。本発明は、とくに、半導体素子および受動部品を含む半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the same. The present invention particularly relates to a semiconductor device including a semiconductor element and a passive component, and a method for manufacturing the same.

近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできている。これらの電子機器に使用される半導体パッケージは、小型化かつ多ピン化してきており、また、半導体パッケージを含めた電子部品を実装する、実装用基板も小型化してきている。さらには電子機器への収納性を高めるため、リジット基板とフレキシブル基板を積層し一体化して、折り曲げを可能としたリジットフレックス基板が、実装用基板として使われるようになってきている。   2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages used in these electronic devices have become smaller and have more pins, and mounting substrates for mounting electronic components including the semiconductor packages have also become smaller. Furthermore, in order to enhance the storage in electronic devices, a rigid-flex board, in which a rigid board and a flexible board are laminated and integrated to be bent, has been used as a mounting board.

半導体パッケージの小型化に伴い、回路基板上にチップを実装したＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）やＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）等のエリア実装型の新しい方式が提案されている。これらの半導体パッケージにおいて、半導体チップの電極とサブストレートの端子との電気的接続方法として、ワイヤボンディング方式やＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）方式、ＦＣ（Ｆｒｉｐ Ｃｈｉｐ）方式等が用いられている。ここで、サブストレートは、半導体パッケージ用基板とも呼ばれ、プラスチックやセラミックス等各種材料を使って構成され、従来型半導体パッケージのリードフレームの機能を有する。   With the miniaturization of the semiconductor package, a new method of area mounting type such as BGA (Ball Grid Array) or CSP (Chip Scale Package) in which a chip is mounted on a circuit board has been proposed. In these semiconductor packages, a wire bonding method, a TAB (Tape Automated Bonding) method, an FC (Flip Chip) method, or the like is used as an electrical connection method between the electrode of the semiconductor chip and the terminal of the substrate. Here, the substrate is also called a substrate for a semiconductor package, is made of various materials such as plastic and ceramics, and has a function of a lead frame of a conventional semiconductor package.

しかし、上記のような従来の工法では一つの半導体パッケージに対し半導体素子を一つしか収納できないため、半導体パッケージの小型化には自ずと限界があった。このため、複数個の半導体素子を積み重ねて一つの半導体パッケージの内部に収納することにより、実装密度を向上させる手法が提案されている（たとえば特許文献１）。この際、何らかの手法で半導体素子をリードフレームやサブストレートと接続する必要がある。現在、このような接続手法としては、ワイヤボンディングやフリップチップ方式が用いられている。   However, in the conventional method as described above, only one semiconductor element can be accommodated in one semiconductor package, and there is naturally a limit to miniaturization of the semiconductor package. For this reason, a method has been proposed in which a plurality of semiconductor elements are stacked and housed in one semiconductor package to improve the mounting density (for example, Patent Document 1). At this time, it is necessary to connect the semiconductor element to a lead frame or a substrate by some method. At present, as such a connection method, a wire bonding or a flip chip method is used.

また、半導体パッケージをプリント配線板に実装する際には、その周辺にプルアップ抵抗、プルダウン抵抗、カップリングコンデンサ等の受動部品を配置しなくてはならない。図１は、プリント配線板３の上にＢＧＡの半導体パッケージ１および受動部品２が載置された構成を示す図である。図２は、有機インターポーザー５の表面に半導体素子４および受動部品２が載置され、有機インターポーザー５の裏面にハンダボール６が設けられた構成を示す図である。   Further, when mounting a semiconductor package on a printed wiring board, passive components such as a pull-up resistor, a pull-down resistor, and a coupling capacitor must be arranged around the package. FIG. 1 is a diagram showing a configuration in which a BGA semiconductor package 1 and a passive component 2 are mounted on a printed wiring board 3. FIG. 2 is a diagram showing a configuration in which the semiconductor element 4 and the passive component 2 are mounted on the front surface of the organic interposer 5 and the solder balls 6 are provided on the back surface of the organic interposer 5.

たとえば特許文献２には、回路基板上に半導体集積回路のベアチップやコンデンサ、コイル等の受動部品を含む複数の回路素子を配置し、これらを封止樹脂により封止した回路モジュールが記載されている。これにより、回路モジュールの小型化を図っている。   For example, Patent Literature 2 describes a circuit module in which a plurality of circuit elements including passive components such as a bare chip, a capacitor, and a coil of a semiconductor integrated circuit are arranged on a circuit board, and these are sealed with a sealing resin. . Thus, the size of the circuit module is reduced.

また、たとえば特許文献３には、図３に示すように、有機インターポーザー５の表面に半導体素子４を配置し、その上に薄膜プロセスでコンデンサ７を作り込む方法が記載されている。
特開２０００−３４９２２８号公報 特開２０００−１２７６９号公報 特開平８−１６２６０８号公報 特開２００３−１１５５６１号公報（図９） In addition, for example, Patent Document 3 discloses a method in which a semiconductor element 4 is arranged on the surface of an organic interposer 5 and a capacitor 7 is formed thereon by a thin film process, as shown in FIG.
JP 2000-349228 A JP-A-2000-12770 JP-A-8-162608 JP 2003-115561 A (FIG. 9)

しかし、特許文献２に記載したような方法でも、半導体パッケージを用いた電子機器の小型化には依然として改善点があった。また、半導体素子上に薄膜プロセスでコンデンサを作り込む方法はコストがかさむという問題があった。   However, even with the method described in Patent Document 2, there is still an improvement in miniaturization of an electronic device using a semiconductor package. Further, the method of forming a capacitor on a semiconductor element by a thin film process has a problem that the cost is increased.

本発明は上記事情を踏まえてなされたものであり、本発明の目的は、半導体素子および受動部品を含む半導体装置を小型化する技術を提供することにある。本発明の別の目的は、このような半導体装置を効率よく製造する技術を提供することにある。本発明のまた別の目的は、このような半導体装置を安定的に製造する技術を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique for reducing the size of a semiconductor device including a semiconductor element and a passive component. Another object of the present invention is to provide a technique for efficiently manufacturing such a semiconductor device. Another object of the present invention is to provide a technique for stably manufacturing such a semiconductor device.

本発明によれば、半導体素子と、当該半導体素子と接着層を介して積層された受動部品と、を含む半導体装置が提供される。   According to the present invention, there is provided a semiconductor device including a semiconductor element and a passive component laminated on the semiconductor element via an adhesive layer.

ここで、受動部品は、たとえば、プルダウン抵抗やプルアップ抵抗等の抵抗、デカップリングコンデンサ等のコンデンサ、コイル、インダクタである。本発明の「受動部品」は、これらのうちの一つ単独であってもよく、複数の受動部品により構成された受動部品機能モジュールであってもよい。   Here, the passive components are, for example, resistors such as pull-down resistors and pull-up resistors, capacitors such as decoupling capacitors, coils, and inductors. The “passive component” of the present invention may be one of them alone, or may be a passive component functional module composed of a plurality of passive components.

半導体素子と受動部品とを積層した構成とすることにより、半導体装置を小型化することができる。   With a structure in which the semiconductor element and the passive component are stacked, the size of the semiconductor device can be reduced.

本発明の半導体装置は、インターポーザーをさらに含むことができ、半導体素子は、素子形成面の反対面である裏面がインターポーザーと接するようにインターポーザー上に載置することができ、受動部品は、半導体素子の素子形成面上に載置することができる。受動部品を半導体素子の素子形成面上に載置することにより、受動部品と半導体素子との距離を近くすることができ、これらをたとえばボンディングワイヤ等で接続する際に、ボンディングワイヤの長さを短くすることができる。これにより、素子間の抵抗を低減することができたり、信号の劣化を防いだりすることができる。この結果、半導体装置の性能を良好にすることができる。   The semiconductor device of the present invention can further include an interposer, and the semiconductor element can be mounted on the interposer such that the back surface opposite to the element forming surface is in contact with the interposer, and the passive component is Can be mounted on the element formation surface of the semiconductor element. By mounting the passive component on the element forming surface of the semiconductor element, the distance between the passive component and the semiconductor element can be reduced. For example, when connecting these with a bonding wire or the like, the length of the bonding wire is reduced. Can be shorter. As a result, the resistance between elements can be reduced, and signal degradation can be prevented. As a result, the performance of the semiconductor device can be improved.

本発明の半導体装置において、接着層は、受動部品が半導体素子と接着する接着面と略同一の大きさを有することができる。   In the semiconductor device of the present invention, the adhesive layer can have substantially the same size as the adhesive surface where the passive component adheres to the semiconductor element.

ここで、接着層は、受動部品を半導体素子と良好に接着することができれば、受動部品の接着面よりも小さくすることもでき、大きくすることもできる。このようにすることにより、受動部品と半導体素子との密着性を良好にすることができる。また、受動部品は、半導体素子の素子形成面に接着することができるが、受動部品を半導体素子上に載置する際に、接着層が半導体素子の素子や配線等に影響を与えることなく、半導体装置の性能を良好に維持することができる。   Here, the bonding layer can be smaller or larger than the bonding surface of the passive component as long as the passive component can be bonded well to the semiconductor element. By doing so, the adhesion between the passive component and the semiconductor element can be improved. In addition, the passive component can be adhered to the element forming surface of the semiconductor element, but when the passive component is mounted on the semiconductor element, the adhesive layer does not affect the element or the wiring of the semiconductor element, Good performance of the semiconductor device can be maintained.

本発明の半導体装置は、半導体素子の一面に接着された複数の受動部品を含むことができ、接着層は、受動部品のそれぞれに設けることができる。   The semiconductor device of the present invention can include a plurality of passive components bonded to one surface of the semiconductor element, and the adhesive layer can be provided on each of the passive components.

このようにすることにより、複数の受動部品と半導体素子との密着性を良好にすることができる。また、受動部品は、半導体素子の素子形成面に接着することができるが、受動部品を半導体素子上に載置する際に、接着層が半導体素子の素子や配線等に影響を与えることなく、半導体装置の性能を良好に維持することができる。   This makes it possible to improve the adhesion between the plurality of passive components and the semiconductor element. In addition, the passive component can be adhered to the element forming surface of the semiconductor element, but when the passive component is mounted on the semiconductor element, the adhesive layer does not affect the element or the wiring of the semiconductor element, Good performance of the semiconductor device can be maintained.

本発明の半導体装置において、接着層は、フィルム状接着剤を硬化させて得られた層とすることができる。フィルム状接着剤を用いることにより、半導体装置の製造工程を簡略にすることができる。これにより、半導体素子の素子や配線等への接着剤による影響を低減することができ、半導体装置の性能を良好に維持することができる。   In the semiconductor device of the present invention, the adhesive layer can be a layer obtained by curing a film adhesive. By using the film adhesive, the manufacturing process of the semiconductor device can be simplified. Thus, the influence of the adhesive on the elements of the semiconductor element, the wiring, and the like can be reduced, and the performance of the semiconductor device can be favorably maintained.

また、フィルム状接着剤を用いることにより、半導体装置のヒートサイクル耐性を高めることができ、受動部品を半導体装置と積層させた場合でも、受動部品と半導体素子との密着性を良好に保つことができる。これにより、小型化を図った半導体装置を安定的に得ることができる。   In addition, by using a film adhesive, the heat cycle resistance of the semiconductor device can be increased, and even when the passive component is laminated with the semiconductor device, good adhesion between the passive component and the semiconductor element can be maintained. it can. Thus, a miniaturized semiconductor device can be stably obtained.

なお、半導体素子は、インターポーザー上に搭載した構成とすることができる。受動部品、半導体素子、およびインターポーザー上の電極パッドとは、それぞれワイヤボンディングにより電気的に接続することができる。半導体素子の電極端子とインターポーザー上の電極パッドとは、受動部品の電極端子を介して電気的に接続することもできる。   Note that the semiconductor element can be configured to be mounted on an interposer. The passive component, the semiconductor element, and the electrode pad on the interposer can be electrically connected to each other by wire bonding. The electrode terminal of the semiconductor element and the electrode pad on the interposer can be electrically connected via the electrode terminal of the passive component.

本発明の半導体装置において、受動部品は、直方体とすることができ、積層方向の厚みが幅および長さよりも薄くなるように形成することができる。ここで、受動部品は、半導体素子上に積層した際に、積層方向の厚みが幅や長さの２分の１以下となるように構成することができる。これにより、半導体素子と受動部品とを積み重ねた積層構造とした場合であっても、受動部品への熱応力への耐性が高まり、半導体装置の性能を良好に維持することができる。   In the semiconductor device of the present invention, the passive component can be a rectangular parallelepiped, and can be formed so that the thickness in the stacking direction is smaller than the width and the length. Here, the passive component can be configured such that when stacked on a semiconductor element, the thickness in the stacking direction is equal to or less than half the width or length. Thereby, even in the case of a laminated structure in which the semiconductor element and the passive component are stacked, the resistance to the thermal stress on the passive component is increased, and the performance of the semiconductor device can be favorably maintained.

本発明の半導体装置において、受動部品は、直方体とすることができ、金属層で構成された接続領域を、接着層が設けられた面以外の面に設けることができる。従来の受動部品においては、たとえば特許文献４（図９）に示すように、受動部品の上面から側面、下面にわたって電気的な接続領域が設けられていた。本発明において、受動部品の下面に接続領域が設けられていない構成とすることができる。このような構成とすれば、受動部品を半導体素子の素子形成面に載置した場合であっても、半導体素子と接する面に接続領域が設けられていないので、受動部品と半導体素子の素子や配線との間のショートを防ぐことができる。また、より好ましくは、接続領域は受動部品の下方にも設けられていない構成とされる。これにより受動部品と半導体素子の素子や配線との間のショートを防ぐことができる。   In the semiconductor device of the present invention, the passive component may be a rectangular parallelepiped, and the connection region formed of the metal layer may be provided on a surface other than the surface on which the adhesive layer is provided. In a conventional passive component, for example, as shown in Patent Document 4 (FIG. 9), an electrical connection region is provided from the upper surface to the side surface and the lower surface of the passive component. In the present invention, a configuration in which no connection region is provided on the lower surface of the passive component can be adopted. With such a configuration, even when the passive component is mounted on the element forming surface of the semiconductor element, the connection region is not provided on the surface in contact with the semiconductor element. A short circuit with the wiring can be prevented. More preferably, the connection region is not provided below the passive component. This can prevent a short circuit between the passive component and the semiconductor element or wiring.

本発明によれば、受動部品を接着層を介して半導体素子上に積層する工程と、半導体素子と受動部品とを接着層により接着させる工程と、を含む半導体装置の製造方法が提供される。   According to the present invention, there is provided a method of manufacturing a semiconductor device including a step of laminating a passive component on a semiconductor element via an adhesive layer and a step of bonding the semiconductor element and the passive component with an adhesive layer.

ここで、受動部品は、半導体素子上で形成するのではなく、別途形成され、品質が確認されたものを半導体素子上に配置して構成される。このように、品質保証された受動部品を半導体素子上に積層し、これらを電気的に接続して半導体装置を製造することにより、半導体装置の製造歩留まりを向上することができる。   Here, the passive component is not formed on the semiconductor element, but is formed separately, and a component whose quality is confirmed is arranged on the semiconductor element. As described above, by stacking the passive components whose quality is guaranteed on the semiconductor element and electrically connecting them to manufacture the semiconductor device, the manufacturing yield of the semiconductor device can be improved.

本発明の半導体装置の製造方法において、接着層は、受動部品が半導体素子と接着する接着面と略同一の大きさを有することができる。   In the method for manufacturing a semiconductor device according to the present invention, the adhesive layer may have substantially the same size as an adhesive surface on which the passive component adheres to the semiconductor element.

本発明の半導体装置の製造方法において、受動部品を接着層を介して半導体素子上に積層する工程において、複数の受動部品を、当該複数の受動部品それぞれに設けられた複数の接着層を介して半導体素子上に積層することができる。   In the method for manufacturing a semiconductor device according to the present invention, in the step of laminating the passive components on the semiconductor element via the adhesive layer, the plurality of passive components are connected via the plurality of adhesive layers provided on the respective passive components. It can be stacked on a semiconductor element.

本発明の半導体装置の製造方法において、受動部品を接着層を介して半導体素子上に積層する工程において、接着層を受動部品に貼り付けた状態で当該受動部品を半導体素子上に積層することができる。   In the method of manufacturing a semiconductor device according to the present invention, in the step of laminating the passive component on the semiconductor element via the adhesive layer, the passive component may be laminated on the semiconductor element with the adhesive layer attached to the passive component. it can.

本発明の半導体装置の製造方法において、受動部品を半導体素子上に積層する工程において、受動部品を半導体素子の素子形成面に積層することができる。   In the method of manufacturing a semiconductor device according to the present invention, in the step of laminating the passive component on the semiconductor element, the passive component can be laminated on the element formation surface of the semiconductor element.

本発明によれば、
［１］ 半導体素子を複数個積み重ねて、一つの半導体パッケージに封入する構造を有し、少なくとも一つの半導体素子がワイヤボンディングによる金線を介して、半導体素子間及び半導体パッケージ外部と接続されている半導体装置の製造方法であって、同時に複数個の受動部品が内蔵されている事を特徴とする半導体装置の製造方法、
［２］ ［１］項記載の受動部品が、インターポーザー上だけでなく、半導体素子上にも搭載されてなることを特徴とする半導体装置の製造方法、
［３］ ［１］項記載の受動部品がワイヤボンディングの手法により電気的に接続されてなることを特徴とする半導体装置の製造方法、
［４］ ［１］項記載の受動部品の端子がワイヤボンディング可能な金属によって被覆されていることを特徴とする半導体装置の製造方法、
［５］ ［１］項記載の受動部品が複数の受動部品が組み合わされて一つの機能モジュールとなっていることを特徴とする半導体装置の製造方法、または、
［６］ ［１］〜［５］項のいずれかに記載の製造方法により製造された半導体装置、
が提供される。 According to the present invention,
[1] A structure in which a plurality of semiconductor elements are stacked and sealed in one semiconductor package, and at least one semiconductor element is connected to between semiconductor elements and to the outside of the semiconductor package via gold wires by wire bonding. A method of manufacturing a semiconductor device, wherein a plurality of passive components are built in at the same time,
[2] A method of manufacturing a semiconductor device, wherein the passive component according to [1] is mounted not only on an interposer but also on a semiconductor element.
[3] A method of manufacturing a semiconductor device, wherein the passive components according to [1] are electrically connected by a wire bonding technique.
[4] A method for manufacturing a semiconductor device, wherein the terminals of the passive component according to [1] are coated with a metal capable of wire bonding.
[5] A method for manufacturing a semiconductor device, wherein the passive component according to the item [1] is combined with a plurality of passive components to form one functional module, or
[6] A semiconductor device manufactured by the manufacturing method according to any one of [1] to [5],
Is provided.

本発明によれば、半導体素子および受動部品を含む半導体装置を小型化することができる。また、本発明によれば、このような半導体装置を効率よく製造することができる。さらに、本発明によれば、このような半導体装置を安定的に製造することができる。   According to the present invention, a semiconductor device including a semiconductor element and a passive component can be reduced in size. Further, according to the present invention, such a semiconductor device can be efficiently manufactured. Further, according to the present invention, such a semiconductor device can be manufactured stably.

図４は、本実施の形態における半導体装置の構成を示す図である。
半導体装置１００は、インターポーザー１０５上に配置された半導体素子１０４と、半導体素子１０４上に接着層１１４を介して配置された受動部品１０２と、半導体素子１０４および受動部品１０２を封止する封止材１０８とを含む。ここで、受動部品１０２は、半導体素子１０４の素子形成面である表面に載置される。インターポーザー１０５の裏面には半田ボール１０６が設けられている。受動部品１０２は、たとえば、プルダウン抵抗やプルアップ抵抗等の抵抗、カップリングコンデンサ等のコンデンサ、コイル、インダクタである。 FIG. 4 is a diagram showing a configuration of the semiconductor device according to the present embodiment.
The semiconductor device 100 includes a semiconductor element 104 disposed on an interposer 105, a passive component 102 disposed on the semiconductor element 104 via an adhesive layer 114, and a sealing for sealing the semiconductor element 104 and the passive component 102. Material 108. Here, the passive component 102 is mounted on the surface of the semiconductor element 104 that is the element forming surface. A solder ball 106 is provided on the back surface of the interposer 105. The passive component 102 is, for example, a resistor such as a pull-down resistor or a pull-up resistor, a capacitor such as a coupling capacitor, a coil, or an inductor.

半導体素子１０４の電極端子は、ボンディングワイヤ１０７を介してインターポーザー１０５上の電極パッド（不図示）と電気的に接続される。また、受動部品１０２の電極端子は、ボンディングワイヤ１０９を介してインターポーザー１０５上の電極パッド（不図示）と電気的に接続される。ボンディングワイヤ１０７およびボンディングワイヤ１０９としては、金やアルミニウム等の金属を用いることができる。このようなボンディングワイヤ１０９の形成を容易にするために、受動部品１０２の電極表面は、ボンディングワイヤ１０９を構成する材料により被覆された構成とすることもできる。また、ボンディングワイヤ１０９は、受動部品１０２の電極表面を構成する材料とは異なる材料により形成することもできる。   The electrode terminal of the semiconductor element 104 is electrically connected to an electrode pad (not shown) on the interposer 105 via a bonding wire 107. The electrode terminals of the passive component 102 are electrically connected to electrode pads (not shown) on the interposer 105 via bonding wires 109. As the bonding wires 107 and 109, a metal such as gold or aluminum can be used. In order to facilitate the formation of the bonding wire 109, the electrode surface of the passive component 102 may be configured to be covered with a material forming the bonding wire 109. Further, the bonding wire 109 can be formed of a material different from the material forming the electrode surface of the passive component 102.

図５は、本実施の形態における半導体装置の製造手順を示す工程図である。
図５（ａ）に示すように、受動部品１０２には、電極１１１が設けられている。 FIG. 5 is a process chart showing a procedure for manufacturing the semiconductor device in the present embodiment.
As shown in FIG. 5A, an electrode 111 is provided on the passive component 102.

受動部品１０２の電極１１１表面に、金等により金属層１１２を形成する（図５（ｂ））。つづいて、受動部品１０２に接着層１１４を貼り付ける。接着層１１４は、たとえば、ＣＲＭ−１５７６Ｃ（住友ベークライト株式会社製）等のフィルム状接着剤である。このような材料を用いることにより、受動部品１０２と半導体素子１０４との密着性を良好にすることができ、半導体装置１００のヒートサイクル耐性を良好にすることができる。   A metal layer 112 is formed on the surface of the electrode 111 of the passive component 102 with gold or the like (FIG. 5B). Subsequently, the adhesive layer 114 is attached to the passive component 102. The adhesive layer 114 is, for example, a film adhesive such as CRM-1576C (manufactured by Sumitomo Bakelite Co., Ltd.). By using such a material, the adhesiveness between the passive component 102 and the semiconductor element 104 can be improved, and the heat cycle resistance of the semiconductor device 100 can be improved.

本実施の形態において、接着層１１４は、受動部品１０２の面積と略等しく形成される。受動部品１０２への接着層１１４の貼り付けは、以下のようにして行うことができる。まず、受動部品１０２が個別化される前に、複数の受動部品１０２の集合体の裏面にフィルム状接着剤を貼り付け、受動部品１０２とフィルム状接着剤を合わせてダイシングマシンにより切断する。これにより、受動部品１０２を半導体素子１０４上に搭載する際に、半導体素子１０４上の素子や配線への影響を抑えることができる。また、受動部品１０２と半導体素子１０４との密着性を良好にすることができる。   In the present embodiment, the adhesive layer 114 is formed substantially equal in area to the passive component 102. The bonding of the adhesive layer 114 to the passive component 102 can be performed as follows. First, before the passive components 102 are individualized, a film adhesive is attached to the back surface of the aggregate of the plurality of passive components 102, and the passive components 102 and the film adhesive are combined and cut by a dicing machine. Accordingly, when the passive component 102 is mounted on the semiconductor element 104, the influence on the elements and the wiring on the semiconductor element 104 can be suppressed. Further, the adhesion between the passive component 102 and the semiconductor element 104 can be improved.

つづいて、受動部品１０２を半導体素子１０４の表面１０４ａに搭載する（図５（ｄ）および図５（ｅ））。半導体素子１０４は、その裏面１０４ｂがインターポーザー１０５と接するようにインターポーザー１０５上に搭載されている。受動部品１０２の搭載には、既存のＳＭＴ(Surface Mounting Technology)マウンターやダイボンダーを用いることができる。   Subsequently, the passive component 102 is mounted on the surface 104a of the semiconductor element 104 (FIGS. 5D and 5E). The semiconductor element 104 is mounted on the interposer 105 such that the back surface 104b is in contact with the interposer 105. For mounting the passive component 102, an existing SMT (Surface Mounting Technology) mounter or die bonder can be used.

ここで、接着層１１４を予め受動部品１０２に貼り付けた後に受動部品１０２を半導体素子１０４上に搭載する形態を示したが、接着層１１４の供給方法としては、フィルム状接着剤を半導体素子１０４上の所定の位置に貼り付ける方法等、他の既存の方法を用いることもできる。工程を簡略化するためには、接着層１１４を予め受動部品１０２に貼り付けた後に受動部品１０２を半導体素子１０４上に搭載する方が好ましい。また、接着層１１４は、受動部品１０２と略同一の大きさに形成されるので、接着層１１４を予め受動部品１０２に貼り付けておいた方が、正確な位置合わせをすることもできる。   Here, the form in which the adhesive layer 114 is previously attached to the passive component 102 and then the passive component 102 is mounted on the semiconductor element 104 has been described. Other existing methods, such as a method of pasting at a predetermined position above, can also be used. In order to simplify the process, it is preferable to mount the passive component 102 on the semiconductor element 104 after attaching the adhesive layer 114 to the passive component 102 in advance. In addition, since the adhesive layer 114 is formed to have substantially the same size as the passive component 102, it is possible to perform accurate positioning by adhering the adhesive layer 114 to the passive component 102 in advance.

つづいて、接着層１１４を硬化した後、受動部品１０２とインターポーザー１０５上の電極パッド（不図示）とをボンディングワイヤ１０９により結線し、半導体素子１０４とインターポーザー１０５上の電極パッドとをボンディングワイヤ１０７により結線する（図５（ｆ））。半導体素子１０４とインターポーザー１０５上の電極パッドとの結線は、受動部品１０２を半導体素子１０４上に搭載する前に行っておくこともできる。このような場合でも、受動部品１０２に予め接着層１１４を貼り付けておくことにより、工程が簡略化されるので、ボンディングワイヤ１０７が変形したり断線したりすることを防ぐことができる。   Subsequently, after the adhesive layer 114 is cured, the passive component 102 and an electrode pad (not shown) on the interposer 105 are connected by a bonding wire 109, and the semiconductor element 104 and the electrode pad on the interposer 105 are connected by a bonding wire. Connection is made by 107 (FIG. 5F). The connection between the semiconductor element 104 and the electrode pad on the interposer 105 can be made before the passive component 102 is mounted on the semiconductor element 104. Even in such a case, by bonding the adhesive layer 114 to the passive component 102 in advance, the process is simplified, so that the bonding wire 107 can be prevented from being deformed or disconnected.

また、ボンディングワイヤ１０７およびボンディングワイヤ１０９を形成する前に、プラズマ処理を行うこともできる。これにより、半導体素子１０４の電極端子、受動部品１０２の電極端子、およびインターポーザー１０５の電極パッドが清浄化される。   Before forming the bonding wires 107 and 109, plasma treatment can be performed. Thereby, the electrode terminals of the semiconductor element 104, the electrode terminals of the passive component 102, and the electrode pads of the interposer 105 are cleaned.

この後、トランスファモールド等により、封止材１０８で半導体素子１０４や受動部品１０２を封止してパッケージ化する。封止材１０８としては、たとえばＥＭＥ−Ｇ７７０（住友ベークライト株式会社製）等のエポキシ封止樹脂を用いることができる。これにより、図４に示した構成の半導体装置１００が得られる。   Thereafter, the semiconductor element 104 and the passive component 102 are sealed with a sealing material 108 by transfer molding or the like to form a package. As the sealing material 108, for example, an epoxy sealing resin such as EME-G770 (manufactured by Sumitomo Bakelite Co., Ltd.) can be used. Thereby, the semiconductor device 100 having the configuration shown in FIG. 4 is obtained.

図６は、半導体装置１００の他の構成を示す図である。
図６（ａ）に示すように、半導体装置１００において、半導体素子１０４上に複数の受動部品１０２を搭載することもできる。この場合、接着層１１４は、複数の受動部品１０２それぞれに個別に設けられる。これにより、半導体素子１０４上で、受動部品１０２が搭載される領域以外には接着層１１４が設けられないため、半導体素子１０４上の素子への接着層１１４の影響を低減することができる。 FIG. 6 is a diagram illustrating another configuration of the semiconductor device 100.
As shown in FIG. 6A, in the semiconductor device 100, a plurality of passive components 102 can be mounted on the semiconductor element 104. In this case, the adhesive layer 114 is provided individually for each of the plurality of passive components 102. Thus, since the adhesive layer 114 is not provided on the semiconductor element 104 except for the region where the passive component 102 is mounted, the influence of the adhesive layer 114 on the element on the semiconductor element 104 can be reduced.

さらに、図６（ｂ）に示すように、半導体装置１００において、半導体素子１０４上に別の半導体素子１２０をさらに搭載し、その周囲に複数の受動部品１０２を搭載した構成とすることもできる。ここで、半導体素子１２０は、受動部品１０２の一方の電極とボンディングワイヤ１０９を介して接続され、受動部品１０２の他方の電極はインターポーザー１０５上の電極パッドとボンディングワイヤ１０９を介して接続される。これにより、半導体素子１２０は、受動部品１０２を介してインターポーザー１０５上の電極パッドと接続される。また、ここでは図示していないが、受動部品と他の受動部品とをボンディングワイヤを介して接続する構成とすることもできる。   Further, as shown in FIG. 6B, in the semiconductor device 100, another semiconductor element 120 may be further mounted on the semiconductor element 104, and a plurality of passive components 102 may be mounted around the semiconductor element 120. Here, the semiconductor element 120 is connected to one electrode of the passive component 102 via a bonding wire 109, and the other electrode of the passive component 102 is connected to an electrode pad on the interposer 105 via the bonding wire 109. . Thus, the semiconductor element 120 is connected to the electrode pad on the interposer 105 via the passive component 102. Although not shown here, a configuration in which a passive component and another passive component are connected via a bonding wire may be employed.

このように、受動部品１０２は、半導体素子１０４の動作および電気的接続の妨げにならない限り、半導体素子１０４上のどの位置に配置してもよい。受動部品１０２は、インターポーザー１０５上に複数の半導体素子１０４が配置、積層されている場合、最上層の半導体素子１０４上に配置してもよく、下層の半導体素子１０４上に配置してもよい。   As described above, the passive component 102 may be arranged at any position on the semiconductor element 104 as long as it does not hinder the operation and the electrical connection of the semiconductor element 104. When a plurality of semiconductor elements 104 are arranged and stacked on the interposer 105, the passive component 102 may be arranged on the uppermost semiconductor element 104 or may be arranged on the lower semiconductor element 104. .

図７は、半導体装置１００のまた他の構成を示す図である。ここでも、図６（ｂ）に示したのと同様、半導体素子１０４上に別の半導体素子１２０が載置されている。受動部品１０２は、下層の半導体素子１０４の張り出した部分に搭載される。また、半導体素子１２０上にさらに受動部品１０２を搭載することもできる。ここでは、半導体素子１２０上に、複数の受動部品１０２により構成される受動部品機能モジュール１１０を搭載した構成を示す。また、ここで半導体素子１０４は、接続端子１１６を介してインターポーザー１０５上に配置されている。   FIG. 7 is a diagram illustrating another configuration of the semiconductor device 100. Here, as in the case shown in FIG. 6B, another semiconductor element 120 is mounted on the semiconductor element 104. The passive component 102 is mounted on a protruding portion of the lower semiconductor element 104. Further, the passive component 102 can be further mounted on the semiconductor element 120. Here, a configuration in which a passive component function module 110 including a plurality of passive components 102 is mounted on a semiconductor element 120 is shown. Here, the semiconductor element 104 is arranged on the interposer 105 via the connection terminal 116.

図８は、半導体装置１００のまた他の構成を示す図である。図示したように、受動部品１０２上に別の半導体素子１２０を搭載した構成とすることもできる。さらに、ここでは図示していないが、受動部品機能モジュール１１０上に他の受動部品機能モジュール１１０や受動部品１０２を搭載することもできる。   FIG. 8 is a diagram showing another configuration of the semiconductor device 100. As illustrated, a configuration in which another semiconductor element 120 is mounted on the passive component 102 may be employed. Further, although not shown here, another passive component function module 110 or a passive component 102 can be mounted on the passive component function module 110.

このように、受動部品１０２や受動部品機能モジュール１１０を半導体素子１０４と積層した構成とすることにより、半導体装置１００を大幅に小型化することができる。また、半導体素子１０４の素子形成面上に受動部品１０２を載置することにより、半導体素子１０４の素子や配線と受動部品１０２との距離を短くすることができ、ボンディングワイヤの長さを短くすることができる。これにより、素子間の抵抗を低減することができたり、信号の劣化を防いだりすることができる。この結果、半導体装置１００の性能を良好にすることができる。   As described above, by adopting a configuration in which the passive component 102 and the passive component functional module 110 are stacked on the semiconductor element 104, the size of the semiconductor device 100 can be significantly reduced. Further, by mounting the passive component 102 on the element formation surface of the semiconductor element 104, the distance between the passive component 102 and the element or wiring of the semiconductor element 104 can be reduced, and the length of the bonding wire can be reduced. be able to. As a result, the resistance between the elements can be reduced, and signal deterioration can be prevented. As a result, the performance of the semiconductor device 100 can be improved.

図９は、受動部品１０２の他の例を示す図である。図９（ａ）は、受動部品１０２の側面図、図９（ｂ）は、受動部品１０２の上面図、図９（ｃ）は、図９（ｂ）のＡ−Ａ’断面図である。図９（ａ）および図９（ｃ）に示すように、電極１１１は、受動部品１０２の上部のみに設けた構成とすることができる。図９（ｃ）に示すように、金属層１１２も受動部品１０２の上部のみに設けられる。このような構成とすれば、受動部品１０２を半導体素子１０４の素子形成面に載置した場合に、受動部品１０２と半導体素子１０４の機能素子とがショート等することがなく、安定的な半導体装置１００を得ることができる。   FIG. 9 is a diagram illustrating another example of the passive component 102. 9A is a side view of the passive component 102, FIG. 9B is a top view of the passive component 102, and FIG. 9C is a cross-sectional view taken along the line A-A 'of FIG. 9B. As shown in FIGS. 9A and 9C, the electrode 111 can be configured to be provided only above the passive component 102. As shown in FIG. 9C, the metal layer 112 is also provided only above the passive component 102. With such a configuration, when the passive component 102 is mounted on the element forming surface of the semiconductor element 104, the passive component 102 and the functional element of the semiconductor element 104 do not short-circuit, and a stable semiconductor device is provided. 100 can be obtained.

図１０は、受動部品１０２のまた他の例を示す図である。図１０（ａ）は、受動部品１０２の斜視図、図１０（ｂ）は、受動部品１０２の上面図、図１０（ｃ）は、図１０（ａ）のＢの方向から見た受動部品１０２の側面図である。ここで、受動部品１０２は、半導体素子１０４上に搭載されたときの積層方向の厚みｄが幅や長さよりも薄く形成される。ここで、受動部品１０２は、たとえば、長さ：幅：厚みが２：１：０．５となるように構成される。このようにすると、受動部品１０２を半導体素子１０４上に搭載し、封止材１０８を埋め込んで半導体装置１００を製造した後に、熱応力への耐性を高めることができる。   FIG. 10 is a diagram illustrating still another example of the passive component 102. 10A is a perspective view of the passive component 102, FIG. 10B is a top view of the passive component 102, and FIG. 10C is a view of the passive component 102 viewed from a direction B in FIG. FIG. Here, the passive component 102 is formed such that the thickness d in the stacking direction when mounted on the semiconductor element 104 is smaller than the width or the length. Here, the passive component 102 is configured such that, for example, length: width: thickness is 2: 1: 0.5. In this way, after the passive component 102 is mounted on the semiconductor element 104 and the encapsulant 108 is embedded to manufacture the semiconductor device 100, the resistance to thermal stress can be increased.

以下、実施例により本発明を具体的に説明するが、本発明はこれに限定されるものではない。
（実施例１）
以下、図４を参照して説明する。受動部品１０２としては、電極が金めっきにより被覆されたチップ抵抗を用いた。まず、ＦＲ−４基板をベースとして構成されたインターポーザー１０５上に、ペースト状接着剤を用いて半導体素子１０４を素子形成面が上を向くように位置決めし、搭載した。その後、ペースト状接着剤を硬化させた。 Hereinafter, the present invention will be described specifically with reference to Examples, but the present invention is not limited thereto.
(Example 1)
Hereinafter, description will be made with reference to FIG. As the passive component 102, a chip resistor whose electrodes were covered with gold plating was used. First, the semiconductor element 104 was positioned and mounted on the interposer 105 configured based on the FR-4 substrate so that the element forming surface faced upward using a paste adhesive. Thereafter, the paste adhesive was cured.

次に、半導体素子１０４上に受動部品１０２の接着面と略等しい大きさのペースト状接着剤を所定の位置にスタンピングしたのち、チップマウンターにより、受動部品１０２を位置決めし、搭載した。その後、ペースト状接着剤を加熱して硬化させた。ここで、ペースト状接着剤としては、ＣＲＭ−１５７６Ｃ（住友ベークライト株式会社製）を用いた。   Next, after a paste adhesive having a size substantially equal to the bonding surface of the passive component 102 was stamped on a predetermined position on the semiconductor element 104, the passive component 102 was positioned and mounted by a chip mounter. Thereafter, the paste adhesive was cured by heating. Here, CRM-1576C (manufactured by Sumitomo Bakelite Co., Ltd.) was used as the paste adhesive.

つづいて、プラズマ処理（条件：Ａｒガス、２００Ｗ、２分）により、半導体素子１０４の電極端子、受動部品１０２の電極端子、およびインターポーザー１０５の電極パッドを清浄化した。その後、ボンディングワイヤ１０７およびボンディングワイヤ１０９を形成した。これにより、半導体素子１０４の電極端子とインターポーザー１０５の電極パッド、および受動部品１０２の電極端子とインターポーザー１０５の電極パッドが電気的に接続された。このとき、半導体素子１０４上の電極端子の一部は、受動部品１０２を介してインターポーザー１０５の電極パッドと電気的に接続した。すなわち、受動部品１０２の一方の電極端子を半導体素子１０４の電極端子と接続し、受動部品１０２の他方の電極端子をインターポーザー１０５の電極パッドと接続した。   Subsequently, the electrode terminal of the semiconductor element 104, the electrode terminal of the passive component 102, and the electrode pad of the interposer 105 were cleaned by plasma treatment (condition: Ar gas, 200 W, 2 minutes). After that, a bonding wire 107 and a bonding wire 109 were formed. As a result, the electrode terminals of the semiconductor element 104 and the electrode pads of the interposer 105, and the electrode terminals of the passive component 102 and the electrode pads of the interposer 105 were electrically connected. At this time, some of the electrode terminals on the semiconductor element 104 were electrically connected to the electrode pads of the interposer 105 via the passive component 102. That is, one electrode terminal of the passive component 102 was connected to the electrode terminal of the semiconductor element 104, and the other electrode terminal of the passive component 102 was connected to the electrode pad of the interposer 105.

その後、このようにして得られた構造体を、エポキシ封止樹脂（ＥＭＥ−Ｇ７７０、住友ベークライト株式会社製）により封止し、インターポーザー１０５の裏面（半導体素子１０４の搭載面と反対の面）に、半田ボール１０６を形成し、ＢＧＡパッケージを得た。このようにして得られた半導体装置１００を、プリント配線板に実装し、動作確認を行った。その結果、半導体装置として正常に動作することが確認された。   Thereafter, the structure thus obtained is sealed with an epoxy sealing resin (EME-G770, manufactured by Sumitomo Bakelite Co., Ltd.), and the back surface of the interposer 105 (the surface opposite to the mounting surface of the semiconductor element 104). Then, a solder ball 106 was formed to obtain a BGA package. The semiconductor device 100 thus obtained was mounted on a printed wiring board, and the operation was confirmed. As a result, it was confirmed that the semiconductor device normally operated.

（実施例２）
本実施例では、図５に示したのと同様の手順で半導体装置１００を作製した。本実施例において、受動部品１０２に予めフィルム状接着剤を貼り付けておき、これを半導体素子１０４上に搭載した点を除いて、実施例１と同様の方法で半導体装置１００を作製した。このようにして得られた半導体装置１００を、プリント配線板に実装し、動作確認を行った結果、半導体装置として正常に動作することが確認された。 (Example 2)
In this example, the semiconductor device 100 was manufactured in the same procedure as that shown in FIG. In this example, a semiconductor device 100 was manufactured in the same manner as in Example 1 except that a film-like adhesive was previously attached to the passive component 102 and mounted on the semiconductor element 104. The semiconductor device 100 obtained as described above was mounted on a printed wiring board, and the operation was confirmed. As a result, it was confirmed that the semiconductor device 100 normally operated as a semiconductor device.

従来の半導体装置の構成を示す図である。FIG. 11 is a diagram illustrating a configuration of a conventional semiconductor device. 従来の半導体装置の構成を示す図である。FIG. 11 is a diagram illustrating a configuration of a conventional semiconductor device. 従来の半導体装置の構成を示す図である。FIG. 11 is a diagram illustrating a configuration of a conventional semiconductor device. 本発明の実施の形態における半導体装置の構成を示す図である。FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the present invention. 図４に示した半導体装置の製造手順の一例を示す工程図である。FIG. 5 is a process chart illustrating an example of a procedure for manufacturing the semiconductor device illustrated in FIG. 4. 本発明の実施の形態における半導体装置の構成の他の例を示す図である。FIG. 9 is a diagram illustrating another example of the configuration of the semiconductor device according to the embodiment of the present invention; 本発明の実施の形態における半導体装置の構成の他の例を示す図である。FIG. 9 is a diagram illustrating another example of the configuration of the semiconductor device according to the embodiment of the present invention; 本発明の実施の形態における半導体装置の構成の他の例を示す図である。FIG. 9 is a diagram illustrating another example of the configuration of the semiconductor device according to the embodiment of the present invention; 受動部品の他の例を示す図である。It is a figure showing other examples of a passive component. 受動部品の他の例を示す図である。It is a figure showing other examples of a passive component.

符号の説明Explanation of reference numerals

１００ 半導体装置
１０２ 受動部品
１０４ 半導体素子
１０５ インターポーザー
１０６ 半田ボール
１０７ ボンディングワイヤ
１０８ 封止材
１０９ ボンディングワイヤ
１１０ 受動部品機能モジュール
１１１ 電極
１１２ 金属層
１１４ 接着剤
１１６ 接続端子
１２０ 半導体素子
Reference Signs List 100 semiconductor device 102 passive component 104 semiconductor element 105 interposer 106 solder ball 107 bonding wire 108 sealing material 109 bonding wire 110 passive component function module 111 electrode 112 metal layer 114 adhesive 116 connection terminal 120 semiconductor element

Claims (13)

半導体素子と、当該半導体素子と接着層を介して積層された受動部品と、を含む半導体装置。   A semiconductor device, comprising: a semiconductor element; and a passive component laminated on the semiconductor element via an adhesive layer. 請求項１に記載の半導体装置において、
インターポーザーをさらに含み、
前記半導体素子は、素子形成面の反対面である裏面が前記インターポーザーと接するように前記インターポーザー上に載置され、
前記受動部品は、前記半導体素子の前記素子形成面上に載置された半導体装置。 The semiconductor device according to claim 1,
Further including an interposer,
The semiconductor element is placed on the interposer such that a back surface opposite to the element forming surface is in contact with the interposer,
The semiconductor device in which the passive component is mounted on the element forming surface of the semiconductor element. 請求項１または２に記載の半導体装置において、
前記接着層は、前記受動部品が前記半導体素子と接着する接着面と略同一の大きさを有する半導体装置。 The semiconductor device according to claim 1, wherein
The semiconductor device, wherein the adhesive layer has substantially the same size as an adhesive surface on which the passive component adheres to the semiconductor element. 請求項１乃至３いずれかに記載の半導体装置において、
前記半導体素子の一面に接着された複数の受動部品を含み、
前記接着層は、前記受動部品のそれぞれに設けられた半導体装置。 The semiconductor device according to claim 1, wherein
Including a plurality of passive components bonded to one surface of the semiconductor element,
The semiconductor device wherein the adhesive layer is provided on each of the passive components. 請求項１乃至４いずれかに記載の半導体装置において、
前記接着層は、フィルム状接着剤を硬化させて得られた層である半導体装置。 The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the adhesive layer is a layer obtained by curing a film adhesive. 請求項１乃至５いずれかに記載の半導体装置において、
前記受動部品は、前記半導体素子の素子形成面に接着された半導体装置。 The semiconductor device according to claim 1, wherein
The semiconductor device, wherein the passive component is bonded to an element forming surface of the semiconductor element. 請求項１乃至６いずれかに記載の半導体装置において、
前記受動部品は、直方体であって、積層方向の厚みが幅および長さよりも薄く形成された半導体装置。 The semiconductor device according to claim 1, wherein
A semiconductor device in which the passive component is a rectangular parallelepiped and has a thickness in a stacking direction smaller than a width and a length. 請求項１乃至７いずれかに記載の半導体装置において、
前記受動部品は、直方体であって、金属層で構成された接続領域が、前記接着層が設けられた面以外の面に設けられた半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the passive component is a rectangular parallelepiped, and a connection region formed of a metal layer is provided on a surface other than a surface on which the adhesive layer is provided. 受動部品を接着層を介して半導体素子上に積層する工程と、
前記半導体素子と受動部品とを前記接着層により接着させる工程と、
を含む半導体装置の製造方法。 Laminating a passive component on the semiconductor element via an adhesive layer,
Bonding the semiconductor element and the passive component with the adhesive layer,
A method for manufacturing a semiconductor device including: 請求項９に記載の半導体装置の製造方法において、
前記接着層は、前記受動部品が前記半導体素子と接着する接着面と略同一の大きさを有する半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the adhesive layer has substantially the same size as an adhesive surface on which the passive component adheres to the semiconductor element. 請求項９または１０に記載の半導体装置の製造方法において、
前記受動部品を接着層を介して半導体素子上に積層する工程において、複数の受動部品を、当該複数の受動部品それぞれに設けられた複数の接着層を介して前記半導体素子上に積層する半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 9,
A semiconductor device in which, in the step of laminating the passive components on a semiconductor element via an adhesive layer, a plurality of passive components are laminated on the semiconductor element via a plurality of adhesive layers provided on each of the plurality of passive components; Manufacturing method. 請求項９乃至１１いずれかに記載の半導体装置の製造方法において、
前記受動部品を接着層を介して半導体素子上に積層する工程において、前記接着層を前記受動部品に貼り付けた状態で当該受動部品を前記半導体素子上に積層する半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 9,
In a method of manufacturing a semiconductor device, in the step of laminating the passive component on a semiconductor element via an adhesive layer, the passive component is laminated on the semiconductor element with the adhesive layer attached to the passive component. 請求項９乃至１２いずれかに記載の半導体装置の製造方法において、
前記受動部品を前記半導体素子上に積層する工程において、前記受動部品を前記半導体素子の素子形成面に積層する半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 9,
In the step of stacking the passive component on the semiconductor element, a method of manufacturing a semiconductor device, wherein the passive component is stacked on an element forming surface of the semiconductor element.
JP2003394813A 2002-12-02 2003-11-25 Semiconductor device and manufacturing method of the same Pending JP2004200665A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156797A (en) * 2004-11-30 2006-06-15 Shinko Electric Ind Co Ltd Semiconductor device
JP2007227596A (en) * 2006-02-23 2007-09-06 Shinko Electric Ind Co Ltd Semiconductor module and its manufacturing method
DE102006034679A1 (en) * 2006-07-24 2008-01-31 Infineon Technologies Ag Semiconductor module with power semiconductor chip and passive component and method for producing the same
JP2012104633A (en) * 2010-11-10 2012-05-31 Mitsubishi Electric Corp Semiconductor device
JP2017504223A (en) * 2014-12-24 2017-02-02 インテル コーポレイション Passive components integrated in a stacked integrated circuit package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156797A (en) * 2004-11-30 2006-06-15 Shinko Electric Ind Co Ltd Semiconductor device
JP2007227596A (en) * 2006-02-23 2007-09-06 Shinko Electric Ind Co Ltd Semiconductor module and its manufacturing method
DE102006034679A1 (en) * 2006-07-24 2008-01-31 Infineon Technologies Ag Semiconductor module with power semiconductor chip and passive component and method for producing the same
US8466561B2 (en) 2006-07-24 2013-06-18 Infineon Technologies Ag Semiconductor module with a power semiconductor chip and a passive component and method for producing the same
US9159720B2 (en) 2006-07-24 2015-10-13 Infineon Technologies Ag Semiconductor module with a semiconductor chip and a passive component and method for producing the same
JP2012104633A (en) * 2010-11-10 2012-05-31 Mitsubishi Electric Corp Semiconductor device
JP2017504223A (en) * 2014-12-24 2017-02-02 インテル コーポレイション Passive components integrated in a stacked integrated circuit package

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