JP2004063824A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2004063824A
JP2004063824A JP2002220587A JP2002220587A JP2004063824A JP 2004063824 A JP2004063824 A JP 2004063824A JP 2002220587 A JP2002220587 A JP 2002220587A JP 2002220587 A JP2002220587 A JP 2002220587A JP 2004063824 A JP2004063824 A JP 2004063824A
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semiconductor chip
conductor
sealing portion
semiconductor device
substrate
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Hiroyuki Hanba
半場　博幸
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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Abstract

【課題】基板上に積層する半導体チップのチップサイズの制約をなくしたスタックドパッケージ構造の半導体装置を提供すること。
【解決手段】本発明では、積層した複数の半導体チップを基板に載設してなる半導体装置において、下層側の半導体チップの周囲に封止部を形成するとともに、同封止部に上層側の半導体チップを載設し、同上層側の半導体チップは、封止部に埋設した基板と導通する導体に接続することにした。かかる半導体装置は、下層側の半導体チップと基板に導通させた導体とを封止して封止部を形成し、同封止部の上部に上層側の半導体チップを載設し、同上層側の半導体チップと前記導体とを接続して製造することにした。
【選択図】　　　図１An object of the present invention is to provide a semiconductor device having a stacked package structure in which the chip size of a semiconductor chip stacked on a substrate is eliminated.
According to the present invention, in a semiconductor device having a plurality of stacked semiconductor chips mounted on a substrate, a sealing portion is formed around a lower semiconductor chip, and an upper semiconductor layer is formed in the sealing portion. The chip is mounted, and the semiconductor chip on the upper layer side is connected to a conductor that is electrically connected to a substrate embedded in the sealing portion. In such a semiconductor device, a sealing portion is formed by sealing a lower semiconductor chip and a conductor conducted to a substrate, and an upper semiconductor chip is mounted on the upper portion of the sealing portion. The semiconductor chip and the conductor are connected to manufacture.
[Selection diagram] Fig. 1

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法に関するものである。
【０００２】
【従来の技術】
従来の電子機器に使用される半導体装置は、基板の上面に１個の半導体チップを載設し、同半導体チップの周囲を樹脂で封止した構造となっていたが、近年の電子機器の高機能化、小型軽量化に伴って、基板の上面に複数個の半導体チップを積層し樹脂で封止したスタックドパッケージ構造の半導体装置が使用されてきている。
【０００３】
このスタックドパッケージ構造の半導体装置１００は、図６に示すように、セラミックス製のインターポーザー基板１０１の上面に半導体チップ１０２を接着し、同半導体チップ１０２の上面に別の半導体チップ１０３を接着し、上下の半導体チップ１０２，１０３の電極とインターポーザー基板１０１の電極とを金線１０４，１０５でそれぞれワイヤボンディングし、その後、上下の半導体チップ１０２，１０３と金線１０４，１０５とを樹脂１０６で封止し、その後、インターポーザー基板１０１の下面に接続端子１０７を接続していた。
【０００４】
【発明が解決しようとする課題】
このように、上記従来の半導体装置においては、下層側の半導体チップの上部に上層側の半導体チップを直接的に載設するとともに、上下の半導体チップと基板とを金線でそれぞれ接続していた。
【０００５】
そのため、上記従来の半導体装置にあっては、上層側の半導体チップを下層側の半導体チップの電極よりも内側部分で接着しなければならず、上層側の半導体チップは下層側の半導体チップよりもサイズが小さいものを使用しなければならないといった制約があり、半導体装置の設計上の自由度が低く、サイズの異なる複数の半導体チップを任意に組合わせて半導体装置を製造することができなかった。
【０００６】
しかも、上層側の半導体チップと下層側の半導体チップとを直接的に金線で接続した構造となっておらず、基板を介して上層側の半導体チップと下層側の半導体チップとを接続した構造となっており、上層側の半導体チップと下層側の半導体チップとの接続長が長くなり、それに伴って配線抵抗や寄生容量が増大して、半導体装置の特性が低減するおそれがあった。
【０００７】
また、上記従来の半導体装置においては、上下の半導体チップと全ての金線とを一括して樹脂で封止していた。
【０００８】
そのため、封止時に金線同士が接触した状態で封止されてしまい、半導体装置が不良品となるおそれがあった。特に、上記従来の半導体装置にあっては、構造上、上層側の半導体チップと基板とを接続する金線の長さが長くなるため、封止時に上層側の半導体チップと基板とを接続する金線が撓みやすく、他の金線と接触するおそれがあった。
【０００９】
【課題を解決するための手段】
そこで、請求項１に係る本発明では、基板に複数の半導体チップを積層してなる半導体装置において、下層側の半導体チップの周囲又は一部に封止部を形成するとともに、同封止部に上層側の半導体チップを載設し、同上層側の半導体チップは、封止部に埋設した基板と導通する導体に接続することにした。
【００１０】
また、請求項２に係る本発明では、前記導体で基板と下層側の半導体チップとを導通させることにした。
【００１１】
また、請求項３に係る本発明では、前記導体の上端部を平坦面状に形成することにした。
【００１２】
また、請求項４に係る本発明では、基板に複数の半導体チップを積層してなる半導体装置の製造方法において、下層側の半導体チップと基板に導通させた導体とを封止して封止部を形成し、同封止部の上部に上層側の半導体チップを載設し、同上層側の半導体チップと前記導体とを接続することにした。
【００１３】
また、請求項５に係る本発明では、前記封止部の上面を研磨することによって、導体の上端部を露出させ、その後、上層側の半導体チップと前記導体とを接続することにした。
【００１４】
また、請求項６に係る本発明では、前記封止部の上面を研磨することによって、導体の上端部を平坦面状に形成することにした。
【００１５】
【発明の実施の形態】
本発明に係る半導体装置は、積層した複数の半導体チップを基板に載設したスタックドパッケージ構造のものである。
【００１６】
しかも、下層側の半導体チップの周囲又は一部に封止部を形成するとともに、同封止部に上層側の半導体チップを載設して半導体チップを積層し、封止部に基板と導通する導体を上端部を露出させた状態で埋設し、同導体と上層側の半導体チップとを接続したものである。
【００１７】
そのため、下層側の半導体チップの上部に上層側の半導体チップを直接的に載設する必要がなくなり、チップサイズの小さい下層側の半導体チップの上方にチップサイズの大きい上層側の半導体チップを積層することができ、チップサイズの制約がなくなり、任意の組合せで複数の半導体チップを積層することができるので、半導体装置の設計上の自由度を増大させることができる。
【００１８】
また、全ての導体が一括して封止されるのではなく、下層側の導体から順に封止されることになるため、封止される導体の長さを可及的に短くすることができ、封止時に導体同士が接触して半導体装置が不良品となるのを未然に防止することができる。
【００１９】
特に、導体を下層側の半導体チップの電極に接続した場合には、上層側の半導体チップと下層側の半導体チップとを直接的に導体を介して接続することができ、上層側の半導体チップと下層側の半導体チップとの接続長を可及的に短くすることができ、それに伴って配線抵抗や寄生容量を小さくすることができて、半導体装置の特性を向上させることができる。
【００２０】
また、導体の上端部を平坦面状に形成した場合には、同導体の上端部に上層側の導体を円滑かつ強固に接続することができ、接続部分の信頼性を向上させることができる。
【００２１】
上記構成の半導体装置は、下層側の半導体チップと基板に導通させた導体とを同導体の上端部を露出させた状態で封止剤で封止し、同封止剤の上部に上層側の半導体チップを載設し、同上層側の半導体チップの電極と前記導体とを接続することによって製造することができる。
【００２２】
そして、下層側の半導体チップと導体とを封止剤で封止し、その後、封止材の上面を研磨することによって、下層側の半導体チップと導体とを導体の上端部を露出させた状態で封止剤で封止することにした。この場合には、下層側の半導体チップと導体とを導体の上端部を露出させた状態で封止剤で封止したものを容易に製造することができる。
【００２３】
また、封止剤の上面を研磨する際に、導体の上端部を研磨することによって、導体の上端部を平坦面状に形成することにした場合には、下層側の半導体チップと導体とを導体の上端部を露出させた状態で封止剤で封止したものを製造すると同時に導体の上端部を容易に平坦面状に形成することができ、これによっても、導体の上端部に上層側の導体を円滑かつ強固に接続することができ、接続部分の信頼性を向上させることができる。
【００２４】
以下に、本発明の実施の形態について図面を参照しながら具体的に説明する。
【００２５】
［第１の実施の形態］
第１の実施の形態に係る半導体装置１は、図１に示すように、セラミックス製の矩形板状のインターポーザー基板２の上面（実装面３）に下層側の半導体チップ４を載設し、同下層側の半導体チップ４の周囲にインターポーザー基板２と導通する導体５，６を埋設した矩形箱型状の下層側の封止部７を形成するとともに、同封止部７の上部に上層側の半導体チップ８を載設し、同上層側の半導体チップ８と前記導体６とを導体９で接続し、さらには、上層側の半導体チップ８の周囲に矩形箱型状の上層側の封止部１０を形成し、インターポーザー基板２の下面（半田面１１）に半田ボール（接続端子１２）を取付けている。
【００２６】
このように、上層側の半導体チップ８を下層側の封止部７の上部に載設しているため、下層側の半導体チップ４の上部に上層側の半導体チップ８を直接的に載設する必要がなくなり、チップサイズの小さい下層側の半導体チップ４の上方にチップサイズの大きい上層側の半導体チップ８を積層することができ、チップサイズの制約がなくなり、任意の組合せで複数の半導体チップ４，８を積層することができるので、半導体装置１の設計上の自由度を増大させることができる。
【００２７】
また、全ての導体５，６，９が一括して封止されるのではなく、下層側の導体５，６が封止された後に上層側の導体９が封止されることになるため、封止される導体５，６，９の長さを可及的に短くすることができ、封止時に導体５，６，９同士が接触して半導体装置１が不良品となるのを未然に防止することができる。また、導体５，６，９の長さが短くなることによって、配線抵抗や寄生容量が小さくなり、半導体装置１の特性を向上させることができる。
【００２８】
かかる半導体装置１は、以下のようにして製造する（図２参照）。
【００２９】
まず、図２（ａ）に示すように、インターポーザー基板２の実装面３に下層側の半導体チップ４をマウンターで所定位置に載設する。なお、インターポーザー基板２と半導体チップ４とは銀ペーストで接着している。
【００３０】
次に、図２（ｂ）に示すように、インターポーザー基板２の実装面３に形成したランドと半導体チップ４の電極とをワイヤーボンディング装置を用いて導体５（金線）で接続するとともに、インターポーザー基板２の実装面３に形成したランドに導体６（金線）をワイヤーボンディング装置で略山形ループ状に接続する。
【００３１】
次に、図２（ｃ）に示すように、インターポーザー基板２の実装面３において半導体チップ４と導体５，６とをモールド装置を用いて封止剤で封止することによって、下層側の半導体チップ４の周囲に下層側の封止部７を形成する。
【００３２】
次に、図２（ｄ）に示すように、下層側の封止部７の上面を研磨することによって、導体６の上端部を封止部７の外部に露出させる。その際に、導体６の上端部も同時に研磨して、導体６の上端部を平坦面状に形成する。
【００３３】
このように、導体６の上端部を平坦面状に形成した場合には、同導体６の上端部に上層側の導体９を円滑かつ強固に接続することができ、接続部分の信頼性を向上させることができる。
【００３４】
次に、図２（ｅ）に示すように、下層側の封止部７の上面に上層側の半導体チップ８をマウンターで所定位置に載設する。なお、封止部７と半導体チップ８とは接着剤で接着している。
【００３５】
次に、図２（ｆ）に示すように、上層側の半導体チップ８の電極と導体６の上端部とをワイヤーボンディング装置を用いて導体９（金線）で接続する。
【００３６】
次に、図２（ｇ）に示すように、下層側の封止部７の上面において上層側の半導体チップ８と導体９とをモールド装置を用いて封止剤で封止することによって、上層側の半導体チップ８の周囲に下層側の封止部１０を形成する。
【００３７】
最後に、図２（ｈ）に示すように、インターポーザー基板２の下面（半田面１１）に半田ボール（接続端子１２）を溶着する。
【００３８】
［第２の実施の形態］
第２の実施の形態に係る半導体装置１３は、図３に示すように、セラミックス製の矩形板状のインターポーザー基板１４の上面（実装面１５）に下層側の半導体チップ１６を載設し、同下層側の半導体チップ１６の周囲にインターポーザー基板１４と導通する導体１７，１８，１９を埋設した矩形箱型状の下層側の封止部２０を形成するとともに、同封止部２０の上部に上層側の半導体チップ２１を載設し、同上層側の半導体チップ２１と前記導体１８，１９とを導体２２で接続し、さらには、上層側の半導体チップ２１の周囲に矩形箱型状の上層側の封止部２３を形成し、インターポーザー基板１４の下面（半田面２４）に半田ボール（接続端子２５）を取付けている。
【００３９】
本実施の形態では、導体１８の一端をインターポーザー基板１４に導通させるとともに、導体１８の他端を下層側の半導体チップ１６の電極に直接的に接続させている。
【００４０】
このように、導体１８を下層側の半導体チップ１６の電極に接続した場合には、上層側の半導体チップ２１と下層側の半導体チップ１６とを直接的に導体１８を介して接続することができ、上層側の半導体チップ２１と下層側の半導体チップ１６との接続長を可及的に短くすることができ、それに伴って配線抵抗や寄生容量を小さくすることができて、半導体装置１３の特性を向上させることができる。
【００４１】
また、本実施の形態では、導体１９を円柱状に形成している。このように、導体１９は、金線に限られず、種々の伝導素材からなるものが利用できる。特に、電気抵抗の低い素材のものを用いた場合には、配線抵抗を低減することができる。
【００４２】
［第３の実施の形態］
第３の実施の形態に係る半導体装置２６は、図４に示すように、セラミックス製の矩形板状のインターポーザーインターポーザー基板２７の上面（実装面２８）に下層側の半導体チップ２９を載設し、同下層側の半導体チップ２９の上面に矩形板状の絶縁体３０を載設し、下層側の半導体チップ２９及び絶縁体３０の周囲に導体３１，３２を埋設した矩形箱型状の下層側の封止部３３を形成するとともに、同封止部３３の上部に上層側の半導体チップ３４を載設し、同上層側の半導体チップ３４と前記導体３１，３２とを導体３５で接続し、さらには、上層側の半導体チップ３４の周囲に矩形箱型状の上層側の封止部３６を形成し、インターポーザーインターポーザー基板２７の下面（半田面３７）に半田ボール（接続端子３８）を取付けている。
【００４３】
本実施の形態では、上下の半導体チップ２９，３４の間に絶縁体３０を介設している。これにより、上層側の半導体チップ３４と下層側の半導体チップ２９とをシールドすることができる。
【００４４】
［第４の実施の形態］
第４の実施の形態に係る半導体装置３９は、図５に示すように、セラミックス製の矩形板状のインターポーザー基板４０の上面（実装面４１）に下層側の半導体チップ４２を載設し、同下層側の半導体チップ４２の周囲にインターポーザー基板４０と導通する導体４３，４４を埋設した矩形箱型状の下層側の封止部４５を形成するとともに、同封止部４５の上部に上層側の半導体チップ４６を載設し、同上層側の半導体チップ４６と前記導体４４とを導体４７で接続し、さらには、上層側の半導体チップ４６の周囲に矩形箱型状の上層側の封止部４８を形成し、同上層側の封止部４８の上部にさらに上層側（最上層側）の半導体チップ４９を載設し、同最上層側の半導体チップ４９と前記導体４７とを導体５０で接続し、最上層側の半導体チップ４９の周囲に矩形箱型状の封止部５１を形成し、インターポーザー基板４０の下面（半田面５２）に半田ボール（接続端子５３）を取付けている。
【００４５】
本実施の形態では、３枚の半導体チップ４２，４６，４９を積層している。この場合には、半導体チップ４２と半導体チップ４６との間では、半導体チップ４２が下層側に位置する一方、半導体チップ４６が上層側に位置することになり、また、半導体チップ４６と半導体チップ４９との間では、半導体チップ４６が下層側に位置する一方、半導体チップ４９が上層側に位置することになる。
【００４６】
このように、本発明は、２枚の半導体チップを積層した場合に限られず、複数枚の半導体チップを積層したものにも適用することができる。
【００４７】
【発明の効果】
本発明は、以上に説明したような形態で実施され、以下に記載されるような効果を奏する。
【００４８】
すなわち、請求項１に係る本発明では、下層側の半導体チップの周囲に封止部を形成するとともに、同封止部に上層側の半導体チップを載設して半導体チップを積層し、封止部に基板と導通する導体を上端部を露出させた状態で埋設し、同導体と上層側の半導体チップとを接続しているため、チップサイズの小さい下層側の半導体チップの上方にチップサイズの大きい上層側の半導体チップを積層することができ、チップサイズの制約がなくなり、半導体装置の設計上の自由度を増大させることができる。
【００４９】
また、請求項２に係る本発明では、導体を下層側の半導体チップの電極に接続しているため、上層側の半導体チップと下層側の半導体チップとの接続長を可及的に短くすることができる。
【００５０】
また、請求項３に係る本発明では、導体の上端部を平坦面状に形成しているため、同導体の上端部に上層側の導体を円滑かつ強固に接続することができる。
【００５１】
また、請求項４に係る本発明では、下層側の半導体チップと基板に導通させた導体とを同導体の上端部を露出させた状態で封止剤で封止し、同封止剤の上部に上層側の半導体チップを載設し、同上層側の半導体チップの電極と前記導体とを接続することにしているため、これによっても、チップサイズの小さい下層側の半導体チップの上方にチップサイズの大きい上層側の半導体チップを積層することができ、半導体装置の設計上の自由度を増大させることができる。
【００５２】
また、請求項５に係る本発明では、下層側の半導体チップと導体とを封止剤で封止し、その後、封止材の上面を研磨することによって、下層側の半導体チップと導体とを導体の上端部を露出させた状態で封止剤で封止することにしているため、下層側の半導体チップと導体とを導体の上端部を露出させた状態で封止剤で封止したものを容易に製造することができる。
【００５３】
また、請求項６に係る本発明では、封止剤の上面を研磨する際に、導体の上端部を研磨することによって、導体の上端部を平坦面状に形成することにしているため、下層側の半導体チップと導体とを導体の上端部を露出させた状態で封止剤で封止したものを製造すると同時に導体の上端部を容易に平坦面状に形成することができる。
【図面の簡単な説明】
【図１】第１の実施の形態に係る半導体装置を示す側面断面図。
【図２】同製造方法を示す説明図。
【図３】第２の実施の形態に係る半導体装置を示す側面断面図。
【図４】第３の実施の形態に係る半導体装置を示す側面断面図。
【図５】第４の実施の形態に係る半導体装置を示す側面断面図。
【図６】従来の半導体装置を示す側面断面図。
【符号の説明】
１　半導体装置
２　基板
３　実装面
４　半導体チップ
５，６　導体
７　封止部
８　半導体チップ
９　導体
１０　封止部
１１　半田面
１２　接続端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
Conventional semiconductor devices used in electronic devices have a structure in which one semiconductor chip is mounted on the upper surface of a substrate and the periphery of the semiconductor chip is sealed with a resin. 2. Description of the Related Art Along with functionalization and miniaturization, a semiconductor device having a stacked package structure in which a plurality of semiconductor chips are stacked on an upper surface of a substrate and sealed with resin has been used.
[0003]
As shown in FIG. 6, in the semiconductor device 100 having the stacked package structure, a semiconductor chip 102 is bonded to an upper surface of a ceramic interposer substrate 101, and another semiconductor chip 103 is bonded to an upper surface of the semiconductor chip 102. The electrodes of the upper and lower semiconductor chips 102 and 103 and the electrodes of the interposer substrate 101 are wire-bonded with gold wires 104 and 105, respectively, and then the upper and lower semiconductor chips 102 and 103 and the gold wires 104 and 105 are bonded with a resin 106. After sealing, the connection terminals 107 were connected to the lower surface of the interposer substrate 101.
[0004]
[Problems to be solved by the invention]
As described above, in the above-described conventional semiconductor device, the upper semiconductor chip is directly mounted on the lower semiconductor chip, and the upper and lower semiconductor chips and the substrate are connected by the gold wires. .
[0005]
Therefore, in the above-described conventional semiconductor device, the upper semiconductor chip must be adhered to the inside of the electrode of the lower semiconductor chip, and the upper semiconductor chip is larger than the lower semiconductor chip. There is a restriction that a semiconductor device having a small size must be used. Therefore, the degree of freedom in designing a semiconductor device is low, and a semiconductor device cannot be manufactured by arbitrarily combining a plurality of semiconductor chips having different sizes.
[0006]
Moreover, the structure does not have a structure in which the upper semiconductor chip and the lower semiconductor chip are directly connected by gold wires, but a structure in which the upper semiconductor chip and the lower semiconductor chip are connected via a substrate. As a result, the connection length between the upper semiconductor chip and the lower semiconductor chip becomes longer, which leads to an increase in wiring resistance and parasitic capacitance, which may reduce the characteristics of the semiconductor device.
[0007]
Further, in the above-mentioned conventional semiconductor device, the upper and lower semiconductor chips and all the gold wires are collectively sealed with resin.
[0008]
Therefore, the sealing is performed in a state where the gold wires are in contact with each other at the time of sealing, and the semiconductor device may be defective. In particular, in the above-described conventional semiconductor device, the length of the gold wire connecting the upper semiconductor chip and the substrate becomes longer due to the structure, so that the upper semiconductor chip and the substrate are connected at the time of sealing. The gold wire was likely to bend and could come into contact with other gold wires.
[0009]
[Means for Solving the Problems]
Therefore, in the present invention according to claim 1, in a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate, a sealing portion is formed around or part of a lower semiconductor chip, and an upper layer is formed on the sealing portion. The semiconductor chip on the side is mounted, and the semiconductor chip on the upper layer side is connected to a conductor that is electrically connected to a substrate embedded in the sealing portion.
[0010]
Further, in the present invention according to claim 2, the conductor connects the substrate to the lower semiconductor chip.
[0011]
In the present invention according to claim 3, the upper end of the conductor is formed in a flat surface.
[0012]
According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate, the lower semiconductor chip and a conductor electrically connected to the substrate are sealed and sealed. And an upper semiconductor chip is mounted on the upper portion of the sealing portion, and the upper semiconductor chip is connected to the conductor.
[0013]
In the present invention according to claim 5, the upper end of the conductor is exposed by polishing the upper surface of the sealing portion, and thereafter, the upper semiconductor chip and the conductor are connected.
[0014]
In the present invention according to claim 6, the upper end of the conductor is formed into a flat surface by polishing the upper surface of the sealing portion.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
A semiconductor device according to the present invention has a stacked package structure in which a plurality of stacked semiconductor chips are mounted on a substrate.
[0016]
In addition, a sealing portion is formed around or part of the lower semiconductor chip, and the upper semiconductor chip is mounted on the sealing portion, the semiconductor chips are stacked, and the conductor is electrically connected to the substrate in the sealing portion. Are buried with the upper end exposed, and the same conductor is connected to the upper semiconductor chip.
[0017]
Therefore, it is not necessary to directly mount the upper semiconductor chip on the lower semiconductor chip, and the upper semiconductor chip having a larger chip size is stacked above the lower semiconductor chip having a smaller chip size. Since there is no restriction on the chip size and a plurality of semiconductor chips can be stacked in any combination, the degree of freedom in designing a semiconductor device can be increased.
[0018]
In addition, since all conductors are not sealed at once, but are sealed in order from the lower conductor, the length of the sealed conductor can be reduced as much as possible. In addition, the semiconductor device can be prevented from becoming defective due to contact between the conductors at the time of sealing.
[0019]
In particular, when the conductor is connected to the electrode of the lower semiconductor chip, the upper semiconductor chip and the lower semiconductor chip can be directly connected via the conductor, and the upper semiconductor chip can be connected to the lower semiconductor chip. The connection length with the lower semiconductor chip can be reduced as much as possible, and accordingly, the wiring resistance and the parasitic capacitance can be reduced, and the characteristics of the semiconductor device can be improved.
[0020]
Further, when the upper end of the conductor is formed in a flat surface, the upper conductor can be smoothly and firmly connected to the upper end of the conductor, and the reliability of the connection portion can be improved.
[0021]
In the semiconductor device having the above configuration, the lower semiconductor chip and the conductor conducted to the substrate are sealed with a sealant in a state where the upper end of the conductor is exposed, and the upper semiconductor layer is placed on the sealant. It can be manufactured by mounting a chip and connecting electrodes of the semiconductor chip on the upper layer side and the conductor.
[0022]
Then, the lower semiconductor chip and the conductor are sealed with a sealing agent, and then the upper surface of the sealing material is polished to expose the lower semiconductor chip and the conductor at the upper end of the conductor. And sealed with a sealant. In this case, a lower semiconductor chip and a conductor sealed with a sealing agent with the upper end of the conductor exposed can be easily manufactured.
[0023]
Further, when the upper end of the conductor is polished to polish the upper surface of the sealant to form the upper end of the conductor as a flat surface, the lower semiconductor chip and the conductor are separated from each other. The upper end of the conductor can be easily formed into a flat surface at the same time that the conductor is sealed with a sealing agent while the upper end of the conductor is exposed. Can be connected smoothly and firmly, and the reliability of the connection portion can be improved.
[0024]
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0025]
[First Embodiment]
In a semiconductor device 1 according to the first embodiment, as shown in FIG. 1, a lower semiconductor chip 4 is mounted on an upper surface (mounting surface 3) of a ceramic rectangular interposer substrate 2; A rectangular box-shaped lower sealing portion 7 in which conductors 5 and 6 that are electrically connected to the interposer substrate 2 are embedded around the lower semiconductor chip 4, and an upper layer portion is formed above the sealing portion 7. And the conductor 6 is connected to the semiconductor chip 8 on the upper layer side by a conductor 9, and further, a rectangular box-shaped upper layer side sealing is formed around the semiconductor chip 8 on the upper layer side. A portion 10 is formed, and a solder ball (connection terminal 12) is attached to the lower surface (solder surface 11) of the interposer substrate 2.
[0026]
As described above, since the upper semiconductor chip 8 is mounted on the upper portion of the lower sealing portion 7, the upper semiconductor chip 8 is directly mounted on the lower semiconductor chip 4. This eliminates the necessity, so that the upper semiconductor chip 8 having a large chip size can be stacked above the lower semiconductor chip 4 having a small chip size, and there is no restriction on the chip size. , 8 can be stacked, so that the degree of freedom in designing the semiconductor device 1 can be increased.
[0027]
Also, not all the conductors 5, 6, 9 are sealed at once, but the upper conductor 9 is sealed after the lower conductors 5, 6 are sealed. The lengths of the conductors 5, 6, and 9 to be sealed can be made as short as possible, and it is possible to prevent the semiconductor devices 1 from becoming defective due to contact between the conductors 5, 6, and 9 during sealing. Can be prevented. In addition, as the lengths of the conductors 5, 6, and 9 are reduced, the wiring resistance and the parasitic capacitance are reduced, and the characteristics of the semiconductor device 1 can be improved.
[0028]
The semiconductor device 1 is manufactured as follows (see FIG. 2).
[0029]
First, as shown in FIG. 2A, a lower semiconductor chip 4 is mounted on a mounting surface 3 of an interposer substrate 2 at a predetermined position by a mounter. Note that the interposer substrate 2 and the semiconductor chip 4 are bonded with a silver paste.
[0030]
Next, as shown in FIG. 2B, the lands formed on the mounting surface 3 of the interposer substrate 2 and the electrodes of the semiconductor chip 4 are connected by conductors 5 (gold wires) using a wire bonding apparatus. The conductor 6 (gold wire) is connected to the land formed on the mounting surface 3 of the interposer substrate 2 in a substantially mountain-shaped loop by a wire bonding device.
[0031]
Next, as shown in FIG. 2C, the semiconductor chip 4 and the conductors 5 and 6 are sealed with a sealing agent on the mounting surface 3 of the interposer substrate 2 using a molding device, thereby forming the lower layer side. A lower sealing portion 7 is formed around the semiconductor chip 4.
[0032]
Next, as shown in FIG. 2 (d), the upper end of the conductor 6 is exposed outside the sealing portion 7 by polishing the upper surface of the lower sealing portion 7. At this time, the upper end of the conductor 6 is also polished at the same time to form the upper end of the conductor 6 into a flat surface.
[0033]
As described above, when the upper end of the conductor 6 is formed in a flat surface shape, the upper-layer conductor 9 can be smoothly and firmly connected to the upper end of the conductor 6, thereby improving the reliability of the connection portion. Can be done.
[0034]
Next, as shown in FIG. 2 (e), the upper semiconductor chip 8 is mounted on the upper surface of the lower sealing portion 7 at a predetermined position by a mounter. Note that the sealing portion 7 and the semiconductor chip 8 are bonded with an adhesive.
[0035]
Next, as shown in FIG. 2F, the electrode of the upper semiconductor chip 8 and the upper end of the conductor 6 are connected by a conductor 9 (gold wire) using a wire bonding apparatus.
[0036]
Next, as shown in FIG. 2 (g), the upper semiconductor chip 8 and the conductor 9 are sealed on the upper surface of the lower sealing portion 7 with a sealing agent using a molding apparatus, thereby forming the upper layer. A lower sealing portion 10 is formed around the semiconductor chip 8 on the lower side.
[0037]
Finally, as shown in FIG. 2H, solder balls (connection terminals 12) are welded to the lower surface (solder surface 11) of the interposer substrate 2.
[0038]
[Second embodiment]
In the semiconductor device 13 according to the second embodiment, as shown in FIG. 3, a lower semiconductor chip 16 is mounted on the upper surface (mounting surface 15) of a ceramic rectangular plate-shaped interposer substrate 14, A rectangular box-shaped lower sealing portion 20 in which conductors 17, 18, and 19 that are electrically connected to the interposer substrate 14 is formed around the lower semiconductor chip 16 and is formed above the sealing portion 20. An upper semiconductor chip 21 is mounted, and the upper semiconductor chip 21 and the conductors 18 and 19 are connected by a conductor 22. Further, a rectangular box-shaped upper layer is formed around the upper semiconductor chip 21. Is formed, and solder balls (connection terminals 25) are attached to the lower surface (solder surface 24) of the interposer substrate 14.
[0039]
In the present embodiment, one end of the conductor 18 is electrically connected to the interposer substrate 14 and the other end of the conductor 18 is directly connected to the electrode of the lower semiconductor chip 16.
[0040]
Thus, when the conductor 18 is connected to the electrode of the lower semiconductor chip 16, the upper semiconductor chip 21 and the lower semiconductor chip 16 can be directly connected via the conductor 18. In addition, the connection length between the upper semiconductor chip 21 and the lower semiconductor chip 16 can be reduced as much as possible, and accordingly, the wiring resistance and the parasitic capacitance can be reduced. Can be improved.
[0041]
In the present embodiment, the conductor 19 is formed in a cylindrical shape. As described above, the conductor 19 is not limited to the gold wire, and may be made of various conductive materials. In particular, when a material having a low electric resistance is used, the wiring resistance can be reduced.
[0042]
[Third Embodiment]
In a semiconductor device 26 according to the third embodiment, as shown in FIG. 4, a lower semiconductor chip 29 is mounted on the upper surface (mounting surface 28) of a ceramic rectangular interposer interposer substrate 27. Then, a rectangular plate-shaped insulator 30 is mounted on the upper surface of the lower semiconductor chip 29, and conductors 31 and 32 are embedded around the lower semiconductor chip 29 and the insulator 30. Forming an upper sealing portion 33, mounting an upper semiconductor chip 34 on the upper sealing portion 33, connecting the upper semiconductor chip 34 and the conductors 31 and 32 with a conductor 35, Further, a rectangular box-shaped upper sealing portion 36 is formed around the upper semiconductor chip 34, and solder balls (connection terminals 38) are attached to the lower surface (solder surface 37) of the interposer interposer substrate 27. Install That.
[0043]
In the present embodiment, an insulator 30 is provided between the upper and lower semiconductor chips 29 and 34. Thereby, the upper semiconductor chip 34 and the lower semiconductor chip 29 can be shielded.
[0044]
[Fourth Embodiment]
In a semiconductor device 39 according to the fourth embodiment, as shown in FIG. 5, a lower semiconductor chip 42 is mounted on the upper surface (mounting surface 41) of a ceramic rectangular interposer substrate 40, A rectangular box-shaped lower-side sealing portion 45 in which conductors 43 and 44 that are electrically connected to the interposer substrate 40 are embedded around the lower-layer semiconductor chip 42, and an upper layer side is formed above the sealing portion 45. And the conductor 44 is connected to the semiconductor chip 46 on the upper layer side by a conductor 47. Further, a rectangular box-shaped upper layer is sealed around the semiconductor chip 46 on the upper layer side. A portion 48 is formed, and a semiconductor chip 49 on the upper layer side (uppermost layer side) is further mounted on the sealing portion 48 on the upper layer side, and the semiconductor chip 49 on the uppermost layer side and the conductor 47 are connected to the conductor 50. And connect the top side semiconductor chip. A rectangular box-shaped sealing portion 51 is formed around the flop 49, it is attached to solder ball (connection terminal 53) to the lower surface of the interposer substrate 40 (solder surface 52).
[0045]
In the present embodiment, three semiconductor chips 42, 46, and 49 are stacked. In this case, between the semiconductor chip 42 and the semiconductor chip 46, the semiconductor chip 42 is located on the lower layer side, while the semiconductor chip 46 is located on the upper layer side. In between, the semiconductor chip 46 is located on the lower layer side, while the semiconductor chip 49 is located on the upper layer side.
[0046]
As described above, the present invention is not limited to the case where two semiconductor chips are stacked, but can also be applied to a case where a plurality of semiconductor chips are stacked.
[0047]
【The invention's effect】
The present invention is implemented in the form described above, and has the following effects.
[0048]
That is, in the present invention according to claim 1, a sealing portion is formed around the lower semiconductor chip, and the upper semiconductor chip is mounted on the sealing portion, and the semiconductor chips are stacked. Since the conductor conducting to the substrate is buried with the upper end exposed, and the conductor is connected to the upper semiconductor chip, the chip size is larger above the lower semiconductor chip having a smaller chip size. The semiconductor chips on the upper layer side can be stacked, the restriction on the chip size is eliminated, and the degree of freedom in designing the semiconductor device can be increased.
[0049]
Further, in the present invention according to claim 2, since the conductor is connected to the electrode of the lower semiconductor chip, the connection length between the upper semiconductor chip and the lower semiconductor chip is reduced as much as possible. Can be.
[0050]
According to the third aspect of the present invention, since the upper end of the conductor is formed in a flat surface, the upper conductor can be smoothly and firmly connected to the upper end of the conductor.
[0051]
Further, in the present invention according to claim 4, the lower semiconductor chip and the conductor conducted to the substrate are sealed with a sealant in a state where the upper end of the conductor is exposed, and the upper part of the sealant is sealed. Since the upper semiconductor chip is mounted and the electrode of the upper semiconductor chip is connected to the conductor, the chip size is also placed above the lower semiconductor chip having a smaller chip size. A large upper semiconductor chip can be stacked, and the degree of freedom in designing a semiconductor device can be increased.
[0052]
Further, in the present invention according to claim 5, the lower semiconductor chip and the conductor are sealed by sealing the lower semiconductor chip and the conductor with a sealant, and thereafter, the upper surface of the sealing material is polished. The lower semiconductor chip and the conductor are sealed with a sealant with the upper end of the conductor exposed because the upper end of the conductor is sealed with a sealant with the upper end exposed. Can be easily manufactured.
[0053]
Further, in the present invention according to claim 6, when polishing the upper surface of the sealant, the upper end portion of the conductor is polished to form the upper end portion of the conductor in a flat surface shape. The upper end of the conductor can be easily formed into a flat surface at the same time as manufacturing a semiconductor chip and the conductor which are sealed with a sealant with the upper end of the conductor exposed.
[Brief description of the drawings]
FIG. 1 is a side sectional view showing a semiconductor device according to a first embodiment.
FIG. 2 is an explanatory view showing the manufacturing method.
FIG. 3 is a side sectional view showing a semiconductor device according to a second embodiment.
FIG. 4 is a side sectional view showing a semiconductor device according to a third embodiment.
FIG. 5 is a side sectional view showing a semiconductor device according to a fourth embodiment.
FIG. 6 is a side sectional view showing a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Substrate 3 Mounting surface 4 Semiconductor chip 5, 6 Conductor 7 Sealing part 8 Semiconductor chip 9 Conductor 10 Sealing part 11 Solder surface 12 Connection terminal

Claims (6)

基板に複数の半導体チップを積層してなる半導体装置において、
下層側の半導体チップの周囲又は一部に封止部を形成するとともに、同封止部に上層側の半導体チップを載設し、同上層側の半導体チップは、封止部に埋設した基板と導通する導体に接続してなることを特徴とする半導体装置。In a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate,
A sealing portion is formed around or part of the lower semiconductor chip, and the upper semiconductor chip is mounted on the sealing portion, and the upper semiconductor chip is electrically connected to the substrate embedded in the sealing portion. A semiconductor device characterized in that it is connected to a conductor. 前記導体は、基板と下層側の半導体チップとを導通することを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the conductor conducts between the substrate and a lower semiconductor chip. 前記導体は、上端部を平坦面状に形成したことを特徴とする請求項１又は請求項２記載の半導体装置。3. The semiconductor device according to claim 1, wherein said conductor has an upper end formed in a flat surface. 基板に複数の半導体チップを積層してなる半導体装置の製造方法において、
下層側の半導体チップと基板に導通させた導体とを封止して封止部を形成し、同封止部の上部に上層側の半導体チップを載設し、同上層側の半導体チップと前記導体とを接続することを特徴とする半導体装置の製造方法。In a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate,
A sealing portion is formed by sealing the lower semiconductor chip and the conductor conducted to the substrate, and the upper semiconductor chip is mounted on the sealing portion, and the upper semiconductor chip and the conductor are mounted. And a method of manufacturing a semiconductor device. 前記封止部の上面を研磨することによって、導体の上端部を露出させ、その後、上層側の半導体チップと前記導体とを接続することを特徴とする請求項４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein an upper end portion of the conductor is exposed by polishing an upper surface of the sealing portion, and thereafter, the upper semiconductor chip is connected to the conductor. 前記封止部の上面を研磨することによって、導体の上端部を平坦面状に形成することを特徴とする請求項５記載の半導体装置の製造方法。6. The method according to claim 5, wherein an upper end portion of the conductor is formed into a flat surface by polishing an upper surface of the sealing portion.
JP2002220587A 2002-07-30 2002-07-30 Semiconductor device and manufacturing method thereof Pending JP2004063824A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006074736A (en) * 2004-08-02 2006-03-16 Seiko Epson Corp Piezoelectric oscillator and manufacturing method thereof
JP2007250764A (en) * 2006-03-15 2007-09-27 Elpida Memory Inc Semiconductor device and manufacturing method thereof
JP2008515189A (en) * 2004-09-28 2008-05-08 フリースケール セミコンダクター インコーポレイテッド Method for forming semiconductor package and package structure
JP2009111392A (en) * 2007-10-30 2009-05-21 Samsung Electronics Co Ltd Stack package and manufacturing method thereof
CN111739849A (en) * 2020-08-06 2020-10-02 甬矽电子(宁波)股份有限公司 Chip package structure, manufacturing method and electronic device
JP2023118033A (en) * 2022-02-14 2023-08-24 ウェスタン デジタル テクノロジーズ インコーポレーテッド Semiconductor device package with exposed bond wires

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006074736A (en) * 2004-08-02 2006-03-16 Seiko Epson Corp Piezoelectric oscillator and manufacturing method thereof
JP2008515189A (en) * 2004-09-28 2008-05-08 フリースケール セミコンダクター インコーポレイテッド Method for forming semiconductor package and package structure
JP2007250764A (en) * 2006-03-15 2007-09-27 Elpida Memory Inc Semiconductor device and manufacturing method thereof
JP2009111392A (en) * 2007-10-30 2009-05-21 Samsung Electronics Co Ltd Stack package and manufacturing method thereof
CN111739849A (en) * 2020-08-06 2020-10-02 甬矽电子(宁波)股份有限公司 Chip package structure, manufacturing method and electronic device
JP2023118033A (en) * 2022-02-14 2023-08-24 ウェスタン デジタル テクノロジーズ インコーポレーテッド Semiconductor device package with exposed bond wires
JP7441887B2 (en) 2022-02-14 2024-03-01 ウェスタン デジタル テクノロジーズ インコーポレーテッド Semiconductor device package with exposed bond wires

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