CN112151390A - 一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法 - Google Patents

一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法 Download PDF

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CN112151390A
CN112151390A CN201910699977.XA CN201910699977A CN112151390A CN 112151390 A CN112151390 A CN 112151390A CN 201910699977 A CN201910699977 A CN 201910699977A CN 112151390 A CN112151390 A CN 112151390A
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chip
electrodes
type
packaging
electrode
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连清宏
邱承贤
黄兴材
黄兴祥
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SFI Electronics Technology Inc
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SFI Electronics Technology Inc
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Abstract

本发明为一种贴片式(SMD型)单颗小尺寸及阵列型(Array Type)的芯片半导体元件新封装方法，利用线路板双面连通设计方式将双面线路板的内外层预留两或多个连接端点，并利用钻孔和电镀的制程方式将内外层的线路作一连结，内层两或多个连接端点作为内电极与半导体晶粒连结用，外层两或多个连接端点作为外电极供SMT焊接时使用。

Description

一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装 方法
技术领域
本案涉及一种芯片半导体封装的新制作方法，尤其涉及一种贴片式单颗 小尺寸及阵列型的芯片半导体封装的新制作方法。
背景技术
半导体封装的公知技术为导线架以环氧树脂100封装后，于芯片两端留 下外引脚101，方便后续焊接制程，因为制程及应用面的不同，外引脚的形式 各有不同，如图1所示。
发明内容
本发明提供一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方 法，包含：提供含正电极及负电极的晶粒，且提供含薄膜或厚膜双面线路的 线路板，双面的该线路板上预留两或多个连接端点，再利用钻孔和电镀的制 程方法将上下两面电路垂直方式连接；以烘烤方式将导电胶连接该晶粒的正 电极及负电极与薄膜或厚膜双面线路，以淋膜、涂布、刮刀..等方法，于表面 布上整面的绝缘封装材料，并进行绝缘封装材料熟化处理；于该晶粒的外的 位置进行切割，即可形成无外引脚的封装结构，即完成单颗小尺寸芯片型半 导体的制作；以及依据晶粒设计方式，制作成正向、反向或双向的芯片型半 导体元件。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该晶粒具有一上电极一下电极、一上电极二下电极、二上电极一下电极、 二下电极、一上电极多下电极或多上电极一下电极…等。
本发明提供一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方 法，包含提供含正电极及负电极的晶粒，且提供含薄膜或厚膜双面线路的线 路板，双面的该线路板上预留两或多个连接端点，再利用钻孔和电镀的制程 方法将上下两面电路垂直方式连接；利用烘烤方式将导电胶连接该晶粒的正 电极及负电极与该薄膜或厚膜双面线路的线路板；以及于上盖板表面涂布一 层黏着剂，以连接该上盖板与该晶粒，且以灌注方法，于内部填满绝缘封装 材料，并进行绝缘封装材料熟化处理。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该上盖板为陶瓷板(例如：氧化铝板、氮化铝板..等)、塑料板(例如：PE、PP、 PC、聚亚酰胺、工程塑料..等)、复合材料板(例如：碳纤板、玻纤板..等)..等， 亦可黏贴散热板，以增加散热性能。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中含薄膜或厚膜双面线路的该线路板更包含双面连通设计的阵列式外电极。
本发明提供一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方 法，包含：提供含三电极的晶粒，且提供含薄膜或厚膜双面线路的至少二线 路板；利用烘烤方式使用导电胶连接该晶粒的三电极与该薄膜或厚膜线路； 以及以灌注方式，填充绝缘封装材料，并进行绝缘封装材料熟化处理。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中封装的该贴片式单颗小尺寸及阵列型的芯片半导体元件具有电流方向一进 二出或正向加接地引出、反向加接地引出及双向+接地引出的型式。
本发明提供一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方 法，包含：提供含正电极及负电极的晶粒，且提供含薄膜或厚膜双面线路的 至少二线路板；利用烘烤方式将导电胶连接该晶粒的正电极及负电极与该薄 膜或厚膜线路；以灌注方法，内部填满绝缘封装材料，并进行绝缘封装材料 熟化处理；切割后以涂布、沾银、薄膜制程等方式制作单边端电极，使单边 端电极与预留电极接点进行连通，即完成单颗小尺寸芯片半导体的制作；以 及进行电镀制程以制成单颗SMD型半导体芯片元件。
本发明提供一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方 法，包含：提供含三电极的晶粒，且提供含薄膜或厚膜双面线路的至少二线 路板；利用烘烤方式使用导电胶连接该晶粒的三电极与该薄膜或厚膜线路； 以及以灌注方法，于内部填满绝缘封装材料，并进行绝缘封装材料熟化处理； 切割后以涂布、沾银、薄膜制程等方式制作两端电极，使两端电极与预留电 极接点进行连通，即完成单颗小尺寸三电极芯片半导体的制作；以及进行电 镀制程以制成单颗SMD型半导体芯片元件。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中含薄膜或厚膜双面线路的该线路板更包含双面连通设计的阵列式外电极， 且该线路板单面更具有连通制成的两端水平引出电极，切割后以涂布、沾银、 薄膜制程等方式制作两端电极，使两端电极与预留电极接点进行连通。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该芯片的规格包含：
芯片类型 端电极数量 长 宽 厚 备注
单颗01005 2个 0.4mm 0.2mm 0.2mm 厚度可微调
单颗0201 ≦3个 0.6mm 0.3mm 0.3mm 厚度可微调
单颗0402 ≦3个 1.0mm 0.5mm 0.5mm 厚度可微调
Array Type 0204 ≥4个 1.0mm 0.5mm 0.3mm 厚度可微调
Array Type 0306 ≥4个 1.6mm 0.8mm 0.4mm 厚度可微调
Array Type 0405 ≥4个 1.3mm 1.0mm 0.4mm 厚度可微调
Array Type 0508 ≥4个 2.0mm 1.3mm 0.5mm 厚度可微调
Array Type 0510 ≥4个 2.5mm 1.3mm 0.5mm 厚度可微调
Array Type 0612 ≥4个 3.0mm 1.5mm 0.6mm 厚度可微调
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该芯片种类包含TVS二极管、萧特基二极管、开关二极管、齐纳二极管、 整流二极管及晶体管...等，但不限于此六种半导体晶粒，举凡半导体晶粒植晶 制程皆适用。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该线路板是将薄膜或厚膜线路制作于陶瓷板(例如：氧化铝板、氮化铝板.. 等)、塑料板(例如：PE、PP、PC、聚亚酰胺、工程塑料..等)及复合材料板(例 如：碳纤板、玻纤板..等)..等，亦可印刷于散热板上，以增加散热性能。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该导电胶是各式导电胶(例如：银胶、银钯胶、钯胶、白金胶、铜胶、镍胶、 铝胶、锡胶及锡铅胶..等)连接半导体晶粒与印刷线路。可使用无铅导电胶(例 如：银胶、银钯胶、钯胶、白金胶、铜胶、镍胶、铝胶及锡胶..等)，以取代公 知的有铅锡膏，以制作出无铅化半导体封装产品。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该绝缘封装材料是以淋膜、涂布、刮刀、灌注…等方法覆盖该晶粒、导电 胶及内部线路板，达到保护晶粒电性及物性特性的功能。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该晶粒依据半导体晶粒设计方式，可制作成正向、反向或双向的芯片型半 导体元件，设计方式可为一进一出或一进二出。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该端电极是以电镀制程或采用免电镀即有焊性的端电极材料(例如：Ag、Au、 Pd、Pt、Ag/Pd合金、Ag/Pt合金…等)，使该端电极具有焊锡性，以制成贴片 式单颗小尺寸及阵列型的芯片半导体元件。
本发明的贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其 中该薄膜线路板材料是利用薄膜制程制作(例如：溅镀、蒸镀、化镀、黄光、 显影、蚀刻..等)。厚膜线路可用印刷方式制作。
附图说明
图1为现有技术单独使用线路板双面连通设计制作单颗小尺寸芯片型半 导体的封装与制作方法的示意图。
图2A、2B、2C为本发明一种贴片式单颗小尺寸及阵列型的芯片半导体 元件的封装方法的实施例一的示意图。
图3A至3C为本发明一种贴片式单颗小尺寸及阵列型的芯片半导体元件 的封装方法的实施例二的示意图。
图4A至4C为本发明一种贴片式单颗小尺寸及阵列型的芯片半导体元件 的封装方法的实施例三的示意图。
图5A至5D为本发明一种贴片式单颗小尺寸及阵列型的芯片半导体元件 的封装方法的实施例四的示意图。
图6A至6D为本发明一种贴片式单颗小尺寸及阵列型的芯片半导体元件 的封装方法的实施例五的示意图。
图7A为本发明一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封 装方法的实施例六的示意图。
图8A为本发明一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封 装方法的实施例七的示意图。
符号说明：
100 环氧树脂
101 外引脚
200 线路板
201 薄膜或厚膜双面线路
210 半导体晶粒
211 正电极
212 负电极
221 导电胶
222 导电胶
230 绝缘封装材料
290 位置
300 线路板
301 薄膜或厚膜线路
310 半导体晶粒
311 正电极
312 负电极
321 导电胶
322 导电胶
330 绝缘封装材料
340 黏着剂
350 上盖板
390 位置
400 线路板
401 薄膜或厚膜双面线路
402 薄膜或厚膜双面线路
410 半导体晶粒
411 电极
412 电极
413 接地引出
421 导电胶
422 导电胶
430 绝缘封装材料
440 导电胶
450 线路板
490 位置
500 线路板
501 薄膜或厚膜单面线路
502 薄膜或厚膜单面线路
521 导电胶
522 导电胶
530 绝缘封装材料
550 线路板
590 位置
600 线路板
601 薄膜或厚膜单面线路
602 薄膜或厚膜单面线路
610 晶粒
611 电极
612 电极
613 电极
621 导电胶
622 导电胶
623 导电胶
630 绝缘封装材料
650 线路板
690 位置
791 阵列式外电极
792 阵列式外电极
793 阵列式外电极
891 阵列式外电极
892 阵列式外电极
893 阵列式外电极
894 电极
895 电极
896 电极
897 两端电极
898 两端电极
899 两端电极
具体实施方式
为充分了解本发明的目的、特征及功效，通过下述具体的实施例，并配 合所附的图式，对本发明做一详细说明，说明如后：
本发明是单独使用线路板双面连通设计或同时使用线路板单面连通设计 及线路板双面连通设计进行半导体晶粒与电极的连接，可将线路以薄膜或厚 膜印刷..等技术，制作于陶瓷板(例如：氧化铝板、氮化铝板..等)、塑料板(例 如：PE、PP、PC、聚亚酰胺、工程塑料..等)、复合材料板(例如：碳纤板、玻 纤板..等)..等，线路板单面连通设计则是在单面线路板上预留两或多个连接端 点并将电路以水平的方式引出至侧边；线路板双面连通设计为在双面线路板 上预留两或多个连接端点，再利用钻孔和电镀的制程方法将上下两面电路垂 直方式连接，内层线路作为内电极与半导体晶粒连结使用，外层线路作为外 电极与SMT板子连结使用。
将两或多个连接端点上点上无铅导电膏(例如：银胶、银钯胶、钯胶、白 金胶、铜胶、镍胶、铝胶、锡胶..等)，并于导电胶上置放半导体晶粒，点胶与 植晶步骤均以CCD方式定位，可将半导体晶粒准确的置放于预留的电极上， 连接半导体晶粒与薄膜或厚膜线路，半导体晶粒两或多个电极可与预留内电 极接点进行连通，可满足单颗小尺寸半导体晶粒的封装(例如：01005、0201、 0402..等小尺寸的半导体晶粒的封装)或阵列型半导体晶粒的封装(例如：0204、 0306、0405、0508、0510、0612..等阵列型的芯片半导体晶粒的封装)。
以淋膜、涂布、刮刀、灌注..等方法，于表面布上整面的绝缘封装材料， 其中淋膜与涂布绝缘封装材料的方式，可于淋膜数次后累积一定的绝缘封装 材料厚度，而刮刀与灌注绝缘封装材料的方式，可于刮刀与灌注1～2次后， 即可累积一定的绝缘封装材料厚度。进行绝缘封装材料熟化处理后，即可进 行切割，若单独使用线路板双面连通设计，切割后即完成的封装产品即制成 贴片式单颗小尺寸或阵列型半导体元件。若同时使用线路板单面连通设计及 线路板双面连通设计，切割后需再经过涂布、沾银、薄膜制程等方式将线路板单面连通设计的侧边引出的内电极连通至外电极，电镀后即制成贴片式单 颗小尺寸或阵列型半导体元件。
实施例一：单独使用线路板双面连通设计制作单颗小尺寸芯片型半导体 的封装与制作方法：(1)如图2A所示，线路板200上含薄膜或厚膜双面线路 201，在双面线路板上预留两或多个连接端点，再利用钻孔和电镀的制程方法 将上下两面电路垂直方式连接，半导体晶粒210含正负两电极211及212，利 用烘烤方式将导电胶221与222连接半导体晶粒的正负电极(211与212)及薄 膜或厚膜线路(201)，以淋膜、涂布、刮刀..等方法，于表面布上整面的绝缘封 装材料230，并进行绝缘封装材料熟化处理。(2)其中薄膜线路板材料可利用薄膜制程制作(例如：溅镀、蒸镀、化镀、黄光、显影、蚀刻..等)。厚膜线路 可用印刷方式制作。(3)于位置290进行切割，即可形成无外引脚的封装结构， 即完成单颗小尺寸(例如：01005、0201、0402..等)芯片型半导体的制作，制成 单颗SMD型半导体元件，如图2B所示。(4)依据晶粒设计方式，可制作成正 向、反向或双向的芯片型半导体元件，如图2C所示。
实施例二：单独使用线路板双面连通设计制作含盖板单颗小尺寸芯片型 半导体的封装与制作方法：(1)如图3A所示，线路板300上含薄膜或厚膜双面 线路301，在双面线路板上预留两或多个连接端点，再利用钻孔和电镀的制程 方法将上下两面电路垂直方式连接，半导体晶粒310含正负两电极311及312， 利用烘烤方式将导电胶321与322连接半导体晶粒的正负电极(311与312)及 薄膜或厚膜线路(301)。(2)于上盖板350表面涂布一层黏着剂340，以连接上 盖板350与晶粒310，上盖板为陶瓷板(例如：氧化铝板、氮化铝板..等)、塑料板(例如：PE、PP、PC、聚亚酰胺、工程塑料..等)、复合材料板(例如：碳 纤板、玻纤板..等)..等，亦可黏贴散热板，以增加散热性能。(3)以灌注方法， 于内部填满绝缘封装材料330，并进行绝缘封装材料熟化处理。(4)于位置390 进行切割，即可形成无外引脚的封装结构。如图3B所示。(5)依据晶粒设计方 式，可制作成正向、反向或双向的芯片型半导体元件，如图3C所示。
实施例三：单独使用线路板双面连通设计制作单颗小尺寸芯片三电极型 半导体的封装与制作方法：(1)如图4A所示，线路板400上含薄膜或厚膜双面 线路401，在双面线路板上预留两或多个连接端点，再利用钻孔和电镀的制程 方法将上下两面电路垂直方式连接，线路板450上含薄膜或厚膜双面线路402， 在双面线路板上预留一或多个连接端点，再利用钻孔和电镀的制程方法将上 下两面电路垂直方式连接，半导体晶粒410含正负两电极411、412及接地引 出413，利用烘烤方式将导电胶421、422及440连接半导体晶粒的三电极(411、 412及413)及薄膜或厚膜线路(401、402)。(2)以灌注方法，于内部布上绝缘封 装材料430，并进行绝缘封装材料熟化处理。(3)于位置490进行切割，即可 形成无外引脚的封装结构。如图4B所示。(4)依据晶粒设计方式，可制作成正 向+接地引出、反向+接地引出及双向+接地引出或电流一进二出的芯片型半导 体元件，如图4C所示。
实施例四：同时使用线路板单面连通设计及线路板双面连通设计制作单 颗小尺寸芯片型半导体的封装与制作方法：(1)如图5A所示，线路板500上含 薄膜或厚膜双面线路501，在双面线路板上预留两或多个连接端点，再利用钻 孔和电镀的制程方法将上下两面电路垂直方式连接，线路板550上含薄膜或 厚膜单面线路502，半导体晶粒510含正负两电极511及512，利用烘烤方式 将导电胶521及522连接半导体晶粒的负电极(511及512)及薄膜或厚膜线路 (501及502)。(2)以灌注方法，于内部布上整面的绝缘封装材料530，并进行绝缘封装材料熟化处理。(3)于位置590进行切割，即可形成一个无外引脚及 一个外引脚的封装结构。如图5B所示。(4)依据晶粒设计方式，可制作成正向、 反向或双向的芯片型半导体元件，如图5C所示。(5)以涂布、沾银、薄膜制程 等方式将线路板单面连通设计的侧边引出的内电极连通至外电极，电镀后即 制成单颗小尺寸(例如：01005、0201、0402..等)芯片型半导体SMD型半导体 芯片。如图5D所示。
实施例五：同时使用线路板单面连通设计及线路板双面连通设计制作单 颗小尺寸三电极型半导体的封装与制作方法：(1)如图6A所示，线路板600 上含薄膜或厚膜双面线路601，在双面线路板上预留两或多个连接端点，再利 用钻孔和电镀的制程方法将上下两面电路垂直方式连接，线路板650上含薄 膜或厚膜单面线路602，半导体晶粒610含三电极611、612及613，利用烘 烤方式使用导电胶621、622与623连接半导体晶粒的三电极(611、612与613) 及薄膜或厚膜线路(601及602)。(2)以灌注方式，填充绝缘封装材料630，并 进行绝缘封装材料熟化处理。(3)于位置690进行切割，即可形成一个无外引 脚及二个外引脚的封装结构。如图6B所示。(4)依据晶粒设计方式，可制作成 三电极型芯片型半导体元件，如图6C所示。此设计方式具有正向+接地引出、 反向+接地引出及双向+接地引出或电流方向一进两出的芯片型半导体元件。 (5)以涂布、沾银、薄膜制程等方式制作两端电极，使两端电极与预留电极接 点进行连通，即完成单颗小尺寸(例如：01005、0201、0402..等)芯片型半导体 的封装。并于电镀制程后，制成单颗SMD型半导体元件。如图6D所示。
实施例六：单独使用线路板双面连通设计制作阵列型芯片型半导体的封 装与制作方法：(1)在双面线路板上内外层阵列多个连接端点，利用钻孔和电 镀的制程方法将上下两面电路垂直方式连接，可制成2X 2(791)、2X 3(792)、 2X 4(793)…等等阵列式外电极。(2)以实施例一或二的方式进行封装，即完 成阵列型(例如：0204、0306、0405、0508..等)芯片半导体的制作，如图7A所 示。
实施例七：同时使用线路板单面连通设计及线路板双面连通设计制作阵 列型芯片半导体的封装与制作方法：(1)线路板双面连通设计为在双面线路板 内外层阵列多个连接端点，利用钻孔和电镀的制程方法将上下两面电路垂直 方式连接，可制成2X 2(891)、2X3(892)、2X 4(893)…等等阵列式外电极。 线路板单面连通设计为在单面线路板将内层电路以水平的方式引出至侧边如 894、895、896。(2)以实施例五的方式进行封装，切割后以涂布、沾银、薄 膜制程等方式制作两端电极，使两端电极与预留电极接点进行连通如897、898、 899，并于电镀制程后即完成阵列型(例如：0204、0306、0405、0508..等)的芯 片半导体的制作，如图8A所示。
综上所述，本发明可提供数种用于贴片式单颗小尺寸及阵列型的芯片半 导体元件的封装方法。
本发明在上文中已以较佳实施例揭露，然熟习本项技术者应理解的是， 该实施例仅用于描绘本发明，而不应解读为限制本发明的范围。应注意的是， 举凡与该实施例等效的变化与置换，均应设为涵盖于本发明的范畴内。因此， 本发明的保护范围当以申请专利范围所界定者为准。

Claims (18)

1.一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，包含：
提供含正电极及负电极的晶粒，且提供含薄膜或厚膜双面线路的线路板，双面的该线路板上预留两或多个连接端点，再利用钻孔和电镀的制程方法将上下两面电路垂直方式连接；
以烘烤方式将导电胶连接该晶粒的正电极及负电极与薄膜或厚膜双面线路，以淋膜、涂布、刮刀的其中一种方法，于表面布上整面的绝缘封装材料，并进行绝缘封装材料熟化处理；
于该晶粒的外的位置进行切割，即可形成无外引脚的封装结构，即完成单颗小尺寸芯片型半导体的制作；以及
依据晶粒设计方式，制作成正向、反向或双向的芯片型半导体元件。
2.如权利要求1所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该晶粒具有一上电极一下电极、一上电极二下电极、二上电极一下电极、二下电极、一上电极多下电极或多上电极一下电极的至少一种。
3.一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，包含：
提供含正电极及负电极的晶粒，且提供含薄膜或厚膜双面线路的线路板，双面的该线路板上预留两或多个连接端点，再利用钻孔和电镀的制程方法将上下两面电路垂直方式连接；
利用烘烤方式将导电胶连接该晶粒的正电极及负电极与该薄膜或厚膜双面线路的线路板；以及
于上盖板表面涂布一层黏着剂，以连接该上盖板与该晶粒，且以灌注方法，于内部填满绝缘封装材料，并进行绝缘封装材料熟化处理。
4.如权利要求3所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该上盖板为陶瓷板、塑料板、复合材料板，亦可黏贴散热板，以增加散热性能。
5.如权利要求1或3所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中含薄膜或厚膜双面线路的该线路板更包含双面连通设计的阵列式外电极。
6.一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，包含：
提供含三电极的晶粒，且提供含薄膜或厚膜双面线路的至少二线路板；
利用烘烤方式使用导电胶连接该晶粒的三电极与该薄膜或厚膜线路；以及
以灌注方式，填充绝缘封装材料，并进行绝缘封装材料熟化处理。
7.如权利要求6所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中封装的该贴片式单颗小尺寸及阵列型的芯片半导体元件具有电流方向一进二出或正向加接地引出、反向加接地引出及双向+接地引出的型式。
8.一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，包含：
提供含正电极及负电极的晶粒，且提供含薄膜或厚膜双面线路的至少二线路板；
利用烘烤方式将导电胶连接该晶粒的正电极及负电极与该薄膜或厚膜线路；
以灌注方法，内部填满绝缘封装材料，并进行绝缘封装材料熟化处理；
切割后以涂布、沾银、薄膜制程方式制作单边端电极，使单边端电极与预留电极接点进行连通，即完成单颗小尺寸芯片半导体的制作；以及
进行电镀制程以制成单颗SMD型半导体芯片元件。
9.一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，包含：
提供含三电极的晶粒，且提供含薄膜或厚膜双面线路的至少二线路板；
利用烘烤方式使用导电胶连接该晶粒的三电极与该薄膜或厚膜线路；以及
以灌注方法，于内部填满绝缘封装材料，并进行绝缘封装材料熟化处理；
切割后以涂布、沾银、薄膜制程方式制作两端电极，使两端电极与预留电极接点进行连通，即完成单颗小尺寸三电极芯片半导体的制作；以及
进行电镀制程以制成单颗SMD型半导体芯片元件。
10.如权利要求9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中含薄膜或厚膜双面线路的该线路板更包含双面连通设计的阵列式外电极，且该线路板单面更具有连通制成的两端水平引出电极，切割后以涂布、沾银、薄膜制程方式制作两端电极，使两端电极与预留电极接点进行连通。
11.如权利要求1、3、6、8或9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该芯片的规格包含：
芯片类型 端电极数量 长 宽 厚 备注 单颗01005 2个 0.4mm 0.2mm 0.2mm 厚度可微调 单颗0201 ≦3个 0.6mm 0.3mm 0.3mm 厚度可微调 单颗0402 ≦3个 1.0mm 0.5mm 0.5mm 厚度可微调 Array Type 0204 ≥4个 1.0mm 0.5mm 0.3mm 厚度可微调 Array Type 0306 ≥4个 1.6mm 0.8mm 0.4mm 厚度可微调 Array Type 0405 ≥4个 1.3mm 1.0mm 0.4mm 厚度可微调 Array Type 0508 ≥4个 2.0mm 1.3mm 0.5mm 厚度可微调 Array Type 0510 ≥4个 2.5mm 1.3mm 0.5mm 厚度可微调 Array Type 0612 ≥4个 3.0mm 1.5mm 0.6mm 厚度可微调
12.如权利要求1或3所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该芯片种类包含TVS二极管、萧特基二极管、开关二极管、齐纳二极管、整流二极管及晶体管的其中一种。
13.如权利要求1、3、6、8或9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该线路板是将薄膜或厚膜线路制作于陶瓷板、塑料板及复合材料板，亦可印刷于散热板上，以增加散热性能。
14.如权利要求1、3、6、8或9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该导电胶为各式导电胶连接半导体晶粒与印刷线路，可使用无铅导电胶，以取代公知的有铅锡膏，以制作出无铅化半导体封装产品。
15.如权利要求1、3、6、8或9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该绝缘封装材料是以淋膜、涂布、刮刀、灌注的至少一种方法覆盖该晶粒、导电胶及内部线路板，达到保护晶粒电性及物性特性的功能。
16.如权利要求1、3、6、8或9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该晶粒依据半导体晶粒设计方式，可制作成正向、反向或双向的芯片型半导体元件，设计方式可为一进一出或一进二出。
17.如权利要求8或9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该端电极是以电镀制程或采用免电镀即有焊性的端电极材料，使该端电极具有焊锡性，以制成贴片式单颗小尺寸及阵列型的芯片半导体元件。
18.如权利要求1、3、6、8或9所述贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法，其特征在于，其中该薄膜线路板材料是利用薄膜制程制作，厚膜线路可用印刷方式制作。
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