TWI651830B - 多功能小型化表面黏著型電子元件及其製法 - Google Patents

多功能小型化表面黏著型電子元件及其製法 Download PDF

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TWI651830B
TWI651830B TW104105626A TW104105626A TWI651830B TW I651830 B TWI651830 B TW I651830B TW 104105626 A TW104105626 A TW 104105626A TW 104105626 A TW104105626 A TW 104105626A TW I651830 B TWI651830 B TW I651830B
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Taiwan
Prior art keywords
die
electrode
grain
circuit board
diode
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TW104105626A
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English (en)
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TW201631736A (zh
Inventor
連清宏
黃興祥
黃興材
朱頡安
許鴻宗
陳逸偉
江榮峻
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立昌先進科技股份有限公司
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Priority to TW104105626A priority Critical patent/TWI651830B/zh
Priority to KR1020160014264A priority patent/KR101770729B1/ko
Priority to JP2016021801A priority patent/JP2016152416A/ja
Priority to US15/018,896 priority patent/US9443825B2/en
Priority to EP16155607.1A priority patent/EP3059761A3/en
Publication of TW201631736A publication Critical patent/TW201631736A/zh
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Publication of TWI651830B publication Critical patent/TWI651830B/zh

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Abstract

一種表面黏著型電子元件的特點，為單顆元件具備多種不同使用功能，其關鍵技術包括使用具特殊結構的晶粒，這種晶粒的底部及頂部構成進行電性連接的正、負電極，所以多顆這種晶粒可經過電性串聯、電性並聯或電性串聯/並聯的組合組成一種晶粒模組，藉選擇具備不同使用功能的晶粒組合，所述晶粒模組及所製成的表面黏著型電子元件即具備多種不同使用功能；所述表面黏著型電子元件的有利優點，在於製程簡單、可減少必要零組件的使用數量、可有效地減少線路佈置的長度及降低雜訊的干擾。

Description

多功能小型化表面黏著型電子元件及其製法
本發明涉及一種表面黏著型電子元件，尤指單顆電子元件就具備多種不同使用功能的小型化表面黏著型電子元件及其製法。
在半導體晶粒的傳統封裝製程中，導線架是完成封裝的關鍵性元件，要封裝不同型式、不同功能或不同用途的半導體晶粒，是需要設計不同形式的導線架進行封裝。
然而，為因應IC製程技術微小化的趨勢，電子資訊產品已走向輕薄短小，電子元件尺寸愈來愈小型化，連帶影響電子元件連結在印刷電路板上的技術，已演進到使用表面黏著型電子元件(下文簡稱SMD元件)。以小型化SMD元件而言，如果仍舊承襲習知導線架的封裝模式，在封裝製程中，除有不易將小型化二極體晶粒準確安裝到導線架上的缺點外，也經常發生安裝失誤偏離固定位置，導致有安裝精度上的問題，更導致封裝後的小型化SMD元件的使用特性易失真、甚至失效。
據此，現有技術中的習知導線架封裝方式，已不適 用且不利於對小型化SMD元件進行封裝。
此外，將兩種不同功能的元件以積層技術構成單顆SMD元件，是近來的流行趨勢。例如，將電感及電容組合成單顆SMD元件，即構成一種電感電容濾波器(或稱LC濾波器)，具有濾波功能。或者，將電阻及電容組合成單顆SMD元件，即構成一種電阻電容濾波器(或稱RC濾波器)，同樣具有濾波功能。
但是，以積層技術製成的具兩種不同功能的單顆SMD元件，因為兩種不同元件的燒結溫度及收縮率不相同，導致不同元件之間的緊密結合效果不佳，有易剝離及功能失效的問題。
有鑑於此，本發明的主要目的在於對現有技術中的小型化SMD元件提出封裝製程的改進，尤其是使用線路板取代習知導線架進行封裝，可解決及突破小型化SMD元件使用導線架進行封裝所導致的安裝精度問題。
本發明的多功能小型化SMD元件，為只使用一組晶粒模組的晶片型SMD元件，且單顆SMD元件的封裝尺寸為長度(L)介於0.4~2.0mm、寬度(W)介於0.2~1.3mm及厚度(T)介於0.2~0.8mm，具體結構由下列組件所構成，包括：一組晶粒模組，由單顆晶粒組成或由二顆或以上晶粒以電性串聯、電性並聯或電性串聯/並聯的組合組成，且所述晶粒模組的最下方 底部至少具有一第一電極，其最上方頂部至少具有一第二電極；一片底部線路板，其板面上設有一個線路電極，且與所述晶粒模組的第一電極構成電性連接；一片頂部線路板，其板面上設有一個線路電極，且與所述晶粒模組的各個第二電極構成電性連接；一個封膠體，與所述底部線路板及所述頂部線路板構成一體化結構，將所述晶粒模組及所述二個線路電極包裹在內，且保持所述二個線路電極的一端各自延伸到該封膠體的其中一側端面表面；及二個外端電極，各自包覆於由所述頂部線路板、所述封膠體及所述底部線路板三者共同構成一體化結構的其中一側端面，且與所對應的線路電極構成電性連接。
本發明的另一種多功能小型化SMD元件，為使用至少二組晶粒模組的陣列型SMD元件，且單顆SMD元件的封裝尺寸為長度(L)介於1.0~2.4mm、寬度(W)介於0.5~1.3mm及厚度(T)介於0.5~0.8mm。
本發明的多功能小型化SMD元件的製法，不使用含鉛錫膏的有鉛製程，適用於製成不具外引腳的小型化SMD元件，包括以下步驟：1)預製底面設有一下電極及頂面設有一上電極的晶粒；2)從步驟1)預製的晶粒中，選用單顆晶粒組成一組晶粒模組，或選用至少二顆晶粒以電性串聯、電性並聯或電性串聯/並聯的組合組 成一組晶粒模組，且所述晶粒模組的最下方底部至少具有一第一電極，其最上方頂部至少具有一第二電極；3)預製板面設有線路電極的底部線路板及頂部線路板；4)對所述底部線路板的線路電極印上、沾上或點上無鉛導電膏；5)透過無鉛導電膏的聯結，將步驟2)預製的晶粒模組的第一電極連接到所述底部線路板的線路電極；6)對步驟5)的晶粒模組的第二電極印上、沾上或點上無鉛導電膏；7)透過步驟6)的無鉛導電膏的聯結，將所述頂部線路板的線路電極連接到與其對應的所述晶粒模組的第二電極；8)對介於所述底部線路板及所述頂部線路板之間的空間實施絕緣材料封裝；9)取得經過切割後擁有二個預留線路電極的電子元件半成品；及10)對步驟9)的電子元件半成品的兩側端部分別製作一外端電極，且與所對應的線路電極分別構成電性連接，以製得所述小型化SMD元件。
作為優選實施例，構成所述晶粒模組的晶粒，是選自瞬態電壓抑制二極體晶粒、蕭基特二極體晶粒、開關二極體晶粒、齊納二極體晶粒、整流二極體晶粒、晶粒變阻器、晶粒電容、晶粒電阻、晶粒電感、晶粒保險絲、正溫度系數熱敏晶片電阻或負溫度系數熱敏晶片電阻的其中一種或其中至少二種的組合。
所述封膠體是選自陶瓷材料或塑膠材料。
所述底部線路板及頂部線路板是以陶瓷板、塑膠板、複合材料板或具散熱特性的散熱板製成。
所述外端電極是以銀(Ag)、金(Au)、銅(Cu)、鎳(Ni)、鈀(Pd)或鉑(Pt)單一或兩種以上成分或其金屬合金製成，且以塗佈、沾覆、蒸鍍薄膜或濺鍍薄膜製程製成。
本發明的多功能小型化SMD元件及其製法，具有以下有益效果：1.與現有技術中的封裝製程不同，使用底部線路板及頂部線路板取代習知導線架進行封裝，節省成本及製程簡單；2.所製成的單顆SMD元件可減少必要零組件的使用數量；尤其是，可以有效地減少線路佈置(lay out)的長度及降低雜訊的干擾；及3.所製成的單顆SMD元件具備多種不同使用功能，且排除失真或失效的問題，可滿足市場愈來愈小型化的電子元件需求。
10‧‧‧晶片型SMD元件
15‧‧‧陣列型SMD元件
20‧‧‧晶粒模組
21‧‧‧第一電極
22‧‧‧第二電極
Dn‧‧‧晶粒
31‧‧‧下電極
32‧‧‧上電極
40‧‧‧無鉛導電膏
50‧‧‧底部線路板
55‧‧‧薄膜或厚膜線路
56‧‧‧線路電極
60‧‧‧頂部線路板
65‧‧‧薄膜或厚膜線路
66‧‧‧線路電極
70‧‧‧絕緣材料
73‧‧‧切割線
75‧‧‧封膠體
80a‧‧‧外端電極
80b‧‧‧外端電極
D1‧‧‧晶粒或瞬態電壓抑制二極體晶粒
D2‧‧‧正溫度系數熱敏晶片電阻
D3‧‧‧晶粒電容
D4‧‧‧蕭基特二極體晶粒
D5‧‧‧顆粒保險絲
圖1為本發明的晶片型SMD元件放大圖。
圖2為本發明的陣列型SMD元件放大圖。
圖3為圖1的SMD元件使用單顆晶粒及具備單一使用功能的剖面結構圖。
圖4為圖1的晶片型SMD元件使用兩顆晶粒構成電性串聯封裝及具備兩項使用功能的剖面結構圖。
圖5為圖1的晶片型SMD元件使用兩顆晶粒構成電性並聯封裝及具備兩項使用功能的剖面結構圖。
圖6為圖1的晶片型SMD元件使用三顆晶粒構成電性串聯封裝及至少具備兩項使用功能的剖面結構圖。
圖7為圖1的晶片型SMD元件使用四顆晶粒構成電性串聯及並聯的組合封裝及至少具備兩項使用功能的剖面結構圖。
圖8為圖1的晶片型SMD元件的製作流程圖。
圖9為圖2的陣列型SMD元件使用三組晶粒模組構成封裝及具備多項使用功能的剖面結構圖。
圖10為圖4的晶片型SMD元件以一顆TVS二極體晶粒與另一顆PTC晶粒構成電性串聯封裝的等效電路圖，以說明具備溫度反應開關及突波防護雙項使用功能。
圖11為圖5的晶片型SMD元件以一顆TVS二極體晶粒與另一顆晶粒電容構成電性並聯封裝的等效電路圖，以說明具備突波防護及電容雙項使用功能。
圖12為圖5的晶片型SMD電子元件以一顆TVS二極體晶粒與另一顆蕭基特二極體晶粒構成電性並聯封裝的等效電路圖，以說明具備突波防護及防電壓逆流雙項使用功能。
如圖1及圖8所示，本發明的小型化表面黏著型電子元件10(以下簡稱晶片型SMD元件10)，具多種使用功能，都不使 用習知導線架，也都沒有由導線架延伸出來的外引腳，其基本構造，包括一組晶粒模組20、一片底部線路板50、一片頂部線路板60、二個線路電極56及66、一個封膠體75及二個外端電極80a及80b。
如圖8所示，所述晶粒模組20的基本構造，為底部至少具有一第一電極21及其頂部至少具有一第二電極22。而且，所述晶粒模組20得選擇只具備單一使用功能或是具備多種使用功能。
如圖3或圖8所示，所述晶粒模組20的組成，由單顆晶粒D1組成者，只具備單一使用功能；所述晶粒模組20選擇使用晶粒D1再以電性串聯、電性並聯或電性串聯/並聯的組合與其它不同使用功能的一顆或以上的晶粒Dn共同組成者，則具備至少兩種或以上的多種使用功能。
所述晶粒D1或晶粒Dn選自瞬態電壓抑制二極體晶粒(以下簡稱TVS二極體晶粒)、蕭基特二極體晶粒(Schottky Diode)、開關二極體晶粒(Switch Diode)、齊納二極體晶粒(Zener Diode)、整流二極體晶粒(Rectifiers Diode)、晶粒變阻器(Chip Varistor)、晶粒電容(Chip Capacitor)、晶粒電阻(Chip Resistor)、晶粒電感(Chip Inductor)、晶粒保險絲(Chip Fuse)、正溫度系數熱敏晶片電阻(以下簡稱PTC晶粒)或負溫度系數熱敏晶片電阻(以下簡稱NTC晶粒)的其中一種，但不限於此。
本發明的晶片型SMD元件10的使用功能，是依據所使用的晶粒模組20的種類而決定，故具備單一使用功能或兩項或以 上的多種使用功能。
如圖8所示，所述晶粒D1或所述晶粒Dn的正、負電極結構，是分別設於所述晶粒D1或所述晶粒Dn的底部及頂部。所述晶粒D1或所述晶粒Dn的具體實施例，為底部設有一個下電極31及其頂部設有一個上電極32，以構成所述晶粒D1或所述晶粒Dn進行電性連接的正、負電極。所以，所述晶粒D1或晶粒Dn的上電極32，藉無鉛導電膏40的聯結，可以電性串聯另一顆晶粒Dn的下電極31。
如圖3所示，所述晶粒模組20由單顆晶粒D1或晶粒Dn組成時，所述晶粒模組20的第一電極21及第二電極22，則由所述晶粒D1或所述晶粒Dn的下電極31及上電極32構成。
如圖4至圖7所示，所述晶粒模組20是由晶粒D1與其它晶粒Dn以電性串聯、電性並聯或電性串聯/並聯組合組成時，所述晶粒模組20的第一電極21，是由串聯及/或並聯在最下方的晶粒D1或晶粒Dn的下電極31構成，所述晶粒模組20的第二電極22，是由串聯及/或並聯在最上方的晶粒D1或晶粒Dn的上電極31構成。
如圖3至圖8所示，本發明的晶片型SMD元件10，藉無鉛導電膏40的聯結，將所述晶粒模組20的第一電極21及第二電極22與所述線路電極56及66分別構成電性聯結。
所述線路電極56是設於所述底部線路板50的板面 上，且與所述晶粒模組20的第一電極21構成電性連接。
同理，所述線路電極66是設於所述頂部線路板60的板面上，且與所述晶粒模組20的第二電極22構成電性連接。
所述封膠體75充實在所述底部線路板50及所述頂部線路板60的中間，與所述底部線路板50及所述頂部線路板60共同構成一體化結構，將所述所述晶粒模組20及所述線路電極56及66包裹在內，且保持所述線路電極56及66的一端各自延伸到該封膠體75的其中一側端面表面。
所述外端電極80a及80b各自包覆於由所述底部線路板50、所述封膠體75及所述頂部線路板60三者共同構成一體化結構的其中一側端面，且與所對應的線路電極56及66分別構成電性連接。
如圖2及圖9所示，本發明的晶片型SMD元件10的另一種具體實施例，是使用二組以上(包含二組)晶粒模組20且封裝成小型化SMD元件，本文定義為陣列型SMD元件15，其基本構造，包括至少二組晶粒模組20、一片底部線路板50、一片頂部線路板60、至少二個線路電極56、至少二個線路電極66、一個封膠體75、至少二個外端電極80a及至少二個外端電極80b。
其中，所述封膠體75包裹分開佈置的二組或以上晶粒模組20；所述底部線路板50的板面上設有二個或以上線路電極56，分別電性連接每組晶粒模組20的第一電極21；所述頂部線路板 60的板面上設有二個或以上線路電極66，分別電性連接每組晶粒模組20的第二電極22；每組晶粒模組20各自對應的二個外端電極80a及80b，且與所對應的線路電極56及66分別構成電性連接。
本發明的晶片型SMD元件10或陣列型SMD元件15的製法，是在封裝製程中使用底部線路板50及頂部線路板60取代習知導線架進行SMD元件的電極電性連接。尤其是，本發明的晶片型SMD元件10或陣列型SMD元件15，具有以下有益效果：1.與現有技術中的封裝製程不同，不使用習知導線架進行封裝，節省成本及製程簡單；及2.所製成的單顆SMD元件，具備多種不同使用功能，且製程簡單可減少必要零組件的使用數量；尤其是，可以有效地減少線路佈置(lay out)的長度及降低雜訊的干擾。
如圖8所示，本發明的晶片型SMD元件10的製法，包括以下驟：1.預製底面設有一下電極31及頂面設有一上電極32的晶粒Dn；2.從步驟1預製的晶粒Dn中，選用單顆晶粒Dn組成一組晶粒模組20或選用至少二顆晶粒Dn以電性串聯、電性並聯或電性串聯/並聯的組合組成一組晶粒模組20，且所述晶粒模組20的最下方底部至少具有一第一電極21，其最上方頂部至少具有一第二電極22；3.預製板面設有線路電極56的底部線路板50及板面設有線路電極66的頂部線路板60； 4.對所述底部線路板50的線路電極56印上、沾上或點上無鉛導電膏40；5.透過無鉛導電膏40的聯結，將步驟2預製的晶粒模組20的第一電極21連接到所述底部線路板50的線路電極56；6.對步驟5的晶粒模組20的第二電極22印上、沾上或點上無鉛導電膏40；7.透過步驟6的無鉛導電膏40的聯結，將所述頂部線路板60的線路電極66連接到與其對應的所述晶粒模組20的第二電極22；8.對介於所述底部線路板50及所述頂部線路板60之間的空間實施絕緣材料70封裝；9.沿著預定切割線73進行切割及取得切割後擁有二個預留線路電極56及66的電子元件半成品；10.對步驟9的電子元件半成品的兩側端部，各別以塗佈、沾銀或薄膜製程製作外端電極80a或80b，且與所對應的線路電極56及66分別構成電性連接，以製得所述小型化晶片型SMD元件10。
如圖8及圖9所示，本發明的陣列型SMD元件15的製法，除了使用至少二組晶粒模組20外，是沿用及承襲本發明的晶片型SMD元件10的製法及步驟。
在本發明的晶片型SMD元件10製法中，所述絕緣材料70或所述晶片型SMD元件10製品的封膠體75，可為陶瓷材料或塑膠材料，優選為使用環氧樹脂。
在本發明的晶片型SMD元件10製法中，所述底部線路板50(或所述頂部線路板60)是選用陶瓷板、塑膠板、複合材料板或具散熱特性的散熱板製成，其中，所述陶瓷板可選用氧化鋁板或氮化鋁板；所述塑膠板可選用PE板、PP板、PC板、聚亞醯胺板或工程塑膠製成的平板；所述複合材料板可選用碳纖板或玻纖板。
如圖8所示，所述底部線路板50(或所述頂部線路板60)的板面上，使用薄膜或厚膜印刷技術設有薄膜或厚膜線路55(或65)。其中，所述薄膜或厚膜線路55或65具備導電特性，其用途將構成本發明的晶片型SMD元件10(或陣列型SMD元件15)的線路電極56及66內電極。
在本發明的晶片型SMD元件10製法中或其製品，所述外端電極80a及80b是以塗佈、沾覆、蒸鍍薄膜或濺鍍薄膜製製作，其材質可選自銀(Ag)、金(Au)、銅(Cu)、鎳(Ni)、鈀(Pd)或鉑(Pt)單一成分或其兩種成上以上混合，或是其金屬合金，但不此為限。
在本發明的晶片型SMD元件10製法中或其製品，所述無鉛導電膏40的成分，選自含銀(Ag)、錫(Sn)、銅(Cu)、金(Au)、鎳(Ni)、鈀(Pd)或鉑(Pt)單一成分或其兩種成上以上混合。
根據前面所述，本發明的晶片型SMD元件10製法，可解決及突破小型化SMD元件使用導線架進行封裝所導致的安裝精度問題，可應用於製作小型化晶片型SMD元件10，尤其是適用於製成如圖1所示的長度(L)介於0.4~2.0mm、寬度(W)介於0.2~1.3mm且 厚度(T)介於0.2~0.8mm的晶片型SMD元件10，優選為適用於製成尺寸規格如表1所示的晶片型SMD元件10。
本發明的晶片型SMD元件10製法，也適用於製成如圖2所示的長度(L)介於1.0~2.4mm、寬度(W)介於0.5~1.3mm且厚度(T)介於0.5~0.8mm的陣列型SMD元件15，優選為適用於製成尺寸規格如表2所示的陣列型SMD元件15。
除此之外，本發明的晶片型SMD元件10製法，不使用含鉛錫膏的有鉛製程，可滿足國際上各項環保要求。
以下實施例將闡明本發明的晶片型SMD元件10或陣列型SMD元件15具有多種使用功能，但本發明的權利範圍不以實施例為限。
實施例1：
如圖3所示，本實施例的SMD元件10，是選用單顆晶粒D1製成，所述晶粒D1選用瞬態電壓抑制二極體晶粒(TVS Diode)，所製成的SMD元件10具備突波防護單一使用功能。
實施例2：
如圖4所示，本實施例的SMD元件10，是選用實施例1的瞬態電壓抑制二極體晶粒D1與另一顆正溫度系數熱敏晶片電阻(PTC Chip Thermistor)D2構成電性串聯封裝製成，其等效電路圖如圖10所示，所製成的SMD元件10具備溫度反應開關及突波防護雙項使用功能。
實施例3：
如圖5所示，本實施例的SMD元件10，是選用實施例1的瞬態電壓抑制二極體晶粒D1與另一顆晶粒電容(Chip Capacitor)D3構成電性並聯封裝製成，其等效電路圖如圖11所示，所製成的SMD元件10具備突波防護及濾波雙項使用功能。
實施例4：
如圖5所示，本實施例的SMD元件10，是選用實施例1的瞬態電壓抑制二極體晶粒D1與蕭基特二極體晶粒(Schottky Diode)D4構成電性並聯封裝製成，其等效電路圖如圖12所示，所製成的SMD元件10具備突波防護及防電壓逆流雙項使用功能。
實施例5：
如圖6所示，本實施例的SMD元件10，是選用實施例1的瞬態電壓抑制二極體晶粒D1、一顆正溫度系數熱敏晶片電阻D2與一顆粒保險絲(Chip Fuse)D5構成電性串聯封裝製成，所製成的SMD元件10具備電路斷開、溫度反應開關及突波防護三項使用功能。
實施例6：
如圖7所示，本實施例的SMD元件10，是選用實施例1的瞬態電壓抑制二極體晶粒D1與另一顆正溫度系數熱敏晶片電阻D2構成電性串聯，另使用一顆晶粒電容D3與另一顆粒保險絲D5構成電性串聯，再對二組電性串聯晶粒施以電性並聯封裝製成，所製成的SMD元件10具備溫度反應開關、突波防護、濾波及電路斷開四項使用功能。
實施例7-14：
參照表3，各實施例的SMD元件10，選用二顆不同使用功能的晶粒，以電性並聯或電性串聯封裝製成，所製成的SMD元件10具備表3所列的雙項使用功能。
實施例15-16：
參照表4，各實施例的SMD元件10，選用三顆晶粒以電性並聯及串聯封裝製成，所製成的SMD元件10具備表4所列的三項使用功 能。

Claims (4)

  1. 一種多功能表面黏著型電子元件，為長度(L)介於0.4~2.0mm、寬度(W)介於0.2~1.3mm及厚度(T)介於0.2~0.8mm的晶片型表面黏著型電子元件，其特徵在於，包括：一組晶粒模組，由單顆晶粒組成或由二顆或以上晶粒以電性串聯、電性並聯或電性串聯/並聯的組合組成，且所述晶粒模組的最下方底部至少具有一第一電極，其最上方頂部至少具有一第二電極；其中，所述晶粒選自瞬態電壓抑制二極體晶粒、蕭基特二極體晶粒、開關二極體晶粒、齊納二極體晶粒、整流二極體晶粒、晶粒變阻器、晶粒電容、晶粒電阻、晶粒電感、晶粒保險絲、正溫度系數熱敏晶片電阻或負溫度系數熱敏晶片電阻的其中一種或其中至少二種的組合；一片底部線路板，以陶瓷板、塑膠板、複合材料板或具散熱特性的散熱板製成；其板面上設有一個線路電極，且與所述晶粒模組的各個第一電極構成電性連接；一片頂部線路板，以陶瓷板、塑膠板、複合材料板或具散熱特性的散熱板製成；其板面上設有一個線路電極，且與所述晶粒模組的各個第二電極構成電性連接；一個封膠體，與所述底部線路板及所述頂部線路板構成一體化結構，將所述晶粒模組及所述二個線路電極包裹在內，並且保持所述二個線路電極的一端各自延伸到該封膠體的其中一側端面表面；及二個外端電極，以銀(Ag)、金(Au)、銅(Cu)、鎳(Ni)、鈀(Pd)或鉑(Pt)單一或兩種以上成分或其金屬合金製成，且各自包覆於由所述頂部線路板、所述封膠體及所述底部線路板三者共同構成一體化結構的其中一側端面， 且與所對應的線路電極構成電性連接。
  2. 如申請專利範圍第1項所述之多功能表面黏著型電子元件，其特徵在於，所述晶粒模組由二顆晶粒以電性串聯或電性並聯的組合組成，其中一顆晶粒選自瞬態電壓抑制二極體晶粒、蕭基特二極體晶粒、開關二極體晶粒、齊納二極體晶粒、整流二極體晶粒或晶粒變阻器的其中一種；另一顆晶粒選自晶粒電容、晶粒電阻、晶粒電感、晶粒保險絲、正溫度系數熱敏晶片電阻或負溫度系數熱敏晶片電阻的其中一種。
  3. 一種多功能表面黏著型電子元件，為長度(L)介於1.0~2.4mm、寬度(W)介於0.5~1.3mm及厚度(T)介於0.5~0.8mm的陣列型表面黏著型電子元件，其特徵在於，包括：二組或以上分開且平行佈置的晶粒模組，且每組晶粒模組由單顆晶粒組成或由二顆或以上晶粒以電性串聯、電性並聯或電性串聯/並聯的組合組成，且每組晶粒模組的最下方底部至少具有一第一電極，其最上方頂部至少具有一第二電極；其中，所述晶粒選自瞬態電壓抑制二極體晶粒、蕭基特二極體晶粒、開關二極體晶粒、齊納二極體晶粒、整流二極體晶粒、晶粒變阻器、晶粒電容、晶粒電阻、晶粒電感、晶粒保險絲、正溫度系數熱敏晶片電阻或負溫度系數熱敏晶片電阻的其中一種或其中至少二種的組合；一片底部線路板，以陶瓷板、塑膠板、複合材料板或具散熱特性的散熱板製成；其板面上設有一個線路電極，且與每組晶粒模組的各個第一電極構成電性連接；一片頂部線路板，以陶瓷板、塑膠板、複合材料板或具散熱特性的散熱板 製成；其板面上設有一個線路電極，且與每組晶粒模組的各個第二電極構成電性連接；一個封膠體，與所述底部線路板及所述頂部線路板構成一體化結構，將每組晶粒模組及所述二個線路電極包裹在內，並且保持所述二個線路電極的一端各自延伸到該封膠體的其中一側端面表面；及二個外端電極，以銀(Ag)、金(Au)、銅(Cu)、鎳(Ni)、鈀(Pd)或鉑(Pt)單一或兩種以上成分或其金屬合金製成，且各自包覆於由所述頂部線路板、所述封膠體及所述底部線路板三者共同構成一體化結構的其中一側端面，且與所對應的線路電極構成電性連接。
  4. 一種多功能表面黏著型電子元件的製法，其特徵在於，包括以下步驟：1)預製底面設有一下電極及頂面設有一上電極的晶粒；其中，所述晶粒為瞬態電壓抑制二極體晶粒、蕭基特二極體晶粒、開關二極體晶粒、齊納二極體晶粒、整流二極體晶粒、晶粒變阻器、晶粒電容、晶粒電阻、晶粒電感、晶粒保險絲、正溫度系數熱敏晶片電阻或負溫度系數熱敏晶片電阻的其中一種；2)從步驟1)預製的晶粒中，選用單顆晶粒組成一組晶粒模組或選用至少二顆晶粒以電性串聯、電性並聯或電性串聯/並聯的組合組成一組晶粒模組，且所述晶粒模組的最下方底部至少具有一第一電極，其最上方頂部至少具有一第二電極；3)以陶瓷板、塑膠板、複合材料板或具散熱特性的散熱板，預製板面設有線路電極的底部線路板及頂部線路板；4)對所述底部線路板的線路電極印上、沾上或點上無鉛導電膏； 5)透過無鉛導電膏的聯結，將步驟2)預製的晶粒模組的第一電極連接到所述底部線路板的線路電極；6)對步驟5)的晶粒模組的第二電極印上、沾上或點上無鉛導電膏；7)透過步驟6)的無鉛導電膏的聯結，將所述頂部線路板的線路電極連接到與其對應的所述晶粒模組的第二電極；8)對介於所述底部線路板及所述頂部線路板之間的空間實施絕緣材料封裝；9)取得經過切割後擁有二個預留線路電極的電子元件半成品；及10)對步驟9)的電子元件半成品的兩側端部分別製作一外端電極，且與所對應的線路電極分別構成電性連接，以製得所述表面黏著型電子元件。
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