JP2015133487A - 小型smdダイオードパッケージおよびその製造プロセス - Google Patents
小型smdダイオードパッケージおよびその製造プロセス Download PDFInfo
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- JP2015133487A JP2015133487A JP2014260789A JP2014260789A JP2015133487A JP 2015133487 A JP2015133487 A JP 2015133487A JP 2014260789 A JP2014260789 A JP 2014260789A JP 2014260789 A JP2014260789 A JP 2014260789A JP 2015133487 A JP2015133487 A JP 2015133487A
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- diode
- circuit board
- package
- electrode
- electrodes
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Abstract
Description
1.製造プロセスを簡略化し、製作費を低減すること。
2.従来使用されているリードフレームの代わりに回路基板を使用することによって、小型SMDダイオードパッケージを製造する際の精度および精密度を改良すること。
3.製造された小型SMDダイオードパッケージが、歪みまたは欠陥なく、確実に優れたダイオード特性を備えるようにすること。
4.いっそう小型のSMD電子デバイスをより適切に製造すること。
ダイオードアレイパッケージ20は、開示されている前述のSMDダイオードチップパッケージ10のような下部構造を有し、この基本構造は、少なくとも、底面回路基板50、2つ以上のダイオードチップ30a、30bまたは30cを入れるためのカプセル封じ75、および、対応するダイオードチップ30a、30bまたは30cにそれぞれ電気的に接続された外部電極80a、80bの2つ以上の対を含む。
ダイオードアレイパッケージ20はさらに、上部回路電極66a(または上部回路電極66a、66bの対)が置かれた上面回路基板60を有し、前記上部回路電極66a(または前記上部回路電極66aおよび66bの対)は、それぞれ、各対応するダイオードチップ30b(または30c)の対応する高位の電極32に対応し、かつ、電気的に接続する。そして、外部電極80aおよび80bの各対は、各対応するダイオードチップ30b(または30c)に対応し、カプセル封じ75の2つの対向する端部上に別個に配置され、回路電極56aおよび56bの各対応する対、ならびに、前記対応する上部回路電極66a(または前記上部回路電極66aおよび66bの対)にそれぞれ電気的に接続する。
1.パッケージングプロセスの過程で、パッケージングのために従来使用されているリードフレームの代わりに底面回路基板50が使用される。
2.図3を参照すると、底面回路基板50には、1アレイに分離されかつ配置される複数の薄膜または厚膜回路55(以降、配列膜回路55という)が置かれており、底面回路基板50上で互いに分離しかつ互いに隣接する位置に位置する2つの配列膜回路55は、以降、2つの間隔があけられた配列膜回路56という。
3.ペーストを施すプロセスは、底面回路基板50の各配列膜回路55の2つの端部上でCCD画像登録を使用して行われ、それによって、無鉛の導体ペースト40は、その所定の場所に精確につけられかつ施される。
4.チップボンディングプロセスは、CCD画像登録を使用して行われ、それによって、図3に示されるように、小型ダイオードチップ30は、底面回路基板50の2つの間隔をあけられた配列膜回路56の1つの対応する端部を精確に配列したその底部表面上に既に形成されているそれ自体の正電極および負電極を有することが可能である。さらに詳細には、対応する位置で被覆された無鉛の導体ペースト40によって、2つの間隔をあけられた配列膜回路56との電気接続を行うことによるダイオードチップ30の正電極および負電極には、短絡の危険性はない。
A1.正電極および負電極の役割を果たす2つの下部電極31を備える底面を有するダイオードチップ30aを前もって製造するステップと、
A2.配列膜回路55を有する底面回路基板50を前もって製造するステップと、
A3.底面回路基板50の各配列膜回路55の2つの端部に対して無鉛の導体ペースト40をつけるまたは施すために、CCD画像登録によってペーストを施すステップと、
A4.図3に示されるように、底面回路基板50の2つの間隔があけられた配列膜回路56の2つの対向する対応端部ごとを既定の接続端子とし、かつ、ダイオードチップ30aの2つの下部電極31を、無鉛の導体ペースト40によって底面回路基板50の既定の接続端子に確実にかつ電気的に接続できるようにするために、CCD画像登録によってチップボンディングを行うステップと、
A5.全てのダイオードチップ30aおよび全ての配列膜回路55を入れるための絶縁パッケージ70のパッケージングを行うステップであって、チップボンディング後、底面回路基板50上にパッケージされた絶縁材料を使用することによって行われる、パッケージングを行うステップと、
A6.CCD画像登録によって底面回路基板50の全ての配列膜回路55上で切線73を画成し、かつ、切線73に沿って絶縁パッケージ70および底面回路基板50を切断することによって半製品のダイオードパッケージ15aを達成するようにして、底面回路基板50上に置かれた全ての配列膜回路55を、2つの別個の回路電極に切断できるようにする、すなわち、半製品のダイオードパッケージ15aが、ダイオードチップ30aと、底面回路基板50と、配列膜回路55を切断することによって形成された2つの回路電極56a、56bと、絶縁パッケージ70を切断することによって形成されたカプセル封じ75とで構成されるステップと、
A7.半製品のダイオードパッケージ15aの2つの端部上に外部電極80a、80bを形成するために、被覆プロセス、銀浸漬プロセス、または、製膜プロセスを行い、かつ、第1の実施形態のダイオードパッケージ10aを達成するために、外部電極80a、80bを対応する回路電極56a、56bに電気的に接続させるステップと、
を含む。
B1.ステップA1と同じステップと、
B2.ステップA2と同じステップと、
B3.ステップA3と同じステップと、
B4.ステップA4と同じステップと、
B5.ステップA5と同じステップと、
B6.絶縁パッケージ70の硬化表面上に接着剤層45を被覆し、かつ、その上に上部カバー53を覆うステップと、
B7.ステップA6と同様のステップであって、ダイオードチップ30aと、底面回路基板50と、配列膜回路55を切断することによって形成された2つの回路電極56a、56bと、絶縁パッケージ70および上部カバー53を切断することによって形成されたカプセル封じ75とで構成される半製品のダイオードパッケージ15bを達成するステップと、
B8.ステップA7と同様のステップであって、半製品のダイオードパッケージ15bの2つの端部上に外部電極80a、80bを作り、第2の実施形態のダイオードパッケージ10bを達成するステップと、
を含む。
C1.底面が2つの下部電極31を備え、上面が高位の電極32(または2つの高位の電極32)を備えたダイオードチップ30b(または30c)を前もって製造するステップと、
C2.配列膜回路55が上に置かれた底面回路基板50、および、配列膜回路65が上に置かれた上面回路基板60を前もって製造するステップと、
C3.底面回路基板50の各配列膜回路55の2つの端部に対して無鉛の導体ペースト40をつけるまたは施すために、CCD画像登録によってペーストを施すステップと、
C4.ダイオードチップ30b(または30c)の2つの底部回路31を、ステップC3の無鉛の導体ペースト40によって底面回路基板50の既定の接続端子に確実にかつ電気的に接続できるように、CCD画像登録によってチップボンディングを行うステップと、
C5.ダイオードチップ30b(または30c)の高位の電極32ごとに無鉛の導体ペースト40をつけるまたは施すために、CCD画像登録によってペーストを施すステップと、
C6.CCD画像登録によって上面回路基板60で覆って、上面回路基板60の既定の接続端子を、ステップC5の無鉛の導体ペースト40によってダイオードチップ30b(または30c)の高位の電極32に精確に接続できるようにするステップと、
C7.全てのダイオードチップ30b(または30c)および全ての配列膜回路55および65を入れるための絶縁パッケージ70のパッケージングを行うステップであって、チップボンディング後、底面回路基板50と上面回路基板60との間の空間に対してパッケージされた絶縁材料を使用することによって行われる、パッケージングを行うステップと、
C8.CCD画像登録によって底面回路基板50の全ての配列膜回路55上で切線73を画成し、かつ、切線73に沿って上面回路基板60、絶縁パッケージ70および底面回路基板50を切断することによって半製品のダイオードパッケージ15c(または15d)を達成するようにするステップと、
C9.半製品のダイオードパッケージ15c(または15d)の2つの端部上に外部電極80a、80bを形成するために、被覆プロセス、銀浸漬プロセス、または、製膜プロセスを行い、かつ、本発明の第3(または第4)の実施形態のダイオードパッケージ10c(または10d)を達成するために、外部電極80a、80bを対応する回路電極56a、56bおよび66a(または56a、56b、66aおよび66b)に電気的に接続させるようにするステップと、
を含む。
Claims (8)
- TVSダイオード、ショットキーダイオード、スイッチダイオード、ツェナーダイオード、または、整流ダイオードから形成され、かつ、正電極および負電極を備えた底面を有する第1のダイオードチップと、
セラミック板、プラスチック板、複合材シート、または、放熱板から形成される底面回路基板と、
前記底面回路基板上に別個に置かれ、かつ、それぞれ、前記第1のダイオードチップの前記底面上の前記正電極および前記負電極に電気的に接続される2つの回路電極と、
カプセル封じであって、前記第1のダイオードチップおよび前記2つの回路電極を入れるために、かつ、前記2つの回路電極が、前記カプセル封じの1端部まで延在しかつ当該端部に触れている1端部を有することを可能とするために、前記底面回路基板と一体化させるように、セラミック材料またはプラスチック材料から形成されるカプセル封じと、
銀(Ag)、スズ(Sn)、銅(Cu)、金(Au)、ニッケル(Ni)、パラジウム(Pd)、および、白金(Pt)から形成され、それぞれが、前記カプセル封じおよび前記底面回路基板によって形成された一体構造の1端部を覆い、かつ、それぞれが、前記カプセル封じの1端部に触れている対応する回路電極に電気的に接続される、2つの外部電極と、を含む、小型SMDダイオードパッケージ。 - 前記カプセル封じの上面に取り付けられた上部カバーをさらに含み、各前記外部電極は、前記上部カバー、前記カプセル封じ、および、前記底面回路基板によって形成された前記一体構造の1端部を覆い、かつ、それぞれが前記カプセル封じの1端部に触れている前記対応する回路電極に電気的に接続する、請求項1に記載のSMDダイオードパッケージ。
- 前記第1のダイオードチップの第1のダイオードの全体の機能を備えるのに加えて、前記第1のダイオードチップの代わりに使用される第2のダイオードチップであって、高位の電極を備えた上面をさらに有する第2のダイオードチップと、
セラミック板、プラスチック板、複合材シート、または、放熱板から形成され、上部回路電極が上に置かれており、前記第2のダイオードチップの前記高位の電極に電気的に接続される上面回路基板と、をさらに含み、
前記カプセル封じは、前記上面回路基板および底面回路基板と一体化して、さらに、中に前記上部回路電極を入れ、かつ、前記上部回路電極が前記カプセル封じの1端部まで延在しかつ当該1端部で触れている1端部を有することを可能にし、各前記外部電極は、前記上面回路基板、前記カプセル封じ、および、前記底面回路基板によって形成された前記一体構造の1端部を覆って、前記カプセル封じの1端部に触れている前記対応する回路電極に電気的に接続し、前記2つの外部電極のうちの1つはさらに、前記上部回路電極に電気的に接続することを特徴とする、請求項1に記載のSMDダイオードパッケージ。 - 前記第1のダイオードチップの第1のダイオードの全体の機能を備えるのに加えて、前記第1のダイオードチップの代わりに使用される第3のダイオードチップであって、正電極および負電極を備えた上面をさらに有する第3のダイオードチップと、
セラミック板、プラスチック板、複合材シート、または、放熱板から形成され、2つの分離した上部回路電極が上に置かれており、それぞれ、前記第3のダイオードチップの前記上面における前記正電極および負電極に電気的に接続される上面回路基板と、をさらに含み、
前記カプセル封じは、前記上面回路基板および前記底面回路基板と一体化して、さらに、前記2つの上部回路電極を中に入れ、かつ、前記上部回路電極が前記カプセル封じの1端部まで延在しかつ当該1端部に触れている1端部を有することを可能にし、各前記外部電極は、前記上面回路基板、前記カプセル封じ、および、前記底面回路基板によって形成された前記一体構造の1端部を覆って、それぞれ、前記カプセル封じの1端部に触れている対応する回路電極および上部回路電極に電気的に接続することを特徴とする、請求項1に記載のSMDダイオードパッケージ。 - 前記SMDダイオードパッケージは、0.4〜1.0mmの長さ(L)、0.2〜0.5mmの幅(W)、および、0.2〜0.5mmの厚さ(T)の小型サイズを有することを特徴とする、請求項1〜4のうちいずれか一項に記載のSMDダイオードパッケージ。
- 前記SMDダイオードパッケージは、1.0〜2.4mmの長さ(L)、0.5〜1.0mmの幅(W)、および、0.4〜0.8mmの厚さ(T)の小型サイズを有し、かつ、1アレイに分離されかつ配置される2つ以上の前記第1のダイオードチップ、前記第2のダイオードチップ、または、前記第3のダイオードチップを含むことを特徴とする、請求項1〜4のうちいずれか一項に記載のSMDダイオードパッケージ。
- 小型SMDダイオードパッケージを製造するためのプロセスであって、
1)TVSダイオード、ショットキーダイオード、スイッチダイオード、ツェナーダイオード、または、整流ダイオードから形成され、かつ、正電極および負電極を備えた底面を有するダイオードチップを前もって製造するステップと、
2)セラミック板、プラスチック板、複合材シート、または、放熱板から形成され、かつ、複数の配列膜回路が上に置かれている底面回路基板を前もって製造するステップと、
3)前記底面回路基板の各配列膜回路の2つの端部に対して無鉛の導体ペーストをつけるまたは施すために、CCD画像登録によってペーストを施すステップと、
4)前記ダイオードチップの前記正電極および前記負電極を、前記底面回路基板上で互いから分離されかつ互いに隣接する位置に位置する2つの配列膜回路に確実にかつ電気的に接続できるようにするために、CCD画像登録によってチップボンディングを行うステップと、
5)前記底面回路基板上の全てのボンディング済みダイオードチップおよび全ての配列膜回路を入れるために、セラミック材料またはプラスチック材料から形成された絶縁パッケージのパッケージングを行うステップと、
6)前記絶縁パッケージの硬化表面上に接着剤層を被覆し、かつ、その上に上部カバーを載置する任意のステップと、
7)それぞれが2つの逆回路電極を有する半製品のダイオードパッケージを達成するようにCCD画像登録によって切断を行うステップであって、当該2つの逆回路電極のそれぞれが、前記半製品のダイオードパッケージの1つの対向する端部に対応して触れている1端部を有する、切断を行うステップと、
8)外部電極を、前記半製品のダイオードパッケージの2つの端部で覆うようにし、かつ、被覆プロセス、銀浸漬プロセス、または、製膜プロセスによって、ステップ7)の前記半製品のダイオードパッケージの対応する触れている回路電極に電気的に接続させることによって、前記小型SMDダイオードパッケージが達成されるステップと、を含む、小型SMDダイオードパッケージを製造するためのプロセス。 - 小型SMDダイオードパッケージを製造するためのプロセスであって、
1)TVSダイオード、ショットキーダイオード、スイッチダイオード、ツェナーダイオード、または、整流ダイオードから形成され、底面が第1の正電極および第1の負電極を備え、上面が第2の正電極および/または第2の負電極を備えるダイオードチップを前もって製造するステップと、
2)双方が、セラミック板、プラスチック板、複合材シート、または、放熱板から形成され、かつ、複数の配列膜回路が上に置かれている底面回路基板および上面回路基板を前もって製造するステップと、
3)前記底面回路基板の各配列膜回路の2つの端部に対して無鉛の導体ペーストをつけるかまたは施すために、CCD画像登録によってペーストを施すステップと、
4)前記ダイオードチップの前記第1の正電極および前記第1の負電極を、前記無鉛導体ペーストによって、前記底面回路基板上で互いから分離されかつ互いに隣接する位置に位置する2つの配列膜回路に確実にかつ電気的に接続できるようにするために、CCD画像登録によってチップボンディングを行うステップと、
5)前記ダイオードチップの前記第2の正電極および/または前記第2の負電極上に無鉛の導体ペーストをつけるまたは施すために、CCD画像登録によってペーストを施すステップと、
6)前記ダイオードチップの前記第2の正電極および/または前記第2の負電極が、前記無鉛の導体ペーストによって、前記上面回路基板の各対応する配列膜回路に電気的に接続できるようにするために、CCD画像登録によって、前記上面回路基板を前記ダイオードチップの上面上で覆うように載置することを行うステップと、
7)セラミック材料またはプラスチック材料から形成され、かつ、前記底面回路基板および前記上面回路基板双方上の全てのボンディング済みダイオードチップおよび全ての配列膜回路を入れるために、前記底面回路基板と前記上面回路基板との間の空間に充填される絶縁パッケージのパッケージングを行うステップと、
8)それぞれが3つまたは4つの逆回路電極を有する半製品のダイオードパッケージを達成するようにCCD画像登録によって切断を行うステップであって、当該3つまたは4つの逆回路電極のそれぞれが、前記半製品のダイオードパッケージの1つの対向する端部で対応して触れている1端部を有する、切断を行うステップと、
9)前記半製品のダイオードパッケージの2つの端部で外部電極を覆うようにし、かつ、被覆プロセス、銀浸漬プロセス、または、製膜プロセスによって、ステップ8)の前記半製品のダイオードパッケージの対応する触れている回路電極に電気的に接続させることによって、前記小型SMDダイオードパッケージが達成されるステップと、を含む、小型SMDダイオードパッケージを製造するためのプロセス。
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