JP2008198805A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
【解決手段】ベースとなる金属基板100の上に多層配線基板20を構築し、多層配線基板20の複数の領域上にそれぞれ半導体チップ30をフリップチップ実装する。複数の半導体チップ30を封止樹脂層40を用いて封止した後、金属基板100を除去する。この後、多層配線基板20の下面にはんだボール等を搭載し、半導体装置を個片化する。
【選択図】図6
Description
次に、図5(A)および図5(B)に示すように、半導体チップ30の外部電極端子が設けられた表面をフェイスダウンにした状態で、外部電極端子に設けられた各はんだバンプ32とそれらに対応する多層配線基板20の上面のC4バンプ27とをはんだ付けすることにより、複数の半導体チップ30を多層配線基板20にフリップチップ実装する。なお、図5以下では、多層配線基板20の詳細な構造については簡略化する。はんだバンプ32とC4バンプ27との接合は、たとえば、周知のリフロー処理により行うことができる。
次に、図6(A)に示すように、トランスファーモールド法、ポッディングなどの樹脂封止方法を用いて、多層配線基板20の上に隣接する多層配線層を跨るように封止樹脂層40を成型する。これにより、多層配線基板20上の複数の領域にそれぞれ実装された半導体チップ30が一度に封止される。なお、封止樹脂層40を成型は、既存のモールド装置、金型等を用いることが可能であるため、製造コストの増加を防ぐことができる。
この他、リッドが設けられた半導体装置を製造する場合について説明する。上述した封止樹脂形成では、多層配線基板20の上面全体に封止樹脂層40が形成されている。これに対して、半導体装置にリッドを設ける場合には、図1〜図5を参照して説明した工程の後、図8(A)に示すように、所定の金型を用いて、金属基板100に構築された多層配線基板20の上に各半導体チップ30の周囲に離間した封止樹脂層40を設ける。封止樹脂層40の上面の位置は、各半導体チップ30の上面の位置と等しいか、各半導体チップ30の上面の位置からたとえば1〜3mm程度高い位置とする。
Claims (6)
- 金属基板の上の複数の領域に多層配線層をそれぞれ構築する工程と、
前記各多層配線層の上面にそれぞれ半導体チップを実装する工程と、
隣接する多層配線層を跨るように前記各多層配線層の上に封止樹脂を成型する工程と、
前記金属基板を前記各多層配線層から除去する工程と、
各領域間を切断し、前記各多層配線層を個片化する工程と、
を備えることを特徴とする半導体装置の製造方法。 - 少なくとも1層の層間絶縁膜によって相互に接続されるように前記各多層配線を構築し、
前記各多層配線層を個片化する工程において、前記各領域間の前記封止樹脂および前記層間絶縁膜が切断されることを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記金属基板を剥離した後、前記各多層配線層の下面にはんだボールを搭載する工程をさらに備えることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 金属基板の上の複数の領域に多層配線層をそれぞれ構築する工程と、
前記各多層配線層の上面にそれぞれ半導体チップを実装する工程と、
前記各多層配線層の上に封止樹脂を成型する工程と、
前記封止樹脂および前記半導体チップの上面に熱インターフェース材料を介して、放熱部材を設置する工程と、
前記金属基板を前記各多層配線層から除去する工程と、
前記各領域を切断し、前記各多層配線層および放熱部材を個片化する工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記封止樹脂を成型する工程において、前記半導体チップの周囲に離間して前記封止樹脂が形成されることを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記金属基板を剥離した後、前記各多層配線層の下面にはんだボールを搭載する工程をさらに備えることを特徴とする請求項4または5に記載の半導体装置の製造方法。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011096903A (ja) * | 2009-10-30 | 2011-05-12 | Shinko Electric Ind Co Ltd | 半導体素子実装配線基板の製造方法 |
JP2014011289A (ja) * | 2012-06-29 | 2014-01-20 | Ibiden Co Ltd | 電子部品及び電子部品の製造方法 |
TWI474413B (zh) * | 2009-01-15 | 2015-02-21 | Chipmos Technologies Inc | 晶片封裝結構的製程 |
JP2015133487A (ja) * | 2014-01-10 | 2015-07-23 | 立昌先進科技股▲分▼有限公司 | 小型smdダイオードパッケージおよびその製造プロセス |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000349203A (ja) * | 1999-06-07 | 2000-12-15 | Nec Corp | 回路装置、その製造方法 |
JP2002033411A (ja) * | 2000-07-13 | 2002-01-31 | Nec Corp | ヒートスプレッダ付き半導体装置及びその製造方法 |
JP2004047666A (ja) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | 多層配線基板とその製造方法および樹脂封止型半導体装置の製造方法 |
JP2006186321A (ja) * | 2004-12-01 | 2006-07-13 | Shinko Electric Ind Co Ltd | 回路基板の製造方法及び電子部品実装構造体の製造方法 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000349203A (ja) * | 1999-06-07 | 2000-12-15 | Nec Corp | 回路装置、その製造方法 |
JP2002033411A (ja) * | 2000-07-13 | 2002-01-31 | Nec Corp | ヒートスプレッダ付き半導体装置及びその製造方法 |
JP2004047666A (ja) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | 多層配線基板とその製造方法および樹脂封止型半導体装置の製造方法 |
JP2006186321A (ja) * | 2004-12-01 | 2006-07-13 | Shinko Electric Ind Co Ltd | 回路基板の製造方法及び電子部品実装構造体の製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI474413B (zh) * | 2009-01-15 | 2015-02-21 | Chipmos Technologies Inc | 晶片封裝結構的製程 |
JP2011096903A (ja) * | 2009-10-30 | 2011-05-12 | Shinko Electric Ind Co Ltd | 半導体素子実装配線基板の製造方法 |
JP2014011289A (ja) * | 2012-06-29 | 2014-01-20 | Ibiden Co Ltd | 電子部品及び電子部品の製造方法 |
JP2015133487A (ja) * | 2014-01-10 | 2015-07-23 | 立昌先進科技股▲分▼有限公司 | 小型smdダイオードパッケージおよびその製造プロセス |
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