JP2007115774A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2007115774A JP2007115774A JP2005303395A JP2005303395A JP2007115774A JP 2007115774 A JP2007115774 A JP 2007115774A JP 2005303395 A JP2005303395 A JP 2005303395A JP 2005303395 A JP2005303395 A JP 2005303395A JP 2007115774 A JP2007115774 A JP 2007115774A
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- semiconductor device
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- insulating layer
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Abstract
【解決手段】支持基板上に金属膜を形成する工程と、金属膜上に、第1パッド及び第1絶縁層を含む第1配線層を形成する工程と、第1配線層上に、第1パッドに電気的に接続する第2パッドを形成する工程と、第2パッドを覆うように熱可塑性樹脂からなる第2絶縁層7を形成する工程と、第2絶縁層7を加熱し軟化させた状態で、第1半導体チップ9と第2パッドと電気的に接続し、同時に、第1半導体チップ9と第1配線層との間の間隙を第2絶縁層7で封止する工程とを有する半導体装置の製造方法。
【選択図】図7
Description
そして、図11を参照して、露出した導体ポスト3に、半田バンプなどの外部電極端子12を接合する。図中には、一つの半導体チップのみ描かれているが、実際には、複数の半導体チップが搭載されている。そのため、最後に、ダイシング等の方法により個片化することにより、微細な配線体に高密度に接続された構造が完成する。
2 シード層
3 導体ポスト
4 絶縁樹脂膜
5 配線パターン
6 導体ポスト
7 熱可塑性樹脂
8 配線体
9 半導体チップ
10 半導体チップの電極
11 封止樹脂
12 半田バンプ
Claims (15)
- 支持基板上に金属膜を形成する工程と、
前記金属膜上に、第1パッド及び第1絶縁層を含む第1配線層を形成する工程と、
前記第1配線層上に、前記第1パッドに電気的に接続する第2パッドを形成する工程と、
前記第2パッドを覆うように熱可塑性樹脂からなる第2絶縁層を形成する工程と、
前記第2絶縁層を加熱し軟化させた状態で、第1半導体チップと前記第2パッドと電気的に接続し、同時に、前記第1半導体チップと前記第1配線層との間の間隙を第2絶縁層で封止する工程と、
を有すること、
を特徴とする半導体装置の製造方法。 - 前記第2絶縁層上に、前記第1半導体チップを封止する封止樹脂を形成する工程をさらに有すること、
を特徴とする請求項1に記載の半導体装置の製造方法。 - 前記シリコン基板を前記金属膜から剥離する工程をさらに有すること、
を特徴とする請求項2に記載の半導体装置の製造方法。 - 前記封止樹脂を形成する工程の後、前記シリコン基板を前記金属膜から剥離すること、
を特徴とする請求項3に記載の半導体装置の製造方法。 - 前記金属膜を除去し、前記第1パッドを前記第1絶縁層から露出させる工程をさらに有すること、
を特徴とする請求項3若しくは請求項4に記載の半導体装置の製造方法。 - 前記第1絶縁層が熱可塑性樹脂からなること、
を特徴とする請求項5に記載の半導体装置の製造方法。 - 前記第1絶縁膜を加熱し軟化させた状態で、前記第1絶縁層の裏面において前記第1パッドと第2半導体チップとを電気的に接続し、同時に、前記第2半導体チップと前記第2絶縁層との間の間隙を前記第1絶縁層で封止すること、
を特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第1絶縁層の裏面に露出した前記第1パッドに外部電極端子を接続すること、
を特徴とする請求項5に記載の半導体装置の製造方法。 - 前記第1パッドが複数形成され、
前記第1パッドの一部に前記第2半導体チップが接続され、他の第1パッドに外部電極端子が接続されること、
を特徴とする請求項7に記載の半導体装置の製造方法。 - 前記第1絶縁層上に、前記第1パッドと前記第2パッドとを電気的に接続する配線を形成する工程をさらに有すること、
を特徴とする請求項1ないし請求項9に記載の半導体装置の製造方法。 - 前記第1絶縁層の少なくとも一部を除去し、前記第1パッドの表面を露出する工程をさらに有すること、
を特徴とする請求項1ないし請求項10に記載の半導体装置の製造方法。 - 前記第2絶縁層の少なくとも一部を除去し、前記第2パッドの表面を露出する工程をさらに有すること、
を特徴とする請求項1ないし請求項11に記載の半導体装置の製造方法。 - 前記第1配線層を形成する工程が、
前記金属膜上に前記第1パッドを形成する工程と、
前記金属膜上に前記第1パッドを覆うように前記第1絶縁膜を形成する工程と、
を有することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1絶縁膜の少なくとも一部を除去して、前記第1パッドを前記第1絶縁膜から露出させる工程をさらに有することを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記第1配線層を形成する工程が、
前記金属膜上に前記第1絶縁膜を形成する工程と、
前記第1絶縁膜の部分的に除去してスルーホールを形成し、当該スルーホールの底に前記第金属膜を露出する工程と、
前記スルーホールの底に露出した前記金属膜上に前記第1パッドを形成する工程と、
を有することを特徴とする請求項1に記載の半導体装置の製造方法。
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JP2005303395A JP5065586B2 (ja) | 2005-10-18 | 2005-10-18 | 半導体装置の製造方法 |
US11/580,869 US7598117B2 (en) | 2005-10-18 | 2006-10-16 | Method for manufacturing semiconductor module using interconnection structure |
CNB2006101356451A CN100530581C (zh) | 2005-10-18 | 2006-10-18 | 一种利用互连结构制造半导体模块的方法 |
CNA2009101182631A CN101504937A (zh) | 2005-10-18 | 2006-10-18 | 半导体模块 |
US12/505,011 US20090273092A1 (en) | 2005-10-18 | 2009-07-17 | Semiconductor module having an interconnection structure |
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JP2015170809A (ja) * | 2014-03-10 | 2015-09-28 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
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2006
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JP2000022040A (ja) * | 1998-07-07 | 2000-01-21 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002110717A (ja) * | 2000-10-02 | 2002-04-12 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2003332508A (ja) * | 2002-05-16 | 2003-11-21 | Renesas Technology Corp | 半導体装置及びその製造方法 |
Cited By (2)
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JP2013526066A (ja) * | 2010-04-29 | 2013-06-20 | 日本テキサス・インスツルメンツ株式会社 | 低減されたダイ歪みアッセンブリのためのパッケージ基板のためのcte補償 |
JP2015170809A (ja) * | 2014-03-10 | 2015-09-28 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
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CN100530581C (zh) | 2009-08-19 |
JP5065586B2 (ja) | 2012-11-07 |
US7598117B2 (en) | 2009-10-06 |
US20090273092A1 (en) | 2009-11-05 |
US20070086166A1 (en) | 2007-04-19 |
CN1953152A (zh) | 2007-04-25 |
CN101504937A (zh) | 2009-08-12 |
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