JP5065586B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5065586B2 JP5065586B2 JP2005303395A JP2005303395A JP5065586B2 JP 5065586 B2 JP5065586 B2 JP 5065586B2 JP 2005303395 A JP2005303395 A JP 2005303395A JP 2005303395 A JP2005303395 A JP 2005303395A JP 5065586 B2 JP5065586 B2 JP 5065586B2
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- forming
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- insulating layer
- semiconductor device
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
そして、図11を参照して、露出した導体ポスト3に、半田バンプなどの外部電極端子12を接合する。図中には、一つの半導体チップのみ描かれているが、実際には、複数の半導体チップが搭載されている。そのため、最後に、ダイシング等の方法により個片化することにより、微細な配線体に高密度に接続された構造が完成する。
2 シード層
3 導体ポスト
4 絶縁樹脂膜
5 配線パターン
6 導体ポスト
7 熱可塑性樹脂
8 配線体
9 半導体チップ
10 半導体チップの電極
11 封止樹脂
12 半田バンプ
Claims (8)
- 支持基板上に金属膜を形成する工程と、
前記金属膜上に、第1パッド及び第1絶縁層を含む第1配線層を形成する工程と、
前記第1配線層上に、前記第1パッドに電気的に接続する導体ポストを形成する工程と、
前記導体ポストを覆うように熱可塑性樹脂からなる第2絶縁層を形成する工程と、
前記第2絶縁層の一部を除去し、前記導体ポストの上部を露出させる工程と、
前記第2絶縁層を加熱し軟化させた状態で、第1半導体チップの電極と前記導体ポストとを電気的に接続し、同時に、前記第1半導体チップと前記第1配線層との間の間隙を第2絶縁層で封止する工程と、
前記第2絶縁層上に、前記第1半導体チップを封止する封止樹脂を形成する工程と、
前記支持基板を研削、化学的機械的研磨(CMP)またはエッチングにより除去する工程と、
前記金属膜を除去し、前記第1パッドを前記第1絶縁層から露出させる工程と、
を有し、
前記第1絶縁層が熱可塑性樹脂からなり、
前記第1絶縁膜を加熱し軟化させた状態で、前記第1絶縁層の裏面において前記第1パッドと第2半導体チップとを電気的に接続し、同時に、前記第2半導体チップと前記第2絶縁層との間の間隙を前記第1絶縁層で封止すること、
を特徴とする半導体装置の製造方法。 - 前記封止樹脂を形成する工程の後、前記支持基板を除去すること、
を特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1パッドが複数形成され、
前記第1パッドの一部に前記第2半導体チップが接続され、他の第1パッドに外部電極端子が接続されること、
を特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記第1絶縁層上に、前記第1パッドと前記導体ポストとを電気的に接続する配線を形成する工程をさらに有すること、
を特徴とする請求項1ないし3の何れか一項に記載の半導体装置の製造方法。 - 前記第1絶縁層の少なくとも一部を除去し、前記第1パッドの表面を露出する工程をさらに有すること、
を特徴とする請求項1ないし4の何れか一項に記載の半導体装置の製造方法。 - 前記第1配線層を形成する工程が、
前記金属膜上に前記第1パッドを形成する工程と、
前記金属膜上に前記第1パッドを覆うように前記第1絶縁膜を形成する工程と、
を有することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1絶縁膜の少なくとも一部を除去して、前記第1パッドを前記第1絶縁膜から露出させる工程をさらに有することを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記第1配線層を形成する工程が、
前記金属膜上に前記第1絶縁膜を形成する工程と、
前記第1絶縁膜を部分的に除去してスルーホールを形成し、当該スルーホールの底に前記金属膜を露出する工程と、
前記スルーホールの底に露出した前記金属膜上に前記第1パッドを形成する工程と、
を有することを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (5)
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JP2005303395A JP5065586B2 (ja) | 2005-10-18 | 2005-10-18 | 半導体装置の製造方法 |
US11/580,869 US7598117B2 (en) | 2005-10-18 | 2006-10-16 | Method for manufacturing semiconductor module using interconnection structure |
CNB2006101356451A CN100530581C (zh) | 2005-10-18 | 2006-10-18 | 一种利用互连结构制造半导体模块的方法 |
CNA2009101182631A CN101504937A (zh) | 2005-10-18 | 2006-10-18 | 半导体模块 |
US12/505,011 US20090273092A1 (en) | 2005-10-18 | 2009-07-17 | Semiconductor module having an interconnection structure |
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JP2005303395A JP5065586B2 (ja) | 2005-10-18 | 2005-10-18 | 半導体装置の製造方法 |
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JP5065586B2 true JP5065586B2 (ja) | 2012-11-07 |
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JP (1) | JP5065586B2 (ja) |
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JP4752825B2 (ja) * | 2007-08-24 | 2011-08-17 | カシオ計算機株式会社 | 半導体装置の製造方法 |
US8343809B2 (en) | 2010-03-15 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die |
US8456002B2 (en) | 2007-12-14 | 2013-06-04 | Stats Chippac Ltd. | Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief |
US8183095B2 (en) | 2010-03-12 | 2012-05-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation |
US7767496B2 (en) | 2007-12-14 | 2010-08-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer |
US9318441B2 (en) | 2007-12-14 | 2016-04-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die |
JP5147678B2 (ja) * | 2008-12-24 | 2013-02-20 | 新光電気工業株式会社 | 微細配線パッケージの製造方法 |
US9548240B2 (en) | 2010-03-15 | 2017-01-17 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package |
US8338231B2 (en) * | 2010-03-29 | 2012-12-25 | Infineon Technologies Ag | Encapsulated semiconductor chip with external contact pads and manufacturing method thereof |
US8298863B2 (en) * | 2010-04-29 | 2012-10-30 | Texas Instruments Incorporated | TCE compensation for package substrates for reduced die warpage assembly |
CN101819951B (zh) * | 2010-05-07 | 2012-01-25 | 日月光半导体制造股份有限公司 | 基板及应用其的半导体封装件与其制造方法 |
JP2012069734A (ja) * | 2010-09-24 | 2012-04-05 | Toshiba Corp | 半導体装置の製造方法 |
TWI453872B (zh) * | 2011-06-23 | 2014-09-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9023690B2 (en) * | 2012-11-19 | 2015-05-05 | United Test And Assembly Center | Leadframe area array packaging technology |
US10128175B2 (en) * | 2013-01-29 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company | Packaging methods and packaged semiconductor devices |
JP6336298B2 (ja) * | 2014-03-10 | 2018-06-06 | ローム株式会社 | 半導体装置 |
TWI616979B (zh) * | 2014-03-14 | 2018-03-01 | Toshiba Memory Corp | 半導體裝置及其製造方法 |
JP6259737B2 (ja) * | 2014-03-14 | 2018-01-10 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
US9257414B2 (en) | 2014-04-10 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor structure and method |
US20170338128A1 (en) * | 2016-05-17 | 2017-11-23 | Powertech Technology Inc. | Manufacturing method of package structure |
CN110268511A (zh) * | 2016-12-22 | 2019-09-20 | 深圳中科四合科技有限公司 | 一种三极管的封装方法及三极管 |
CN111627867A (zh) * | 2019-02-28 | 2020-09-04 | 富泰华工业(深圳)有限公司 | 芯片封装结构及其制作方法 |
CN110366308A (zh) * | 2019-08-02 | 2019-10-22 | 昆山丘钛微电子科技有限公司 | 线路板制造方法及线路板 |
CN110854111A (zh) * | 2019-11-25 | 2020-02-28 | 维沃移动通信有限公司 | 封装组件、电子设备及封装方法 |
CN110854086A (zh) * | 2019-11-25 | 2020-02-28 | 维沃移动通信有限公司 | 封装组件、电子设备及封装方法 |
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KR100192179B1 (ko) * | 1996-03-06 | 1999-06-15 | 김영환 | 반도체 패키지 |
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JP2000022040A (ja) * | 1998-07-07 | 2000-01-21 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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JP2001345418A (ja) | 2000-06-02 | 2001-12-14 | Matsushita Electric Ind Co Ltd | 両面実装構造体の製造方法及びその両面実装構造体 |
TW507352B (en) * | 2000-07-12 | 2002-10-21 | Hitachi Maxell | Semiconductor module and producing method therefor |
JP2002110717A (ja) * | 2000-10-02 | 2002-04-12 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
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EP1489657A4 (en) * | 2002-02-06 | 2011-06-29 | Ibiden Co Ltd | SEMICONDUCTOR CHIP MOUNTING PLATE, METHOD FOR THE PRODUCTION THEREOF AND SEMICONDUCTOR MODULE |
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JP2003332508A (ja) * | 2002-05-16 | 2003-11-21 | Renesas Technology Corp | 半導体装置及びその製造方法 |
TWI221664B (en) * | 2002-11-07 | 2004-10-01 | Via Tech Inc | Structure of chip package and process thereof |
JP2004193497A (ja) * | 2002-12-13 | 2004-07-08 | Nec Electronics Corp | チップサイズパッケージおよびその製造方法 |
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- 2005-10-18 JP JP2005303395A patent/JP5065586B2/ja not_active Expired - Fee Related
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2006
- 2006-10-16 US US11/580,869 patent/US7598117B2/en not_active Expired - Fee Related
- 2006-10-18 CN CNB2006101356451A patent/CN100530581C/zh not_active Expired - Fee Related
- 2006-10-18 CN CNA2009101182631A patent/CN101504937A/zh active Pending
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US20070086166A1 (en) | 2007-04-19 |
CN101504937A (zh) | 2009-08-12 |
US7598117B2 (en) | 2009-10-06 |
JP2007115774A (ja) | 2007-05-10 |
CN1953152A (zh) | 2007-04-25 |
CN100530581C (zh) | 2009-08-19 |
US20090273092A1 (en) | 2009-11-05 |
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