CN1953152A - 一种利用互连结构制造半导体模块的方法 - Google Patents

一种利用互连结构制造半导体模块的方法 Download PDF

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Publication number
CN1953152A
CN1953152A CNA2006101356451A CN200610135645A CN1953152A CN 1953152 A CN1953152 A CN 1953152A CN A2006101356451 A CNA2006101356451 A CN A2006101356451A CN 200610135645 A CN200610135645 A CN 200610135645A CN 1953152 A CN1953152 A CN 1953152A
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Prior art keywords
conductive pole
insulating barrier
conductive
semiconductor device
interconnection structure
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CN100530581C (zh
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栗田洋一郎
副岛康志
川野连也
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Renesas Electronics Corp
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NEC Corp
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Abstract

本发明涉及一种用于制造半导体模块的方法。在该方法中，在支撑基片上形成金属层，然后在所述金属层上形成第一导电柱和第一绝缘层。所述第一绝缘层围绕所述第一导电柱的侧面。然后，在所述第一导电柱上形成第二导电柱。所述第二导电柱与所述第一导电柱电连接。然后，形成第二绝缘层以覆盖所述第二导电柱。所述第二绝缘层由粘性树脂形成。最后，通过所述第二绝缘层将半导体装置粘接到所述第二导电柱，同时通过所述第二绝缘层密封所述第一半导体装置和所述第一绝缘层之间的间隙。

Description

一种利用互连结构制造半导体模块的方法
技术领域
本发明涉及一种用于制造半导体模块的方法。
背景技术
在用于制造半导体模块的现有技术的方法中，将带有电极的半导体芯片按压(face down)并且粘接到带有外部端子的印刷电路板上。然后，使用密封树脂以将半导体芯片和印刷电路板之间的间隙密封起来(参见JP2001-345418A)。
发明内容
但是，在上述现有技术的方法中，由于半导体芯片和印刷电路板之间的热膨胀系数存在很大的不同，因此半导体芯片的电极相对于印刷电路板的外部端子的定位的精确性会恶化。结果，将半导体芯片的电极相对于印刷电路板的外部电极的连接的精确性会恶化，以至于使半导体模块的质量也恶化。
根据本发明，在用于制造半导体模块的方法中，在支撑基片上形成金属层，然后在所述金属层上形成第一导电柱和第一绝缘层。所述第一绝缘层围绕所述第一导电柱的侧面。然后，在所述第一导电柱上形成第二导电柱。所述第二导电柱与所述第一导电柱电连接。然后，形成第二绝缘层以覆盖所述第二导电柱。所述第二绝缘层由粘性树脂制成。最后，通过所述第二绝缘层将半导体装置连接到所述第二导电柱上，同时通过所述第二绝缘层密封所述第一半导体装置和所述第一绝缘层之间的间隙。
由于该支撑基片和该半导体装置之间的热膨胀系数基本上没有差异，所以将会提高半导体装置的电极相对于支撑基片的外部电极的定位的精确性。
值得注意的是，在将半导体模块安装在印刷电路板等上之前，先除去支撑基片和金属层。在这种情况下，通过连接结构将半导体装置的电极之间的间隔扩展为互连结构的外部电极之间的间隔，其中所述连接结构包括第一导电柱、第一绝缘层、第二导电柱以及第二绝缘层。因此，能够容易地将半导体模块安装到印刷电路板等上。
附图说明
结合以下附图，从以下描述中可以更加清楚地理解本发明，其中：
图1A到1L是截面图，用于解释根据本发明的制造半导体模块的方法的第一实施例；
图2A到2P是截面图，用于解释根据本发明的制造半导体模块的方法的第二实施例；
图3A、3B和3C是截面图，用于解释根据本发明的制造半导体模块的方法的第三实施例；
图4A、4B和4C是截面图，用于解释根据本发明的制造半导体模块的方法的第四实施例；
图5A、5B和5C是截面图，用于解释根据本发明的制造半导体模块的方法的第五实施例；
图6A、6B和6C是截面图，用于解释根据本发明的制造半导体模块的方法的第六实施例。
具体实施方式
现在参考图1A到1L解释根据本发明的用于制造半导体模块的方法的第一实施例。
首先，参考图1A，制备例如硅晶片的支撑基片1。然后，通过溅射工艺等在整个表面上淀积由Cu或Ni制成的籽晶金属层2作为电镀中间层。然后，使用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺在籽晶金属层2上形成由Cu或Ni所制成的导电柱(焊盘)3。值得注意的是，如果导电柱3由Cu制成，则在形成导电柱3之前，利用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺也可以形成由Ni制成的薄的铜扩散阻挡层(未示出)。
接下来，参考图1B，通过旋转涂覆工艺在整个表面上涂覆由聚酰亚胺树脂或者环氧树脂制成的绝缘树脂层4，然后，进行烧结。值得注意的是，可以通过在整个表面上粘接由聚酰亚胺树脂或者环氧树脂制成的绝缘树脂薄膜，从而形成绝缘树脂层4。
接下来，参考图1C，通过化学机械抛光(CMP)工艺、研磨工艺或者切削工艺来使绝缘树脂层4平坦化，以便暴露出导电柱3的上表面。
接下来，参考图1D，利用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺来形成导电图案层5，所述导电图案层由Cu或Ni制成且用做互连。导电图案层5与导电柱3电连接。
接下来，参考图1E，使用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺形成由Cu或Ni制成的导电柱(焊盘)6。导电柱6与导电图案层5电连接。
接下来，参考图1F，在整个表面上涂覆由热塑性聚酰亚胺制成的热塑性树脂层7用作粘接层，以覆盖导电图案层5和导电柱6。
接下来，参考图1G，通过CMP工艺、研磨工艺或切削工艺从而使热塑性树脂层7变得平坦化，从而暴露出导电柱6的上表面。值得注意的是，如果导电柱6由Cu制成，则使用籽晶金属层2作为阴极电极，通过电镀工艺也可以在导电柱6的表面上形成由Au所制成的铜氧化阻挡层(未示出)。
因此，通过导电柱3、绝缘树脂层4、导电图案层5、导电柱6以及热塑性树脂层7形成了互连结构CS1。
接下来，参考图1H，带有电极9的由硅制成的半导体芯片8被按压到互连结构CS1上，在该电极9上施加有焊球、电镀球或者柱状凸起，由此半导体芯片8的多个电极9对应于互连结构CS1中相应的多个导电柱6。在这种情况下，加热支撑基片1和/或半导体芯片8从而熔化热塑性树脂层7。结果，能够同时进行半导体芯片1的电极9与导电柱6的电连接、半导体芯片8和互连结构CS1的粘接以及密封半导体芯片8和绝缘树脂层4之间的间隙，这减少了制造步骤的数目。
在图1H中，由于互连结构CS1被粘接到支撑基片1上，所以互连结构CS1随着支撑基片1的热膨胀和收缩而一起热膨胀和收缩。在这种情况下，由于支撑基片1和半导体芯片8基本上由同样的材料例如硅制成，从而它们之间的热膨胀系数基本上没有差异，因此随着支撑基片1的热膨胀和收缩，半导体芯片8也会一起热膨胀和收缩。
而且，即使仅仅加热支撑基片1和半导体芯片8中的一个或者将它们加热到不同的温度，当通过XY工作台(XY stage)和吸入压头使它们之间相互施压时也能够整体地加热支撑基片1和半导体芯片8，从而支撑基片1和半导体芯片8之间的温度基本没有差异。例如，支撑基片1与互连结构CS1一起被安装到XY工作台上，半导体芯片8被安装在吸入压头上。然后，吸入压头被压向XY工作台，从而使支撑基片1和半导体芯片8相互施压。然后，通过集成到XY工作台的加热器将支撑基片1加热到大约100℃，同时通过集成到吸入压头中的加热器将半导体芯片8加热到大约300℃。因此，即使导电柱6的宽度变窄以及各导电柱6之间的间隔(间距)变小，导电柱6也能够恰当地与半导体芯片8的电极9相对应。
接下来，参考图1I，通过注塑工艺、印刷工艺或者灌封工艺使用密封树脂层10对互连结构CS1进行密封。在这种情况下，如图1I所示，尽管半导体芯片8的后表面被密封树脂层10所密封，但是这个后表面可以被暴露于空气中。
接下来，参考图1J，通过CMP工艺、研磨工艺、切削工艺、湿蚀刻工艺、干蚀刻工艺或者这些工艺的某些组合，从籽晶金属层2上除去支撑基片1。例如，如果在支撑基片1上进行干蚀刻工艺作为最后一道工艺，则支撑基片1和籽晶金属层2的蚀刻比非常大，以至于能够确实地保留籽晶金属层2。结果，利用籽晶金属层2确实地覆盖了导电柱3以及导电柱3和绝缘树脂层4之间的边缘部分，因此防止了导电柱3被损坏以及防止了在导电柱3和绝缘树脂层4之间的边缘部分断裂。
接下来，参考图1K，通过蚀刻工艺从互连结构CS1上除去籽晶金属层2，以便暴露出导电柱3。
最后，参考图1L，将外部电极11例如焊球、电镀球或者柱状凸起连接到导电柱3。
值得注意的是，尽管图1A到1L示出了单个半导体模块，但是实际上制造了多个半导体模块。因此，在图1L所示的工艺之后，通过切割工艺将多个半导体模块相互分开。
接下来，参考图2A到1P解释根据本发明的制造半导体模块的方法的第二实施例。
首先，参考图2A，以与图1A类似的方式，制备支撑基片1例如硅晶片。然后，通过溅射工艺等在整个表面上淀积由Cu或Ni制成的籽晶金属层2作为电镀中间层。然后，使用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺在籽晶金属层2上形成由Cu或Ni制成的导电柱(焊盘)31。
接下来，参考图2B，以与图1B类似的方式，通过旋转涂覆工艺在整个表面上涂覆由聚酰亚胺树脂或者环氧树脂制成的绝缘树脂层41，然后，进行烧结。
接下来，参考图2C，以与图1C类似的方式，通过CMP工艺、研磨工艺或者切削工艺使绝缘树脂层41平坦化，从而暴露出导电柱31的上表面。
接下来，参考图2D，以与图1D类似的方式，使用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺形成导电图案层51，该导电图案层用作互连且由Cu或Ni制成。导电图案层51与导电柱31电连接。
接下来，参考图2E，使用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺在导电图案层51上形成由Cu或Ni制成的导电柱32。导电柱32与导电图案层51电连接。
接下来，参考图2F，通过旋转涂覆工艺在整个表面上涂覆由聚酰亚胺树脂或环氧树脂制成的绝缘树脂层42，然后进行烧结。
接下来，参考图2G，通过CMP工艺、研磨工艺或切削工艺使绝缘树脂层42平坦化，以暴露出导电柱32的上表面。
接下来，参考2H，使用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺形成导电图案层52，该导电图案层用作互连且由Cu或Ni制成。导电图案层52与导电柱32电连接。
接下来，参考图2I，以与图1E类似的方式，使用籽晶金属层2作为阴极电极，通过光蚀刻工艺和电镀工艺形成由Cu或Ni制成的导电柱(焊盘)6。导电柱6与导电图案层52电连接。
接下来，参考图2J，以与图1F类似的方式，在整个表面上涂覆由热塑性聚酰亚胺制成的热塑性树脂层7用作粘接层，用以覆盖导电图案层52和导电柱6。
接下来，参考图2K，以与图1G类似的方式，通过CMP工艺、研磨工艺或切削工艺使热塑性树脂层7平坦化，从而暴露出导电柱6的上表面。
因此，通过导电柱31、绝缘树脂层41、导电图案层51、导电柱32、绝缘树脂层42、导电图案层52、导电柱6以及热塑性树脂层7形成了互连结构CS2。
接下来，参考图2L，以与图1H类似的方式，带有电极9的由硅制成的半导体芯片8被按压到互连结构CS2上，在该电极9上施加有焊球、电镀球或者柱状凸起，从而半导体芯片8的多个电极9对应于互连结构CS2中相应的多个导电柱6。在这种情况下，加热支撑基片1和/或半导体芯片8从而熔化热塑性树脂层7。结果，能够同时进行半导体芯片1的电极9与导电柱6的电连接、半导体芯片8和互连结构CS2的粘接、以及密封半导体芯片8和绝缘树脂层42之间的间隙，这减少了制造步骤的数目。
甚至在图2L中，以与图1H类似的方式，由于互连结构CS2粘接到支撑基片1上，所以互连结构CS2随着支撑基片1的热膨胀和收缩而一起热膨胀和收缩。在这种情况下，由于支撑基片1和半导体芯片8基本上由同样的材料例如硅制成，从而它们之间的热膨胀系数基本没有差异，因此随着支撑基片1的热膨胀和收缩，半导体芯片8也会一起热膨胀和收缩。因此，即使导电柱6的宽度变窄并且在各导电柱6之间的间隔(间距)变小，导电柱6也能够恰当地与半导体芯片8的电极9相对应。
接下来，参考图2M，以与图1I类似的方式，通过注塑工艺、印刷工艺或者灌封工艺借助密封树脂层10对互连结构CS2进行密封。
接下来，参考图2N，以与图1J类似的方式，通过CMP工艺、研磨工艺、切削工艺、湿蚀刻工艺、干蚀刻工艺或者这些工艺的某些组合从籽晶金属层2上除去支撑基片1。结果，能够确实地利用籽晶金属层2覆盖导电柱31(32)以及位于导电柱31(32)和绝缘树脂层41(42)之间的边缘部分，因此防止了导电柱31(32)被损坏以及防止了导电柱31(32)和绝缘树脂层41(42)之间的边缘部分断裂。
接下来，参考图2O，以与图1K类似的方式，通过蚀刻工艺从互连结构CS2上除去籽晶金属层2，从而暴露出导电柱31。
最后，参考图2P，以与图1L类似的方式，将外部电极11例如焊球、电镀球或者柱状凸起连接到导电柱31。
值得注意的是，尽管图2A到2P示出了单个半导体模块，但是实际上制造了多个半导体模块。因此，在图2P所示的工艺之后，通过切割工艺将多个半导体模块相互分开。
接下来，参考图3A、3B和3C解释根据本发明的制造半导体模块的方法的第三实施例。
首先，参考图3A，除了形成热塑性树脂层7’来代替互连结构CS1中的绝缘树脂层4之外，通过图1A到1K所示的工艺获得了与带有电极9的半导体芯片8相粘接的互连结构CS1。
因此，通过导电柱3、热塑性树脂层7’、导电图案层5、导电柱6以及热塑性树脂层7来形成互连结构CS1。
接下来，参考图3B，带有电极13的、由硅制成的半导体芯片12被按压到互连结构CS1，在该电极13上施加有焊球、电镀球或者柱状凸起，由此半导体芯片12的多个电极13对应于互连结构CS1中相应的多个导电柱3。在这种情况下，加热半导体芯片8(互连结构CS1)和/或半导体芯片12从而熔化热塑性树脂层7’。因此，能够同时进行半导体芯片12的电极13与导电柱3的电连接、半导体芯片12和互连结构CS1的粘接以及密封半导体芯片12和热塑性树脂层7’之间的间隙，这减少了制造步骤的数目。
在图3B中，由于互连结构CS1粘接到半导体芯片12上，所以互连结构CS1随着半导体芯片8的热膨胀和收缩而一起热膨胀和收缩。在这种情况下，由于半导体芯片8和半导体芯片12基本上由同样的材料例如硅制成，因此它们之间的热膨胀系数基本没有差异，所以随着半导体芯片8的热膨胀和收缩，半导体芯片12也会一起热膨胀和收缩。
而且，即使仅仅加热半导体芯片8和半导体芯片12中的一个或者将它们加热到不同的温度，当通过挤压部件(未示出)使半导体芯片8和半导体芯片12之间相互施压时，也能够整体地对它们进行加热，从而在半导体芯片8和半导体芯片12之间基本上没有温度差异。例如，半导体芯片8和半导体芯片12被加热到大约300℃。因此，即使导电柱3的宽度变窄并且在各导电柱3之间的间隔(间距)变小，导电柱3也能够恰当地与半导体芯片12的电极13相对应。
而且，在图3B中，当半导体芯片8和/或半导体芯片12被加热时，可能会重新熔化热塑性树脂层7；但是，在这种情况下，半导体芯片8通过XY工作台和吸入压头被压向半导体芯片12，不会出现问题。实际上，在这种情况下，半导体芯片8以及互连结构CS1一同被安装在XY工作台上，以及半导体芯片12被安装在吸入压头上。然后，吸入压头被压向XY工作台，由此半导体芯片8和半导体芯片12相互挤压。然后，通过集成到吸入压头中的加热器仅仅加热半导体芯片12，因此完全防止了热塑性树脂层7被重新熔化。
最后，参考图3C，将外部电极11例如焊球、电镀球或者柱状凸起连接到导电柱3。
值得注意的是，尽管图3A到3C示出了单个半导体模块，但是实际上制造了多个半导体模块。因此，在图3C所示的工艺之后，通过切割工艺将多个半导体模块相互分开。
接下来，参考图4A、4B和4C解释根据本发明的制造半导体模块的方法的第四实施例。
首先，参考图4A，除了形成热塑性树脂层7’来代替互连结构CS2中的绝缘树脂层4之外，通过图2A到2N所示的工艺获得与连带有电极9的半导体芯片8相粘接的互连结构CS2。
因此，通过导电柱31、热塑性树脂层7’、导电图案层51、导电柱32、绝缘树脂层42、导电图案层52、导电柱6以及热塑性树脂层7形成了互连结构CS2。
接下来，参考图4B，连带有电极13的、由硅制成的半导体芯片12被按压到互连结构CS2上，在该电极13上施加有焊球、电镀球或者柱状凸起，从而半导体芯片12的多个电极13对应于互连结构CS2中相应的多个导电柱31。在这种情况下，加热半导体芯片8(互连结构CS2)和/或半导体芯片12从而熔化热塑性树脂层7’。因此，能够同时进行半导体芯片12的电极13与导电柱31的电连接、半导体芯片12和互连结构CS2的粘接、以及密封半导体芯片12和热塑性树脂层7’之间的间隙，这减少了制造步骤的数目。
在图4B中，由于互连结构CS2粘接到半导体芯片12，所以互连结构CS2随着半导体芯片8的热膨胀和收缩而一起热膨胀和收缩。在这种情况下，由于半导体芯片8和半导体芯片12基本上由同样的材料例如硅制成，从而它们之间的热膨胀系数基本上没有差异，因此随着半导体芯片8的热膨胀和收缩，半导体芯片12也会一起热膨胀和收缩。因此，即使导电柱31的宽度变窄并且在导电柱31之间的间隔(间距)变小，导电柱31也能够恰当地与半导体芯片12的电极13相对应。
最后，参考图4C，将外部电极11例如焊球、电镀球或者柱状凸起连接到导电柱31。
值得注意的是，尽管图4A到4C示出了单个半导体模块，但是实际上制造了多个半导体模块。因此，在图4C所示的工艺之后，通过切割工艺将多个半导体模块相互分开。
接下来，参考图5A、5B和5C解释根据本发明的制造半导体模块的方法的第五实施例。
首先，参考图5A，通过图1A到1K所示的工艺获得了与连带有电极9的半导体芯片8相粘接的互连结构CS1。
因此，通过导电柱3、绝缘树脂层4、导电图案层5、导电柱6以及热塑性树脂层7形成了互连结构CS1。
接下来，参考图5B，通过多个由光敏环氧树脂所制成的光敏绝缘层201、202和203以及导电结构(包括通孔和互连)204和205形成了复合互连结构BCS，其中所述导电结构是由Cu所制成的、并与光敏绝缘层201、202和203相交替地形成。
最后，参考图5C，将外部电极11例如焊球、电镀球或者柱状凸起连接到导电结构205。
值得注意的是，尽管图5A到5C示出了单个半导体模块，但是实际上制造了多个半导体模块。因此，在图5C所示的工艺之后，通过切割工艺将多个半导体模块相互分开。
接下来，参考图6A、6B和6C解释根据本发明的制造半导体模块的方法的第六实施例。
首先，参考图6A，通过图2A到2N所示的工艺获得了与连带有电极9的半导体芯片8相粘接的互连结构CS2。
因此，通过导电柱31、绝缘树脂层41、导电图案层51、导电柱32、绝缘树脂层42、导电图案层52、导电柱6以及热塑性树脂层7形成了互连结构CS2。
接下来，参考图6B，通过多个由光敏环氧树脂制成的光敏绝缘层201、202和203以及导电结构204和205形成了复合互连结构BCS，其中所述导电结构是由Cu制成的、且与光敏绝缘层201、202和203相交替地形成。
最后，参考图6C，将外部电极11例如焊球、电镀球或者柱状凸起连接到导电结构205。
值得注意的是，尽管图6A到6C示出了单个半导体模块，但是实际上制造了多个半导体模块。因此，在图6C所示的工艺之后，通过切割工艺将多个半导体模块相互分开。
在上述第一、第二、第五和第六实施例中，通过在籽晶金属层2上涂覆光敏树脂层以及通过光蚀刻工艺在光敏树脂层中形成通孔，从而可以形成导电柱3和31，因此形成了所述通孔内的导电柱3和31，这减少了制造步骤的数目。
而且，在上述实施例中，能够使用半硬化阶段(B阶段)的热固性树脂层例如环氧树脂来代替热塑性树脂层7。在这种情况下，不进行加热工艺，半导体芯片8就粘接到B级的热固性树脂层上，然后，通过加热工艺使该热固性树脂层完全硬化。
而且，在上述实施例中，按照场合的需要，能够在导电柱和导电图案层中包含用于与树脂良好接触的由Ti制成的树脂接触层。
此外，能够使用另一个半导体装置例如球形栅格阵列(BGA)封装、插针网格阵列(PGA)封装等来代替每个半导体芯片8和12。在这种情况下，支撑基片1由这样的材料制成，其中所述材料具有与这些半导体装置基本相同的热膨胀系数。而且，在半导体模块的每个表面上都能够安装多个半导体装置。
而且，在上述实施例中，半导体芯片8和12能够由除了硅以外的其它材料制成；在这种情况下，支撑基片1也由这些材料制成，以使得它们之间的热膨胀系数基本上没有差异。

Claims (24)

1.一种用于制造半导体模块的方法，包括：
在支撑基片上形成金属层；
在所述金属层上形成多个第一导电柱和第一绝缘层，所述第一绝缘层围绕在所述第一导电柱的侧面；
在所述第一导电柱上形成多个第二导电柱，所述第二导电柱与所述第一导电柱电连接；
形成第二绝缘层以覆盖所述第二导电柱，所述第二绝缘层由粘性树脂形成；
通过所述第二绝缘层将第一半导体装置粘接到所述第二导电柱，同时通过所述第二绝缘层密封所述第一半导体装置和所述第一绝缘层之间的间隙。
2.如权利要求1所述的方法，其中所述粘性树脂是热塑性树脂，并且所述粘接步骤包括：加热所述支撑基片和所述半导体装置中的至少一个。
3.如权利要求1所述的方法，其中所述粘性树脂是热固性树脂，并且所述方法还包括：在通过B阶段的所述热固性树脂将所述第一半导体装置粘接到所述第二导电柱之后，加热所述支撑基片和所述第一半导体装置中的至少一个。
4.如权利要求1所述的方法，其中所述支撑基片具有与所述第一半导体装置基本相同的热膨胀系数。
5.如权利要求1所述的方法，还包括在所述第二绝缘层上形成密封树脂层，以便密封所述第一半导体装置。
6.如权利要求1所述的方法，还包括：在所述第一半导体装置被粘接到所述第二导电柱之后，将所述支撑基片从所述金属层上除去。
7.如权利要求6所述的方法，还包括：在除去所述支撑基片之后，除去所述金属层以暴露出所述第一导电柱。
8.如权利要求5所述的方法，还包括：在形成所述密封树脂层之后，从所述金属层上除去所述支撑基片。
9.如权利要求8所述的方法，还包括：在除去所述支撑基片之后，除去所述金属层以暴露出所述第一导电柱。
10.如权利要求7所述的方法，还包括：将外部电极连接到所述暴露出的第一导电柱上。
11.如权利要求9所述的方法，还包括：将外部电极连接到所述暴露出的第一导电柱上。
12.如权利要求1所述的方法，还包括：第一导电图案层，其位于所述第一和第二导电柱之间并且与所述第一和第二导电柱电连接。
13.如权利要求12所述的方法，还包括：
在所述第一导电图案层上形成第三导电柱，所述第三导电柱与所述第一导电图案电连接；以及
在形成第二导电柱之前，在所述第三导电柱上形成第二导电图案层，所述第二导电图案层与所述第二和第三导电柱电连接。
14.如权利要求7所述的方法，其中所述第一绝缘层由粘性树脂制成，并且所述方法还包括：在除去所述金属层之后，将第二半导体装置粘接到所述第一绝缘层的后表面，同时通过所述第一绝缘层密封所述第二半导体装置与所述第一导电柱之间的间隙。
15.如权利要求9所述的方法，其中所述第一绝缘层由粘性树脂制成，并且所述方法还包括：在除去所述金属层之后，将第二半导体装置粘接到所述第一绝缘层的后表面，同时通过所述第一绝缘层密封所述第二半导体装置与所述第一导电柱之间的间隙。
16.如权利要求14所述的方法，其中所述粘性树脂是热塑性树脂，并且所述粘接步骤包括：加热所述第一和第二半导体装置中的至少一个。
17.如权利要求15所述的方法，其中所述粘性树脂是热塑性树脂，并且所述粘接步骤包括：加热所述第一和第二半导体装置中的至少一个。
18.如权利要求7所述的方法，还包括：
在所述暴露出的第一导电柱上形成复合互连结构；以及
将外部电极粘接到所述复合互连结构。
19.一种半导体模块，包括：
互连结构，其包括分别在所述互连结构的前和后表面上相互电连接的第一和第二导电柱，并且第一和第二绝缘层分别围绕所述第一和第二导电柱的侧面，所述第二绝缘层由粘性树脂制成；
第一半导体装置，其通过所述第二绝缘层粘接到所述第二导电柱，从而通过所述第二绝缘层密封所述第一半导体装置和所述互连结构之间的间隙。
20.如权利要求19所述的半导体模块，还包括：
在所述互连结构的后表面上所形成的金属层；以及
在所述金属层上所形成的支撑基片。
21.如权利要求19所述的半导体模块，还包括：位于所述第一导电柱的至少一部分上的外部电极。
22.如权利要求19所述的半导体模块，其中所述第一绝缘层由粘性树脂制成，并且所述半导体模块还包括：第二半导体装置，该第二半导体装置通过所述第一绝缘层粘接到所述第一导电柱的一部分上，从而通过所述第一绝缘层密封所述第二半导体装置和所述互连结构之间的间隙。
23.如权利要求19所述的半导体模块，还包括：位于所述第一导电柱和所述第一绝缘层上的复合互连结构。
24.如权利要求23所述的半导体模块，还包括位于所述复合互连结构上的外部电极。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916624A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置及其制造方法
CN110366308A (zh) * 2019-08-02 2019-10-22 昆山丘钛微电子科技有限公司 线路板制造方法及线路板
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4752825B2 (ja) * 2007-08-24 2011-08-17 カシオ計算機株式会社 半導体装置の製造方法
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8343809B2 (en) 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
JP5147678B2 (ja) * 2008-12-24 2013-02-20 新光電気工業株式会社 微細配線パッケージの製造方法
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US8338231B2 (en) * 2010-03-29 2012-12-25 Infineon Technologies Ag Encapsulated semiconductor chip with external contact pads and manufacturing method thereof
US8298863B2 (en) * 2010-04-29 2012-10-30 Texas Instruments Incorporated TCE compensation for package substrates for reduced die warpage assembly
CN101819951B (zh) * 2010-05-07 2012-01-25 日月光半导体制造股份有限公司 基板及应用其的半导体封装件与其制造方法
JP2012069734A (ja) * 2010-09-24 2012-04-05 Toshiba Corp 半導体装置の製造方法
TWI453872B (zh) * 2011-06-23 2014-09-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9023690B2 (en) * 2012-11-19 2015-05-05 United Test And Assembly Center Leadframe area array packaging technology
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
JP6336298B2 (ja) * 2014-03-10 2018-06-06 ローム株式会社 半導体装置
JP6259737B2 (ja) * 2014-03-14 2018-01-10 東芝メモリ株式会社 半導体装置及びその製造方法
US9257414B2 (en) * 2014-04-10 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor structure and method
US20170338128A1 (en) * 2016-05-17 2017-11-23 Powertech Technology Inc. Manufacturing method of package structure
CN110268510B (zh) * 2016-12-22 2021-11-23 厦门四合微电子有限公司 一种分立器件的封装方法及分立器件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100192179B1 (ko) * 1996-03-06 1999-06-15 김영환 반도체 패키지
US5677567A (en) * 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly
JP2000022040A (ja) * 1998-07-07 2000-01-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3502776B2 (ja) * 1998-11-26 2004-03-02 新光電気工業株式会社 バンプ付き金属箔及び回路基板及びこれを用いた半導体装置
JP2001345418A (ja) 2000-06-02 2001-12-14 Matsushita Electric Ind Co Ltd 両面実装構造体の製造方法及びその両面実装構造体
TW507352B (en) * 2000-07-12 2002-10-21 Hitachi Maxell Semiconductor module and producing method therefor
JP2002110717A (ja) * 2000-10-02 2002-04-12 Sanyo Electric Co Ltd 回路装置の製造方法
EP1207555A1 (en) 2000-11-16 2002-05-22 Texas Instruments Incorporated Flip-chip on film assembly for ball grid array packages
US6797537B2 (en) * 2001-10-30 2004-09-28 Irvine Sensors Corporation Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers
WO2003067656A1 (fr) * 2002-02-06 2003-08-14 Ibiden Co., Ltd. Carte de montage pour puce a semiconducteur, realisation correspondante, et module a semiconducteur
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
JP2003332508A (ja) * 2002-05-16 2003-11-21 Renesas Technology Corp 半導体装置及びその製造方法
TWI221664B (en) * 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004193497A (ja) * 2002-12-13 2004-07-08 Nec Electronics Corp チップサイズパッケージおよびその製造方法
US7154186B2 (en) * 2004-03-18 2006-12-26 Fairchild Semiconductor Corporation Multi-flip chip on lead frame on over molded IC package and method of assembly

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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