JP2011501410A - 頑健な多層配線要素および埋設された超小型電子素子とのアセンブリ - Google Patents
頑健な多層配線要素および埋設された超小型電子素子とのアセンブリ Download PDFInfo
- Publication number
- JP2011501410A JP2011501410A JP2010528888A JP2010528888A JP2011501410A JP 2011501410 A JP2011501410 A JP 2011501410A JP 2010528888 A JP2010528888 A JP 2010528888A JP 2010528888 A JP2010528888 A JP 2010528888A JP 2011501410 A JP2011501410 A JP 2011501410A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- conductive
- layer
- dielectric layer
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004377 microelectronic Methods 0.000 title claims description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 350
- 239000002184 metal Substances 0.000 claims abstract description 350
- 238000000034 method Methods 0.000 claims description 74
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 238000007747 plating Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000010030 laminating Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 238000000608 laser ablation Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 description 27
- 229910000679 solder Inorganic materials 0.000 description 23
- 230000004048 modification Effects 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- 239000007787 solid Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000003475 lamination Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000000712 assembly Effects 0.000 description 8
- 238000000429 assembly Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000011295 pitch Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000001459 lithography Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000005496 eutectics Effects 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000002470 thermal conductor Substances 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 125000003700 epoxy group Chemical group 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 230000002730 additional effect Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0361—Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0382—Continuously deformed conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
本願は、2007年10月10日に「頑健な多層配線要素および埋設された超小型電子素子とのアセンブリ」の表題で出願された米国仮特許出願第60/998,564号の出願日における利益を主張するものであり、その開示内容を引用することによって本明細書の一部をなすものとする。
本願の主題事項は、例えば、超小型電子素子、特に、半導体集積回路のパッケージ化または接続に用いられる多層配線要素およびその製造に関する。
Claims (42)
- 相互接続要素であって、
上面および前記上面から離れた底面を有している誘電体層と、
前記底面に沿って延在している面を画定している第1の金属層と、
前記上面に沿って延在している第2の金属層であって、前記第1の金属層および前記第2の金属層の少なくとも1つは、複数の導電性トレースを備えている、第2の金属層と、
前記第1の金属層によって画定された前記面から前記誘電体層を通って上方に延在している複数の導電性突起であって、前記導電性突起は、前記第1の金属層の上方の第1の高さに上面を有しており、前記第1の高さは、前記第1の金属層の上方の前記誘電体層の高さの50%よりも大きくなっている、複数の導電性突起と、
前記上面から前記誘電体層の開口を通って延在して前記導電性突起を前記第2の金属層に導電接続している複数の導電性ビアであって、前記導電性ビアの少なくとも1つは、前記導電性突起の前記上面と接触している箇所において第1の幅を有しており、前記第1の幅は、前記上面の幅よりも小さくなっている、導電性ビアと
を備えていることを特徴とする相互接続要素。 - 前記少なくとも1つの導電性突起は、前記上面から下方に延在している壁を有しており、少なくとも1つの導電性ビアは、前記上面においてのみ、前記導電性突起に接触していることを特徴とする請求項1に記載の相互接続要素。
- 相互接続要素であって、
上面および前記上面から離れた底面を有している誘電体層と、
前記底面に沿って延在している平面を画定している第1の金属層と、
前記上面に沿って延在している第2の金属層であって、前記第1の金属層および前記第2の金属層の少なくとも1つは、複数の導電性トレースを備えている、第2の金属層と、
前記第1の金属層によって画定された前記平面から前記誘電体層を通って上方に延在している複数の導電性突起と、
前記誘電体層の開口を通って延在して前記導電性突起を前記第2の金属層に導電接続している複数のメッキ形成された特徴部と
を備えていることを特徴とする相互接続要素。 - 前記第1の金属層および前記第2の金属層の各々は、複数の導電性トレースを備えていることを特徴とする請求項3に記載の相互接続要素。
- 前記導電性突起は、エッチング形成された金属ポストを含んでいることを特徴とする請求項3に記載の相互接続要素。
- 前記導電性突起は、メッキ形成された金属ポストを含んでいることを特徴とする請求項3に記載の相互接続要素。
- 前記導電性突起は、中空導電性突起を含んでいることを特徴とする請求項6に記載の相互接続要素。
- 前記第1の金属層は、前記平面と真っ直ぐに並んだ平面部分および前記平面から離れる方に延在している突出部分を備えており、前記突出部分は、前記導電性突起を画定していることを特徴とする請求項3に記載の相互接続要素。
- 前記導電性突起は、切頭円錐形状を有していることを特徴とする請求項3に記載の相互接続要素。
- 前記第2の金属層は、複数の導電性トレースを備えており、前記相互接続要素は、前記第2の層を覆う第2の誘電体層、前記第2の誘電体要素を覆う第3の金属層、前記第2の金属層から前記第2の誘電体層を通って上方に延在する複数の第2の導電性突起、および前記第2の誘電体層の開口を通って延在して前記第2の導電性突起を前記第3の金属層に導電接続している複数のメッキ形成された第2の特徴部をさらに備えていることを特徴とする請求項3に記載の相互接続要素。
- 前記第3の金属層は、複数の導電性トレースを備えていることを特徴とする請求項10に記載の相互接続要素。
- 前記第3の金属層から上方に延在している複数の第3の導電性突起をさらに備えていることを特徴とする請求項10に記載の相互接続要素。
- パッケージ化された超小型電子要素であって、
上面および前記上面から離れた底面を有している誘電体層と、
前記底面に沿って延在している平面を画定している第1の金属層と、
前記上面に沿って延在している第2の金属層であって、前記第1の金属層および前記第2の金属層の少なくとも1つは、複数の導電性トレースを備えている、第2の金属層と、
前記第1の金属層によって画定された前記平面から前記誘電体層を通って上方に延在している複数の導電性突起と、
前記第1の配線層と前記第2の配線層との間に配置された超小型電子素子であって、前記誘電体層によって前記第2の金属層から隔離されている接触支持面を有している、超小型電子素子と、
前記誘電体層の開口を通って延在して前記導電性突起および前記超小型電子素子の接点を前記第2の金属層に導電接続している、複数のメッキ形成された特徴部と
を備えていることを特徴とするパッケージ化された超小型電子要素。 - 前記第1の金属層および前記第2の金属層の各々は、複数の導電性トレースを備えていることを特徴とする請求項13に記載のパッケージ化された超小型電子素子。
- 前記導電性突起は、エッチング形成された金属ポストを含んでいることを特徴とする請求項13に記載のパッケージ化された超小型電子素子。
- 前記導電性突起は、メッキ形成された金属層を含んでいることを特徴とする請求項13に記載のパッケージ化された超小型電子素子。
- 前記導電性突起は、中空の導電性突起を含んでいることを特徴とする請求項14に記載のパッケージ化された超小型電子素子。
- 前記第1の金属層は、前記平面と真っ直ぐに並んだ平面部分および前記平面から離れる方に延在している突出部分を備えており、前記突出部分は、前記導電性突起を画定していることを特徴とする請求項13に記載のパッケージ化された超小型電子素子。
- 前記導電性突起は、切頭円錐形状を有していることを特徴とする請求項13に記載のパッケージ化された超小型電子素子。
- 能動構成部品または受動構成部品の少なくとも1つが組み込まれている多配線層相互接続要素であって、
上面および前記上面から離れた底面を有する誘電体層と、
前記底面に沿って延在している平面を画定している第1の金属層と、
前記上面に沿って延在している第2の金属層であって、前記第1の金属層および前記第2の金属層の少なくとも1つは、複数の導電性トレースを備えている、第2の金属層と、
前記平面から前記誘電体層を通って上方に延在している複数の導電性突起と、
前記第1の金属層と前記第2の金属層との間に配置された能動構成部品または受動構成部品の少なくとも1つであって、前記第2の金属層と向き合って前記誘電体層によって前記第2の金属層から隔離されている複数の端子を有している、能動構成部品または受動構成部品の少なくとも1つと、
前記誘電体層の開口を通って延在して前記導電性突起および前記構成部品の前記端子を前記第2の金属層に導電接続している複数のメッキ形成された特徴部と
を備えていることを特徴とする多層配線層相互接続要素。 - 少なくとも1つの誘電体層によって互いに隔離された複数の配線層を有している相互接続要素を製造する方法であって、
(a)誘電体層および前記誘電体層の上の第1の金属層を、平面を画定している少なくとも一部を有する第2の金属層および前記平面から上方に延在している複数の導電性突起を備えているベース要素上に、前記誘電体層の一部が前記導電性突起の互いに隣接するものを互いに隔離するように、積層するステップと、
(b)前記導電性突起の少なくとも上面を露出させる開口を、前記誘電体層に形成するステップと、
(c)前記開口内の前記導電性突起の前記露出面に金属をメッキし、前記導電性突起を前記第1の金属層に接続するメッキ形成された特徴部を形成するステップと
を含んでいることを特徴とする方法。 - 前記メッキ形成された特徴部を形成した後、前記第2の金属層をパターン化し、配線パターンを形成するステップをさらに含んでいることを特徴とする請求項21に記載の方法。
- 前記メッキ形成された特徴部を形成した後、前記第1の金属層をパターン化し、配線パターンを形成するステップをさらに含んでいることを特徴とする請求項21に記載の方法。
- 前記誘電体層は、未硬化の誘電体要素を含んでおり、前記ステップ(a)は、前記未硬化の誘電体要素を前記第2の金属層および前記金属層の上の前記導電性突起上に約200℃以下の温度で加圧し、次いで、前記未硬化の誘電体要素を硬化することによって行われることを特徴とする請求項21に記載の方法。
- 前記ステップ(a)中、前記第1の金属層および前記第2の金属層は、連続的な平面を画定していることを特徴とする請求項21に記載の方法。
- 前記ステップ(a)中、前記第1の金属層および前記第2の金属層の少なくとも1つは、平面を画定している方向に延在している複数の個々のトレースを備えていることを特徴とする請求項21に記載の方法。
- 前記ステップ(a)中、前記第1の金属層は、複数の開口を備えており、前記ステップ(a)は、前記第1の金属層を、前記複数の開口が前記導電性突起と真っ直ぐに並ぶように、前記ベース要素上に積層することを含んでいることを特徴とする請求項21に記載の方法。
- 前記誘電体層の前記開口は、エッチングによって形成されていることを特徴とする請求項21に記載の方法。
- 前記誘電体層の前記開口は、レーザ融除によって形成されていることを特徴とする請求項21に記載の方法。
- 前記ステップ(a)において前記第1の金属層が前記誘電体層と一緒に前記ベース要素に積層されるとき、前記第1の金属層は、前記ベース要素の前記導電性突起と真っ直ぐに並んだ開口を有しており、前記第1の金属層は、前記第1の金属層を覆っている第3の金属層に接合されていることを特徴とする請求項21に記載の方法。
- 前記第3の金属層をパターン化し、前記第1の金属層から上方に延在する第2の導電性突起を形成することを含んでいることを特徴とする請求項30に記載の方法。
- 前記第1の金属層に取り付けられている前記第3の金属層をエッチングし、前記ベース要素の前記導電性突起を形成することをさらに含んでいることを特徴とする請求項30に記載の方法。
- 前記第3の金属層をマンドレルの凹部内にメッキし、前記マンドレルを除去し、前記導電性突起を形成することをさらに含んでいることを特徴とする請求項30に記載の方法。
- 前記導電性突起は、中空の導電性突起を備えていることを特徴とする請求項21に記載の方法。
- (d)第2の誘電体層および前記誘電体層の上の第4の金属層を、前記第1の金属層および前記第1の金属層から上方に延在する複数の第2の導電性突起上に、前記第2の誘電体層の一部が前記第2の導電性突起の互いに隣接しているものを互いに隔離するように、積層するステップと、
(e)前記第2の導電性突起の少なくとも上面を露出させる開口を、前記第2の誘電体層に形成するステップと、
(f)前記第2の誘電体層の前記開口内の前記第2の導電性突起の前記露出面上に金属をメッキし、前記第2の導電性突起を前記第4の金属層に接続する第2のメッキ形成された特徴部を形成するステップと
をさらに含んでいることを特徴とする請求項31に記載の方法。 - 前記ステップ(d)中、前記第1の金属層、前記第2の金属層、および前記第4の金属層は、連続的な平面を画定していることを特徴とする請求項35に記載の方法。
- 前記ステップ(d)中、前記第2の金属層および前記第4の金属層の少なくとも1つは、平面を画定している方向において延在している複数の個々のトレースを備えていることを特徴とする請求項35に記載の方法。
- 前期ステップ(d)において、前記第4の金属層が、前記第2の誘電体層と一緒に、前記第1の金属層および前記第1の金属層から延在している第2の導電性突起上に積層されるとき、前記第4の金属層は、前記第2の導電性突起と真っ直ぐに並んだ開口を有しており、前記第4の金属層を覆っている第5の金属層に取り付けられていることを特徴とする請求項35に記載の方法。
- ステップ(e)の前に、前記第5の金属層をパターン化し、前記第4の金属層から上方に延在する第3の導電性突起を形成することをさらに含んでいることを特徴とする請求項38に記載の方法。
- 少なくとも1つの誘電体層によって互いに隔離された複数の配線層を有する相互接続要素の配線層間に、超小型電子素子をパッケージ化する方法であって、
平面を画定している少なくとも一部を有している第2の金属層と、前記平面から上方に延在している複数の導電性突起と、前記平面に隣接する第1の面を有している超小型電子素子と、を備えている第1の要素の上に、誘電体層および前記誘電体層の上の第1の金属層を積層するステップであって、前記積層ステップは、前記誘電体層の一部が前記導電性突起の互いに隣接するものを互いに隔離すると共に前記超小型電子素子を前記導電性突起から隔離するように行われるものである、ステップと、
前記超小型電子素子の第2の面の接点および前記導電性突起の少なくとも上面を露出させる開口を、前記誘電体層に形成するステップと、
前記開口内の前記露出した接点および前記導電性突起の前記露出面に金属をメッキし、前記接点および前記導電性突起を前記第1の金属層に接続するためのメッキ形成された特徴部を形成するステップと
を含んでいることを特徴とする方法。 - 前記第1の金属層は、前記超小型電子素子の前記第1の面に取り付けられた熱伝導性プレートを備えていることを特徴とする請求項40に記載の方法。
- 少なくとも1つの誘電体層によって互いに隔離された複数の配線層を有している相互接続要素のそれぞれの配線層間に、能動構成部品または受動構成部品の少なくとも1つを備えている多配線層相互接続要素を形成する方法であって、
平面を画定している少なくとも一部を有している第2の金属層と、前記平面から上方に延在している複数の導電性突起と、前記平面を覆う面を有している能動構成部品または受動構成部品の少なくとも1つと、を備えている第1の要素上に、誘電体層および前記誘電体層の上の第1の金属層を積層するステップであって、前記積層ステップは、前記誘電体層の一部が前記導電性突起の互いに隣接するものおよび前記電気素子を互いに隔離するように行われるものである、ステップと、
前記電気素子の接点および前記導電性突起の少なくとも上面を露出させる開口を、前記誘電体層に形成するステップと、
前記開口内の前記露出した接点および前記導電性突起の前記露出面上に金属をメッキし、前記接点および前記導電性突起を前記第2の金属層に接続するメッキ形成された特徴部を形成するステップと
を含んでいることを特徴とする方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US99856407P | 2007-10-10 | 2007-10-10 | |
PCT/US2008/011632 WO2009048604A2 (en) | 2007-10-10 | 2008-10-08 | Robust multi-layer wiring elements and assemblies with embedded microelectronic elements |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011501410A true JP2011501410A (ja) | 2011-01-06 |
JP2011501410A5 JP2011501410A5 (ja) | 2011-11-17 |
Family
ID=40549781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010528888A Pending JP2011501410A (ja) | 2007-10-10 | 2008-10-08 | 頑健な多層配線要素および埋設された超小型電子素子とのアセンブリ |
Country Status (5)
Country | Link |
---|---|
US (2) | US20090115047A1 (ja) |
EP (1) | EP2213148A4 (ja) |
JP (1) | JP2011501410A (ja) |
KR (1) | KR101572600B1 (ja) |
WO (1) | WO2009048604A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013140957A (ja) * | 2011-12-28 | 2013-07-18 | Samsung Electro-Mechanics Co Ltd | 印刷回路基板及びその製造方法 |
Families Citing this family (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8641913B2 (en) | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
US7709968B2 (en) | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
EP2206145A4 (en) | 2007-09-28 | 2012-03-28 | Tessera Inc | FLIP-CHIP CONNECTION WITH DOUBLE POSTS |
EP2213148A4 (en) | 2007-10-10 | 2011-09-07 | Tessera Inc | ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED |
KR101195786B1 (ko) | 2008-05-09 | 2012-11-05 | 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 | 칩 사이즈 양면 접속 패키지의 제조 방법 |
WO2010109746A1 (ja) * | 2009-03-27 | 2010-09-30 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US8847375B2 (en) * | 2010-01-28 | 2014-09-30 | Qualcomm Incorporated | Microelectromechanical systems embedded in a substrate |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US8847376B2 (en) | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
KR101128559B1 (ko) * | 2010-09-13 | 2012-03-23 | 삼성전기주식회사 | 인쇄회로기판의 비아홀 형성방법 |
KR101167429B1 (ko) * | 2010-10-11 | 2012-07-19 | 삼성전기주식회사 | 반도체 패키지의 제조방법 |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8546900B2 (en) | 2011-06-09 | 2013-10-01 | Optiz, Inc. | 3D integration microelectronic assembly for integrated circuit devices |
US8546951B2 (en) | 2011-06-09 | 2013-10-01 | Optiz, Inc. | 3D integration microelectronic assembly for integrated circuit devices |
US8552518B2 (en) | 2011-06-09 | 2013-10-08 | Optiz, Inc. | 3D integrated microelectronic assembly with stress reducing interconnects |
US8604576B2 (en) | 2011-07-19 | 2013-12-10 | Opitz, Inc. | Low stress cavity package for back side illuminated image sensor, and method of making same |
US9018725B2 (en) | 2011-09-02 | 2015-04-28 | Optiz, Inc. | Stepped package for image sensor and method of making same |
US8404520B1 (en) | 2011-10-17 | 2013-03-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8796800B2 (en) | 2011-11-21 | 2014-08-05 | Optiz, Inc. | Interposer package for CMOS image sensor and method of making same |
US8432011B1 (en) | 2011-12-06 | 2013-04-30 | Optiz, Inc. | Wire bond interposer package for CMOS image sensor and method of making same |
US8570669B2 (en) | 2012-01-23 | 2013-10-29 | Optiz, Inc | Multi-layer polymer lens and method of making same |
US8692344B2 (en) | 2012-03-16 | 2014-04-08 | Optiz, Inc | Back side illuminated image sensor architecture, and method of making same |
US9233511B2 (en) | 2012-05-10 | 2016-01-12 | Optiz, Inc. | Method of making stamped multi-layer polymer lens |
US8921759B2 (en) | 2012-07-26 | 2014-12-30 | Optiz, Inc. | Integrated image sensor package with liquid crystal lens |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8759930B2 (en) | 2012-09-10 | 2014-06-24 | Optiz, Inc. | Low profile image sensor package |
JP6143104B2 (ja) * | 2012-12-05 | 2017-06-07 | 株式会社村田製作所 | バンプ付き電子部品及びバンプ付き電子部品の製造方法 |
US9190443B2 (en) | 2013-03-12 | 2015-11-17 | Optiz Inc. | Low profile image sensor |
US9219091B2 (en) | 2013-03-12 | 2015-12-22 | Optiz, Inc. | Low profile sensor module and method of making same |
US9142695B2 (en) | 2013-06-03 | 2015-09-22 | Optiz, Inc. | Sensor package with exposed sensor array and method of making same |
US9398700B2 (en) | 2013-06-21 | 2016-07-19 | Invensas Corporation | Method of forming a reliable microelectronic assembly |
US9070568B2 (en) * | 2013-07-26 | 2015-06-30 | Infineon Technologies Ag | Chip package with embedded passive component |
US9190389B2 (en) | 2013-07-26 | 2015-11-17 | Infineon Technologies Ag | Chip package with passives |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9496247B2 (en) | 2013-08-26 | 2016-11-15 | Optiz, Inc. | Integrated camera module and method of making same |
US9461190B2 (en) | 2013-09-24 | 2016-10-04 | Optiz, Inc. | Low profile sensor package with cooling feature and method of making same |
US9496297B2 (en) | 2013-12-05 | 2016-11-15 | Optiz, Inc. | Sensor package with cooling feature and method of making same |
US9667900B2 (en) | 2013-12-09 | 2017-05-30 | Optiz, Inc. | Three dimensional system-on-chip image sensor package |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US9355997B2 (en) | 2014-03-12 | 2016-05-31 | Invensas Corporation | Integrated circuit assemblies with reinforcement frames, and methods of manufacture |
US9637375B2 (en) * | 2014-04-15 | 2017-05-02 | Taiwan Semiconductor Manufacturing Company Limited | MEMS device having a getter structure and method of forming the same |
US9985063B2 (en) | 2014-04-22 | 2018-05-29 | Optiz, Inc. | Imaging device with photo detectors and color filters arranged by color transmission characteristics and absorption coefficients |
US9524917B2 (en) | 2014-04-23 | 2016-12-20 | Optiz, Inc. | Chip level heat dissipation using silicon |
US9165793B1 (en) | 2014-05-02 | 2015-10-20 | Invensas Corporation | Making electrical components in handle wafers of integrated circuit packages |
US9741649B2 (en) | 2014-06-04 | 2017-08-22 | Invensas Corporation | Integrated interposer solutions for 2D and 3D IC packaging |
US9412806B2 (en) | 2014-06-13 | 2016-08-09 | Invensas Corporation | Making multilayer 3D capacitors using arrays of upstanding rods or ridges |
US9252127B1 (en) | 2014-07-10 | 2016-02-02 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
US9681558B2 (en) | 2014-08-12 | 2017-06-13 | Infineon Technologies Ag | Module with integrated power electronic circuitry and logic circuitry |
US9666730B2 (en) | 2014-08-18 | 2017-05-30 | Optiz, Inc. | Wire bond sensor package |
US10211158B2 (en) * | 2014-10-31 | 2019-02-19 | Infineon Technologies Ag | Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module |
US9543347B2 (en) | 2015-02-24 | 2017-01-10 | Optiz, Inc. | Stress released image sensor package structure and method |
US9478504B1 (en) | 2015-06-19 | 2016-10-25 | Invensas Corporation | Microelectronic assemblies with cavities, and methods of fabrication |
KR101672640B1 (ko) * | 2015-06-23 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
US10276541B2 (en) | 2015-06-30 | 2019-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D package structure and methods of forming same |
US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
DE112015007213B4 (de) * | 2015-12-22 | 2021-08-19 | Intel Corporation | Halbleiter-package mit durchgangsbrücken-die-verbindungen und verfahren zum herstellen eines halbleiter-package |
TWI822659B (zh) | 2016-10-27 | 2023-11-21 | 美商艾德亞半導體科技有限責任公司 | 用於低溫接合的結構和方法 |
US9996725B2 (en) | 2016-11-03 | 2018-06-12 | Optiz, Inc. | Under screen sensor assembly |
FR3060846B1 (fr) * | 2016-12-19 | 2019-05-24 | Institut Vedecom | Procede d’integration de puces de puissance et de bus barres formant dissipateurs thermiques |
US10181447B2 (en) | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
EP3478033A1 (en) * | 2017-10-25 | 2019-05-01 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Embedding component with pre-connected pillar in component carrier |
US10340180B1 (en) * | 2018-01-16 | 2019-07-02 | Globalfoundries Inc. | Merge mandrel features |
US11408589B2 (en) | 2019-12-05 | 2022-08-09 | Optiz, Inc. | Monolithic multi-focus light source device |
KR20210076584A (ko) * | 2019-12-16 | 2021-06-24 | 삼성전기주식회사 | 전자부품 내장기판 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006019361A (ja) * | 2004-06-30 | 2006-01-19 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
Family Cites Families (67)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3679941A (en) * | 1969-09-22 | 1972-07-25 | Gen Electric | Composite integrated circuits including semiconductor chips mounted on a common substrate with connections made through a dielectric encapsulator |
US5091769A (en) * | 1991-03-27 | 1992-02-25 | Eichelberger Charles W | Configuration for testing and burn-in of integrated circuit chips |
US5250843A (en) * | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5111278A (en) * | 1991-03-27 | 1992-05-05 | Eichelberger Charles W | Three-dimensional multichip module systems |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5442143A (en) * | 1993-04-16 | 1995-08-15 | Dyconex Patente Ag | Core for electrical connecting substrates and electrical connecting substrates with core, as well as process for the production thereof |
JP2736042B2 (ja) * | 1995-12-12 | 1998-04-02 | 山一電機株式会社 | 回路基板 |
US5841193A (en) * | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US6083837A (en) * | 1996-12-13 | 2000-07-04 | Tessera, Inc. | Fabrication of components by coining |
US6081989A (en) * | 1998-04-30 | 2000-07-04 | Lockheed Martin Corporation | Fabrication of circuit modules with a transmission line |
US6081988A (en) * | 1998-04-30 | 2000-07-04 | Lockheed Martin Corp. | Fabrication of a circuit module with a coaxial transmission line |
TW512467B (en) * | 1999-10-12 | 2002-12-01 | North Kk | Wiring circuit substrate and manufacturing method therefor |
US6251710B1 (en) * | 2000-04-27 | 2001-06-26 | International Business Machines Corporation | Method of making a dual damascene anti-fuse with via before wire |
US6562709B1 (en) * | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
US6660626B1 (en) * | 2000-08-22 | 2003-12-09 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
US6511865B1 (en) * | 2000-09-20 | 2003-01-28 | Charles W. C. Lin | Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly |
US6548393B1 (en) * | 2000-10-13 | 2003-04-15 | Charles W. C. Lin | Semiconductor chip assembly with hardened connection joint |
US20050097727A1 (en) * | 2001-03-28 | 2005-05-12 | Tomoo Iijima | Multi-layer wiring board, method for producing multi-layer wiring board, polishing machine for multi-layer wiring board, and metal sheet for producing wiring board |
US6930256B1 (en) * | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
US7176506B2 (en) * | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
US6856007B2 (en) * | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
US6762076B2 (en) * | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
US6593224B1 (en) * | 2002-03-05 | 2003-07-15 | Bridge Semiconductor Corporation | Method of manufacturing a multilayer interconnect substrate |
US7633765B1 (en) * | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7548430B1 (en) * | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
US6759264B2 (en) * | 2002-05-17 | 2004-07-06 | Ligh Tuning Technology Inc. | Pressure type fingerprint sensor fabrication method |
DE10228593A1 (de) * | 2002-06-26 | 2004-01-15 | Infineon Technologies Ag | Elektronisches Bauteil mit einer Gehäusepackung |
WO2004077525A2 (en) * | 2003-02-25 | 2004-09-10 | Tessera, Inc. | Ball grid array with bumps |
US6700195B1 (en) * | 2003-03-26 | 2004-03-02 | Delphi Technologies, Inc. | Electronic assembly for removing heat from a flip chip |
JP4016340B2 (ja) * | 2003-06-13 | 2007-12-05 | ソニー株式会社 | 半導体装置及びその実装構造、並びにその製造方法 |
US7462936B2 (en) * | 2003-10-06 | 2008-12-09 | Tessera, Inc. | Formation of circuitry with modification of feature height |
US8641913B2 (en) * | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
US7495179B2 (en) * | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
TWI223103B (en) * | 2003-10-23 | 2004-11-01 | Ind Tech Res Inst | Wire grid polarizer with double metal layers |
JP4120562B2 (ja) * | 2003-10-31 | 2008-07-16 | 沖電気工業株式会社 | 受動素子チップ、高集積モジュール、受動素子チップの製造方法、及び高集積モジュールの製造方法。 |
JP2005191100A (ja) * | 2003-12-24 | 2005-07-14 | Shinko Electric Ind Co Ltd | 半導体基板及びその製造方法 |
US7709968B2 (en) * | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
US7176043B2 (en) * | 2003-12-30 | 2007-02-13 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8207604B2 (en) * | 2003-12-30 | 2012-06-26 | Tessera, Inc. | Microelectronic package comprising offset conductive posts on compliant layer |
US7453157B2 (en) * | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
TWI229433B (en) * | 2004-07-02 | 2005-03-11 | Phoenix Prec Technology Corp | Direct connection multi-chip semiconductor element structure |
US7301239B2 (en) * | 2004-07-26 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wiring structure to minimize stress induced void formation |
WO2006020744A2 (en) * | 2004-08-12 | 2006-02-23 | Tessera, Inc. | Structure and method of forming capped chips |
TW200611612A (en) * | 2004-09-29 | 2006-04-01 | Unimicron Technology Corp | Process of electrically interconnect structure |
JP2006156669A (ja) | 2004-11-29 | 2006-06-15 | Dainippon Printing Co Ltd | 部品内蔵配線板、部品内蔵配線板の製造方法 |
JP4761762B2 (ja) | 2004-12-03 | 2011-08-31 | ソニーケミカル&インフォメーションデバイス株式会社 | 多層配線基板の製造方法 |
US7317249B2 (en) * | 2004-12-23 | 2008-01-08 | Tessera, Inc. | Microelectronic package having stacked semiconductor devices and a process for its fabrication |
JP4792749B2 (ja) | 2005-01-14 | 2011-10-12 | 大日本印刷株式会社 | 電子部品内蔵プリント配線板の製造方法 |
US7939934B2 (en) * | 2005-03-16 | 2011-05-10 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP4738895B2 (ja) | 2005-05-31 | 2011-08-03 | 日本メクトロン株式会社 | ビルドアップ型多層フレキシブル回路基板の製造方法 |
JP4826248B2 (ja) * | 2005-12-19 | 2011-11-30 | Tdk株式会社 | Ic内蔵基板の製造方法 |
US8058101B2 (en) * | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US20080185705A1 (en) * | 2005-12-23 | 2008-08-07 | Tessera, Inc. | Microelectronic packages and methods therefor |
WO2007130471A2 (en) * | 2006-05-01 | 2007-11-15 | The Charles Stark Draper Laboratory, Inc. | Systems and methods for high density multi-component modules |
KR100751995B1 (ko) * | 2006-06-30 | 2007-08-28 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US7545029B2 (en) * | 2006-08-18 | 2009-06-09 | Tessera, Inc. | Stack microelectronic assemblies |
US7659631B2 (en) * | 2006-10-12 | 2010-02-09 | Hewlett-Packard Development Company, L.P. | Interconnection between different circuit types |
US7719121B2 (en) * | 2006-10-17 | 2010-05-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7550857B1 (en) * | 2006-11-16 | 2009-06-23 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US20080150101A1 (en) * | 2006-12-20 | 2008-06-26 | Tessera, Inc. | Microelectronic packages having improved input/output connections and methods therefor |
US7709297B2 (en) * | 2006-12-29 | 2010-05-04 | Tessera, Inc. | Microelectronic package with thermal access |
KR100751955B1 (ko) | 2007-05-28 | 2007-08-27 | 오원록 | 배수로 뚜껑을 대량생산하는 이동식 대차구조 |
EP2213148A4 (en) | 2007-10-10 | 2011-09-07 | Tessera Inc | ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED |
US8330272B2 (en) * | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8580607B2 (en) * | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8647796B2 (en) * | 2011-07-27 | 2014-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photoactive compound gradient photoresist |
JP2014013810A (ja) * | 2012-07-04 | 2014-01-23 | Seiko Epson Corp | 基板、基板の製造方法、半導体装置、及び電子機器 |
-
2008
- 2008-10-08 EP EP08837045A patent/EP2213148A4/en not_active Withdrawn
- 2008-10-08 US US12/287,380 patent/US20090115047A1/en not_active Abandoned
- 2008-10-08 KR KR1020107010116A patent/KR101572600B1/ko not_active IP Right Cessation
- 2008-10-08 JP JP2010528888A patent/JP2011501410A/ja active Pending
- 2008-10-08 WO PCT/US2008/011632 patent/WO2009048604A2/en active Application Filing
-
2016
- 2016-09-30 US US15/282,255 patent/US10032646B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006019361A (ja) * | 2004-06-30 | 2006-01-19 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013140957A (ja) * | 2011-12-28 | 2013-07-18 | Samsung Electro-Mechanics Co Ltd | 印刷回路基板及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP2213148A2 (en) | 2010-08-04 |
KR101572600B1 (ko) | 2015-11-27 |
US20090115047A1 (en) | 2009-05-07 |
WO2009048604A3 (en) | 2009-09-24 |
EP2213148A4 (en) | 2011-09-07 |
KR20100086472A (ko) | 2010-07-30 |
US20170018440A1 (en) | 2017-01-19 |
WO2009048604A2 (en) | 2009-04-16 |
US10032646B2 (en) | 2018-07-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10032646B2 (en) | Robust multi-layer wiring elements and assemblies with embedded microelectronic elements | |
EP2172089B1 (en) | Method for manufacturing a multilayer wiring element having pin interface | |
US6998290B2 (en) | Economical high density chip carrier | |
US8304664B2 (en) | Electronic component mounted structure | |
JP4055717B2 (ja) | 半導体装置およびその製造方法 | |
US7122901B2 (en) | Semiconductor device | |
EP1763295A2 (en) | Electronic component embedded board and its manufacturing method | |
KR20070059186A (ko) | 상호접속 소자를 제조하는 구조와 방법, 및 이 상호접속소자를 포함하는 다층 배선 기판 | |
JP2005217225A (ja) | 半導体装置及びその製造方法 | |
KR20090092326A (ko) | 칩 커패시터 내장 pwb | |
TW201507556A (zh) | 具有散熱墊及電性突柱之散熱增益型線路板 | |
JP4597631B2 (ja) | 部品内蔵配線板、部品内蔵配線板の製造方法 | |
JP5192865B2 (ja) | 部品内蔵配線基板の製造方法 | |
JP4759981B2 (ja) | 電子部品内蔵モジュールの製造方法 | |
JP2008529283A (ja) | 誘電体の表面に埋め込まれた金属トレースを有する相互接続要素を作る構成および方法 | |
JP2010258335A (ja) | 部品内蔵配線板、部品内蔵配線板の製造方法 | |
JP2008244029A (ja) | 部品内蔵配線基板、配線基板内蔵用部品 | |
JP2006303338A (ja) | 多層回路基板とその製造方法 | |
KR100997880B1 (ko) | 칩 내장 기판의 패드와 기판을 접속 제조하는 방법 및 이를적용한 다기능 인쇄회로기판 | |
US20040063040A1 (en) | Joining member for Z-interconnect in electronic devices without conductive paste | |
JP2004087721A (ja) | 配線板の製造方法、配線板、半導体パッケージ用部材 | |
JPH11145622A (ja) | 多層配線基板 | |
KR20080043207A (ko) | 능동 소자 내장형 인쇄회로기판 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110930 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110930 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121026 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121102 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130130 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130206 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130301 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130308 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130402 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130409 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130426 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20131018 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140218 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20140227 |
|
A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20140418 |