JP4761762B2 - 多層配線基板の製造方法 - Google Patents
多層配線基板の製造方法 Download PDFInfo
- Publication number
- JP4761762B2 JP4761762B2 JP2004352060A JP2004352060A JP4761762B2 JP 4761762 B2 JP4761762 B2 JP 4761762B2 JP 2004352060 A JP2004352060 A JP 2004352060A JP 2004352060 A JP2004352060 A JP 2004352060A JP 4761762 B2 JP4761762 B2 JP 4761762B2
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- stainless steel
- multilayer wiring
- wiring board
- steel plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
- B32B37/26—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer which influences the bonding during the lamination process, e.g. release layers or pressure equalising layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/08—PCBs, i.e. printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49163—Manufacturing circuit on or in base with sintering of base
Description
先ず、従来方法により成型を行った。すなわち、製品を通常のステンレス板で挟み込み、銅箔6の熱圧着(成型)を行った。製造プロセスは、第1の実施形態と同様である。その結果、製品の貼り付きが生じ、得られた製品にシワや凹凸が発生した。また、製品の引き剥がしが困難で、楔を入れて引き剥がした。比較例における寸法安定性(ばらつき)3σは、0.05%(N数=50W)であり、ばらつきが大きい値となっていた。
本実施例では、熱圧着に際して、防錆処理した銅箔22を銅箔6とステンレス板21の間に介在させた。使用した銅箔22は、厚さ12μm、ロープロファイル(3μm)である。
本実施例も、先の実施例と同様、銅箔を介在させた例であるが、本例の場合には、図4に示す通り、防錆処理した銅箔22を製品の両側、すなわち、銅箔6とステンレス板21の間、及び銅箔3とステンレス板21の間に介在させた。使用した銅箔22は、厚さ12μm、プロファイルは5μm程度である。
Claims (3)
- 層間接続のための銅からなるバンプが形成された基材上に絶縁層を形成する工程と、ステンレス板で挟み込み前記絶縁層上に銅箔を熱圧着する工程と、前記銅箔をパターンニングする工程とを有し、積層の際の前記バンプの位置において圧力の集中を低減するように少なくとも前記ステンレス板と前記銅箔との間に金属箔を介在させることを特徴とする多層配線基板の製造方法。
- 熱圧着時のプレスの圧力が90〜150Kg/cm2の範囲であることを特徴とする請求項1記載の多層配線基板の製造方法。
- 前記ステンレス板と前記銅箔との間に介在される金属箔は銅箔であることを特徴とする請求項1記載の多層配線基板の製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004352060A JP4761762B2 (ja) | 2004-12-03 | 2004-12-03 | 多層配線基板の製造方法 |
PCT/JP2005/017926 WO2006059428A1 (ja) | 2004-12-03 | 2005-09-29 | 多層配線基板の製造方法 |
CN200580041604XA CN101288349B (zh) | 2004-12-03 | 2005-09-29 | 多层布线基板的制作方法 |
KR1020077013198A KR101168879B1 (ko) | 2004-12-03 | 2005-09-29 | 다층배선기판의 제조방법 |
US11/720,711 US8112881B2 (en) | 2004-12-03 | 2005-09-29 | Method for manufacturing multilayer wiring board |
EP05788279A EP1821588A4 (en) | 2004-12-03 | 2005-09-29 | PROCESS FOR MANUFACTURING A MULTILAYER CONDUCTOR PLATE |
TW094137944A TW200621105A (en) | 2004-12-03 | 2005-10-28 | Manufacturing method of multi-patterned-layer substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004352060A JP4761762B2 (ja) | 2004-12-03 | 2004-12-03 | 多層配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006165133A JP2006165133A (ja) | 2006-06-22 |
JP4761762B2 true JP4761762B2 (ja) | 2011-08-31 |
Family
ID=36564868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004352060A Expired - Fee Related JP4761762B2 (ja) | 2004-12-03 | 2004-12-03 | 多層配線基板の製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8112881B2 (ja) |
EP (1) | EP1821588A4 (ja) |
JP (1) | JP4761762B2 (ja) |
KR (1) | KR101168879B1 (ja) |
CN (1) | CN101288349B (ja) |
TW (1) | TW200621105A (ja) |
WO (1) | WO2006059428A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2213148A4 (en) | 2007-10-10 | 2011-09-07 | Tessera Inc | ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED |
CN101626660B (zh) * | 2008-07-11 | 2012-08-29 | 惠阳科惠工业科技有限公司 | 结构不对称多层板铜面相靠压合工艺 |
WO2011037138A1 (ja) * | 2009-09-25 | 2011-03-31 | 住友化学株式会社 | 金属箔積層体の製造方法 |
KR101089986B1 (ko) * | 2009-12-24 | 2011-12-05 | 삼성전기주식회사 | 캐리어기판, 그의 제조방법, 이를 이용한 인쇄회로기판 및 그의 제조방법 |
KR101048597B1 (ko) * | 2010-05-25 | 2011-07-12 | 주식회사 코리아써키트 | 범프가 형성된 인쇄회로기판의 제조방법 |
TWI572261B (zh) * | 2014-10-29 | 2017-02-21 | 健鼎科技股份有限公司 | 線路結構及線路結構的製作方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0333744B1 (en) * | 1986-11-13 | 1995-08-30 | JOHNSTON, James A. | Method and apparatus for manufacturing printed circuit boards |
US5256474A (en) * | 1986-11-13 | 1993-10-26 | Johnston James A | Method of and apparatus for manufacturing printed circuit boards |
JP2556897B2 (ja) * | 1989-02-23 | 1996-11-27 | ファナック株式会社 | 多層プリント配線板の外層材及び製造方法 |
JPH0946041A (ja) * | 1995-07-26 | 1997-02-14 | Toshiba Corp | 印刷配線板の製造方法 |
JP3633136B2 (ja) * | 1996-09-18 | 2005-03-30 | 株式会社東芝 | 印刷配線基板 |
JP3428480B2 (ja) | 1998-12-28 | 2003-07-22 | 新神戸電機株式会社 | 内層回路入り多層金属箔張り積層板の製造法 |
CN1371240A (zh) * | 2001-02-23 | 2002-09-25 | 华泰电子股份有限公司 | 多层式高密度基板的制造方法 |
JP2003008200A (ja) | 2001-06-22 | 2003-01-10 | Matsushita Electric Ind Co Ltd | 配線基板とその製造方法 |
JP3526838B2 (ja) | 2001-10-22 | 2004-05-17 | 株式会社ノース | 銅膜又は銅系膜に対する選択的エッチング方法と、選択的エッチング装置。 |
JP4045143B2 (ja) * | 2002-02-18 | 2008-02-13 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 配線膜間接続用部材の製造方法及び多層配線基板の製造方法 |
JP3952862B2 (ja) | 2002-05-30 | 2007-08-01 | 新神戸電機株式会社 | 内層回路入り金属箔張り積層板の製造法 |
JP4242623B2 (ja) * | 2002-09-18 | 2009-03-25 | 北川精機株式会社 | 配線回路基板の製造方法 |
JP2004221310A (ja) * | 2003-01-15 | 2004-08-05 | Daiwa Kogyo:Kk | 配線基板部材及びその製造方法 |
-
2004
- 2004-12-03 JP JP2004352060A patent/JP4761762B2/ja not_active Expired - Fee Related
-
2005
- 2005-09-29 WO PCT/JP2005/017926 patent/WO2006059428A1/ja active Application Filing
- 2005-09-29 KR KR1020077013198A patent/KR101168879B1/ko not_active IP Right Cessation
- 2005-09-29 EP EP05788279A patent/EP1821588A4/en not_active Withdrawn
- 2005-09-29 CN CN200580041604XA patent/CN101288349B/zh not_active Expired - Fee Related
- 2005-09-29 US US11/720,711 patent/US8112881B2/en not_active Expired - Fee Related
- 2005-10-28 TW TW094137944A patent/TW200621105A/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2006165133A (ja) | 2006-06-22 |
US8112881B2 (en) | 2012-02-14 |
TW200621105A (en) | 2006-06-16 |
CN101288349A (zh) | 2008-10-15 |
TWI371232B (ja) | 2012-08-21 |
KR20070094896A (ko) | 2007-09-27 |
KR101168879B1 (ko) | 2012-07-26 |
EP1821588A1 (en) | 2007-08-22 |
CN101288349B (zh) | 2010-06-09 |
US20080110018A1 (en) | 2008-05-15 |
WO2006059428A1 (ja) | 2006-06-08 |
EP1821588A4 (en) | 2009-11-11 |
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