TW200621105A - Manufacturing method of multi-patterned-layer substrate - Google Patents

Manufacturing method of multi-patterned-layer substrate

Info

Publication number
TW200621105A
TW200621105A TW094137944A TW94137944A TW200621105A TW 200621105 A TW200621105 A TW 200621105A TW 094137944 A TW094137944 A TW 094137944A TW 94137944 A TW94137944 A TW 94137944A TW 200621105 A TW200621105 A TW 200621105A
Authority
TW
Taiwan
Prior art keywords
substrate
patterned
copper film
layer
compressed
Prior art date
Application number
TW094137944A
Other languages
English (en)
Other versions
TWI371232B (zh
Inventor
Kazuhiro Shimizu
Masanobu Yagi
Kenichiro Hanamura
Mitsuyuki Takayasu
Kiyoe Nagai
Tomoo Iijima
Original Assignee
Sony Chemicals Corp
North Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Chemicals Corp, North Corp filed Critical Sony Chemicals Corp
Publication of TW200621105A publication Critical patent/TW200621105A/zh
Application granted granted Critical
Publication of TWI371232B publication Critical patent/TWI371232B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B32B37/26—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer which influences the bonding during the lamination process, e.g. release layers or pressure equalising layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)
TW094137944A 2004-12-03 2005-10-28 Manufacturing method of multi-patterned-layer substrate TW200621105A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004352060A JP4761762B2 (ja) 2004-12-03 2004-12-03 多層配線基板の製造方法

Publications (2)

Publication Number Publication Date
TW200621105A true TW200621105A (en) 2006-06-16
TWI371232B TWI371232B (zh) 2012-08-21

Family

ID=36564868

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094137944A TW200621105A (en) 2004-12-03 2005-10-28 Manufacturing method of multi-patterned-layer substrate

Country Status (7)

Country Link
US (1) US8112881B2 (zh)
EP (1) EP1821588A4 (zh)
JP (1) JP4761762B2 (zh)
KR (1) KR101168879B1 (zh)
CN (1) CN101288349B (zh)
TW (1) TW200621105A (zh)
WO (1) WO2006059428A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI572261B (zh) * 2014-10-29 2017-02-21 健鼎科技股份有限公司 線路結構及線路結構的製作方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2213148A4 (en) 2007-10-10 2011-09-07 Tessera Inc ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED
CN101626660B (zh) * 2008-07-11 2012-08-29 惠阳科惠工业科技有限公司 结构不对称多层板铜面相靠压合工艺
WO2011037138A1 (ja) * 2009-09-25 2011-03-31 住友化学株式会社 金属箔積層体の製造方法
KR101089986B1 (ko) * 2009-12-24 2011-12-05 삼성전기주식회사 캐리어기판, 그의 제조방법, 이를 이용한 인쇄회로기판 및 그의 제조방법
KR101048597B1 (ko) * 2010-05-25 2011-07-12 주식회사 코리아써키트 범프가 형성된 인쇄회로기판의 제조방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821765B2 (ja) * 1986-11-13 1996-03-04 ジヨンストン，ジエイムズ・エイ 印刷回路板を製造する方法および装置
US5256474A (en) 1986-11-13 1993-10-26 Johnston James A Method of and apparatus for manufacturing printed circuit boards
JP2556897B2 (ja) * 1989-02-23 1996-11-27 ファナック株式会社 多層プリント配線板の外層材及び製造方法
JPH0946041A (ja) * 1995-07-26 1997-02-14 Toshiba Corp 印刷配線板の製造方法
JP3633136B2 (ja) 1996-09-18 2005-03-30 株式会社東芝 印刷配線基板
JP3428480B2 (ja) 1998-12-28 2003-07-22 新神戸電機株式会社 内層回路入り多層金属箔張り積層板の製造法
CN1371240A (zh) * 2001-02-23 2002-09-25 华泰电子股份有限公司 多层式高密度基板的制造方法
JP2003008200A (ja) 2001-06-22 2003-01-10 Matsushita Electric Ind Co Ltd 配線基板とその製造方法
JP3526838B2 (ja) 2001-10-22 2004-05-17 株式会社ノース 銅膜又は銅系膜に対する選択的エッチング方法と、選択的エッチング装置。
JP4045143B2 (ja) * 2002-02-18 2008-02-13 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線膜間接続用部材の製造方法及び多層配線基板の製造方法
JP3952862B2 (ja) 2002-05-30 2007-08-01 新神戸電機株式会社 内層回路入り金属箔張り積層板の製造法
JP4242623B2 (ja) * 2002-09-18 2009-03-25 北川精機株式会社 配線回路基板の製造方法
JP2004221310A (ja) * 2003-01-15 2004-08-05 Daiwa Kogyo:Kk 配線基板部材及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI572261B (zh) * 2014-10-29 2017-02-21 健鼎科技股份有限公司 線路結構及線路結構的製作方法

Also Published As

Publication number Publication date
JP2006165133A (ja) 2006-06-22
EP1821588A4 (en) 2009-11-11
US20080110018A1 (en) 2008-05-15
CN101288349B (zh) 2010-06-09
JP4761762B2 (ja) 2011-08-31
CN101288349A (zh) 2008-10-15
TWI371232B (zh) 2012-08-21
WO2006059428A1 (ja) 2006-06-08
US8112881B2 (en) 2012-02-14
EP1821588A1 (en) 2007-08-22
KR20070094896A (ko) 2007-09-27
KR101168879B1 (ko) 2012-07-26

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees