WO2008126661A1 - 多層セラミック基板およびその製造方法 - Google Patents

多層セラミック基板およびその製造方法 Download PDF

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Publication number
WO2008126661A1
WO2008126661A1 PCT/JP2008/055496 JP2008055496W WO2008126661A1 WO 2008126661 A1 WO2008126661 A1 WO 2008126661A1 JP 2008055496 W JP2008055496 W JP 2008055496W WO 2008126661 A1 WO2008126661 A1 WO 2008126661A1
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WIPO (PCT)
Prior art keywords
interlayer
ceramic substrate
layer
multilayer ceramic
base material
Prior art date
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PCT/JP2008/055496
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English (en)
French (fr)
Inventor
Yuichi Iida
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Murata Manufacturing Co., Ltd.
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Publication date
Application filed by Murata Manufacturing Co., Ltd. filed Critical Murata Manufacturing Co., Ltd.
Priority to JP2008538063A priority Critical patent/JP4821855B2/ja
Publication of WO2008126661A1 publication Critical patent/WO2008126661A1/ja
Priority to US12/265,984 priority patent/US7670672B2/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807Ceramic parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
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    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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    • H05K2203/308Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
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    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
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    • H05K3/46Manufacturing multilayer circuits
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    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
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  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

 いわゆる無収縮プロセスによりキャビティ付き多層セラミック基板を製造するとき、キャビティの底面の周縁部においてクラック等が発生しやすい。  底部(2)とキャビティ(4)を規定する壁部(5)との境界面(8)を挟んで、底部(2)側に基材層(6)を配置し、壁部(5)側に層間拘束層(7)を配置する。境界面(8)を挟んで配置される基材層(6)と層間拘束層(7)との間に、導体膜(9)を配置し、導体膜(9)の作用により、層間拘束層(7)の、基材層(6)に対する密着性を高め、層間拘束層(7)による収縮抑制効果を高める。
PCT/JP2008/055496 2007-04-11 2008-03-25 多層セラミック基板およびその製造方法 WO2008126661A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008538063A JP4821855B2 (ja) 2007-04-11 2008-03-25 多層セラミック基板およびその製造方法
US12/265,984 US7670672B2 (en) 2007-04-11 2008-11-06 Multilayer ceramic substrate and method for producing same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007103439 2007-04-11
JP2007-103439 2007-04-11

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/265,984 Continuation US7670672B2 (en) 2007-04-11 2008-11-06 Multilayer ceramic substrate and method for producing same

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WO2008126661A1 true WO2008126661A1 (ja) 2008-10-23

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010186881A (ja) * 2009-02-12 2010-08-26 Hitachi Metals Ltd 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法
JP2010186880A (ja) * 2009-02-12 2010-08-26 Hitachi Metals Ltd 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法
JP2011151307A (ja) * 2010-01-25 2011-08-04 Kyocera Corp 配線基板の製造方法
JP2012248798A (ja) * 2011-05-31 2012-12-13 Kyocera Corp 配線基板の製造方法および配線基板
JP2013051389A (ja) * 2011-08-01 2013-03-14 Ngk Spark Plug Co Ltd 回路基板、半導体パワーモジュール、製造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102027813A (zh) * 2008-05-15 2011-04-20 株式会社村田制作所 多层陶瓷基板及其制造方法
WO2010122822A1 (ja) * 2009-04-21 2010-10-28 株式会社村田製作所 多層セラミック基板の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135933A (ja) * 1999-11-04 2001-05-18 Murata Mfg Co Ltd 多層セラミック基板
JP2003273513A (ja) * 2002-03-14 2003-09-26 Murata Mfg Co Ltd キャビティ付き多層セラミック基板の製造方法およびキャビティ付き多層セラミック基板
JP2005116938A (ja) * 2003-10-10 2005-04-28 Ngk Spark Plug Co Ltd キャビティ付き多層セラミック基板およびその製造方法
JP2007067364A (ja) * 2004-09-03 2007-03-15 Murata Mfg Co Ltd チップ型電子部品を搭載したセラミック基板及びその製造方法

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