WO2008126661A1 - 多層セラミック基板およびその製造方法 - Google Patents
多層セラミック基板およびその製造方法 Download PDFInfo
- Publication number
- WO2008126661A1 WO2008126661A1 PCT/JP2008/055496 JP2008055496W WO2008126661A1 WO 2008126661 A1 WO2008126661 A1 WO 2008126661A1 JP 2008055496 W JP2008055496 W JP 2008055496W WO 2008126661 A1 WO2008126661 A1 WO 2008126661A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- interlayer
- ceramic substrate
- layer
- multilayer ceramic
- base material
- Prior art date
Links
- 239000000919 ceramic Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 title abstract 2
- 239000010410 layer Substances 0.000 abstract 7
- 239000011229 interlayer Substances 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 2
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/4807—Ceramic parts
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- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
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- H05K2203/063—Lamination of preperforated insulating layer
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Computer Hardware Design (AREA)
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- Ceramic Engineering (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
いわゆる無収縮プロセスによりキャビティ付き多層セラミック基板を製造するとき、キャビティの底面の周縁部においてクラック等が発生しやすい。 底部(2)とキャビティ(4)を規定する壁部(5)との境界面(8)を挟んで、底部(2)側に基材層(6)を配置し、壁部(5)側に層間拘束層(7)を配置する。境界面(8)を挟んで配置される基材層(6)と層間拘束層(7)との間に、導体膜(9)を配置し、導体膜(9)の作用により、層間拘束層(7)の、基材層(6)に対する密着性を高め、層間拘束層(7)による収縮抑制効果を高める。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008538063A JP4821855B2 (ja) | 2007-04-11 | 2008-03-25 | 多層セラミック基板およびその製造方法 |
US12/265,984 US7670672B2 (en) | 2007-04-11 | 2008-11-06 | Multilayer ceramic substrate and method for producing same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007103439 | 2007-04-11 | ||
JP2007-103439 | 2007-04-11 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/265,984 Continuation US7670672B2 (en) | 2007-04-11 | 2008-11-06 | Multilayer ceramic substrate and method for producing same |
Publications (1)
Publication Number | Publication Date |
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WO2008126661A1 true WO2008126661A1 (ja) | 2008-10-23 |
Family
ID=39863779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/055496 WO2008126661A1 (ja) | 2007-04-11 | 2008-03-25 | 多層セラミック基板およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7670672B2 (ja) |
JP (1) | JP4821855B2 (ja) |
WO (1) | WO2008126661A1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010186881A (ja) * | 2009-02-12 | 2010-08-26 | Hitachi Metals Ltd | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
JP2010186880A (ja) * | 2009-02-12 | 2010-08-26 | Hitachi Metals Ltd | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
JP2011151307A (ja) * | 2010-01-25 | 2011-08-04 | Kyocera Corp | 配線基板の製造方法 |
JP2012248798A (ja) * | 2011-05-31 | 2012-12-13 | Kyocera Corp | 配線基板の製造方法および配線基板 |
JP2013051389A (ja) * | 2011-08-01 | 2013-03-14 | Ngk Spark Plug Co Ltd | 回路基板、半導体パワーモジュール、製造方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102027813A (zh) * | 2008-05-15 | 2011-04-20 | 株式会社村田制作所 | 多层陶瓷基板及其制造方法 |
WO2010122822A1 (ja) * | 2009-04-21 | 2010-10-28 | 株式会社村田製作所 | 多層セラミック基板の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001135933A (ja) * | 1999-11-04 | 2001-05-18 | Murata Mfg Co Ltd | 多層セラミック基板 |
JP2003273513A (ja) * | 2002-03-14 | 2003-09-26 | Murata Mfg Co Ltd | キャビティ付き多層セラミック基板の製造方法およびキャビティ付き多層セラミック基板 |
JP2005116938A (ja) * | 2003-10-10 | 2005-04-28 | Ngk Spark Plug Co Ltd | キャビティ付き多層セラミック基板およびその製造方法 |
JP2007067364A (ja) * | 2004-09-03 | 2007-03-15 | Murata Mfg Co Ltd | チップ型電子部品を搭載したセラミック基板及びその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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DE69006609T2 (de) * | 1989-03-15 | 1994-06-30 | Ngk Insulators Ltd | Keramischer Deckel zum Verschliessen eines Halbleiterelements und Verfahren zum Verschliessen eines Halbleiterelements in einer keramischen Packung. |
US5702985A (en) * | 1992-06-26 | 1997-12-30 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method |
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- 2008-03-25 JP JP2008538063A patent/JP4821855B2/ja not_active Expired - Fee Related
- 2008-11-06 US US12/265,984 patent/US7670672B2/en not_active Expired - Fee Related
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010186881A (ja) * | 2009-02-12 | 2010-08-26 | Hitachi Metals Ltd | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
JP2010186880A (ja) * | 2009-02-12 | 2010-08-26 | Hitachi Metals Ltd | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
JP2011151307A (ja) * | 2010-01-25 | 2011-08-04 | Kyocera Corp | 配線基板の製造方法 |
JP2012248798A (ja) * | 2011-05-31 | 2012-12-13 | Kyocera Corp | 配線基板の製造方法および配線基板 |
JP2013051389A (ja) * | 2011-08-01 | 2013-03-14 | Ngk Spark Plug Co Ltd | 回路基板、半導体パワーモジュール、製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20090053532A1 (en) | 2009-02-26 |
JPWO2008126661A1 (ja) | 2010-07-22 |
US7670672B2 (en) | 2010-03-02 |
JP4821855B2 (ja) | 2011-11-24 |
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