CN101288349B - 多层布线基板的制作方法 - Google Patents

多层布线基板的制作方法 Download PDF

Info

Publication number
CN101288349B
CN101288349B CN200580041604XA CN200580041604A CN101288349B CN 101288349 B CN101288349 B CN 101288349B CN 200580041604X A CN200580041604X A CN 200580041604XA CN 200580041604 A CN200580041604 A CN 200580041604A CN 101288349 B CN101288349 B CN 101288349B
Authority
CN
China
Prior art keywords
copper foil
projection
corrosion resistant
resistant plate
mentioned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200580041604XA
Other languages
English (en)
Other versions
CN101288349A (zh
Inventor
清水和浩
八木正展
花村贤一郎
高安光之
永井清惠
饭岛朝雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
North Corp
Dexerials Corp
Invensas Corp
Original Assignee
Sony Chemical and Information Device Corp
Tessera Interconnect Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Chemical and Information Device Corp, Tessera Interconnect Materials Inc filed Critical Sony Chemical and Information Device Corp
Publication of CN101288349A publication Critical patent/CN101288349A/zh
Application granted granted Critical
Publication of CN101288349B publication Critical patent/CN101288349B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B32B37/26Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer which influences the bonding during the lamination process, e.g. release layers or pressure equalising layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00Electrical equipment
    • B32B2457/08PCBs, i.e. printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0384Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0733Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1461Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128Assembling formed circuit to base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49156Manufacturing circuit on or in base with selective destruction of conductive paths
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49163Manufacturing circuit on or in base with sintering of base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

本发明公开了一种多层布线基板的制作方法,具有:在形成了用于层间连接的凸块的基材上形成绝缘层的工序;在所述绝缘层上热压着铜箔的工序;和图案化所述铜箔的工序。所述铜箔热压着时,至少在所述不锈钢板和所述铜箔之间插入金属箔。此时,所插入的金属箔的表面被提供了防锈层或氧化膜。这样,可防止成型(铜箔贴合)后的产品粘连在不锈钢板上,能够制作出不会产生褶皱或凹凸不平且尺寸稳定性良好的多层布线基板。

Description

多层布线基板的制作方法
技术领域
本发明涉及由凸块进行层间连接的多层布线基板的制作方法,特别涉及在成型(铜箔贴合)时防止粘连的多层布线基板的制作方法。
背景技术
所谓组合式(built-up)多层布线基板的制作方法,即依次层叠绝缘层和导体层,对各导体层以规定的布线层图案进行图案化蚀刻时,也需要对各导体进行层间连接,在导体层上形成精细图案并实现高效的层间连接是一种重要技术。
传统的组合式多层布线基板的制作方法是:在铜箔上形成凸块,将其埋入绝缘膜内后,再在凸块上贴合上铜箔,从而与凸块连接(例如,参照专利文献1等。)。
专利文献1记载的发明是有关形成凸块的选择式蚀刻方法、选择式蚀刻装置。作为多层布线电路板的制作方法,公开了如下技术:在形成凸块所用的铜箔的一主面上形成蚀刻阻障层(etching barrier),在该蚀刻阻障层的主面上形成在导体回路的形成中所需要的铜箔,将在其上形成铜箔的同时又用于形成布线电路板的构件作为基底使用,通过适当加工这些构件来得到多层布线电路板。
在上述多层布线电路板制作技术中,首先,选择性地蚀刻用于形成所述布线电路板的构件上的铜箔,形成层间连接用的凸块,由绝缘层将凸块间填充,各凸块间彼此绝缘。其次,在绝缘层、凸块的上面形成在导体回路的形成中所用的铜箔。再次,通过选择地刻蚀上下两面的铜箔来形成布线膜。这样,就具有上下两面的布线膜,并且布线膜通过凸块连接就形成了多层布线基板。
【专利文献1】特开2003-129259号公报
然而,在制作上述利用凸块连接的多层布线基板时,需要在凸块的上面贴合铜箔,并夹持在不锈钢板间被施加压力,从而对上述铜箔进行热压着的成型工序。
该成型工序与通常的成型不同,需要施加较高的压力直到将上述凸块压溃到某种程度。这样,在上述铜箔仅仅与凸块的前端面相接触的状态下,为了确保结合力,要对凸块加压至压溃的程度,从而将铜箔和凸块一体化。而且,相对于在通常成型中设定的施加压力35~40kg/cm2,在上述成型中施加90~150kg/cm2,为接近前者3倍的压力。此外,不仅是压力,例如当在绝缘层上使用聚酰亚胺(polyimide,PI)树脂时,还施加335℃左右的高温。
在这样的高温、高压下进行成型,特别是在凸块的前端部分,成型后的多层布线基板和不锈钢板之间就会产生粘连,难以将产品(多层布线基板)揭下来,存在操作性差的问题。例如,操作者很难用手拆卸,而需要在间隙中插入楔子等一些器具。
此外,上述粘连产生时,将产品揭下来时要向产品施力,这是造成弯折、起褶、凹凸不平、变形、卷曲等的原因。特别是,由于上述粘连在凸块部分发生,在凸块密集的部分问题就更大。当产品上发生起褶或凹凸不平时,尺寸偏差变大,对于布线的图案化等在确保精度上就形成很大的障碍。
再者,在产品上,聚酰亚胺树脂和铜箔的贴合也可能会发生问题。例如,如上所述通过表面较硬的不锈钢板夹持进行成型时,由于贴合的铜箔被刚直地支撑着,不会随着突出形状的凸块变形,其结果是难以确保贴合的铜箔和聚酰亚胺树脂之间具有足够的贴合性,从而出现所谓的白化现象。
发明内容
针对现有技术存在的问题,本发明的目的在于提供一种制作方法,可防止成型(铜箔粘接)后的产品粘连不锈钢板,从而制作出不会产生褶皱、且尺寸稳定性良好的多层布线基板。此外,本发明的另一个目的还在于提供能确保所贴合的铜箔和聚酰亚胺树脂(绝缘层)的贴合性的多层布线基板的制作方法。
为实现上述目的,本发明的多层布线基板的制作方法,其特征在于,具有:在其上具有用于层间连接的凸块的基材上形成绝缘层的工序、通过不锈钢板夹持在上述绝缘层上热压着铜箔的工序、以及图案化所述铜箔的工序,上述铜箔热压着时,至少在上述不锈钢板和上述铜箔之间插入有金属箔。
本发明的制作方法,由于在成型时在不锈钢板和铜箔之间插入金属箔(例如铜箔),即使在高温、高压下进行成型,产品(多层布线基板)也不会粘连在不锈钢板上。从而,在成型后的拆卸时,不需要向产品施加多余的外力,从而不发生褶皱、凹凸不平、弯折、变形、卷曲等现象。此外,在拆卸时也不需要特别的器具,从而降低了操作难度。
另外,插入的金属箔起到了缓冲材料的作用,允许所贴合的铜箔发生变形。因此,上述铜箔能够随着若干凸出形状的凸块变形,在热压着时铜箔和绝缘层可相紧贴,从而确保了两者之间足够的贴合性。
根据本发明,能够防止成型(铜箔粘接)后的产品粘连在不锈钢板上,从而能够通过简易操作制作出不会产生褶皱或凹凸不平等且尺寸稳定性良好的多层布线基板。此外,还能够确保粘接的铜箔和绝缘层(聚酰亚胺树脂)的贴合性,避免了白化现象等。
附图说明
图1表示多层布线基板的制作工序的一个例子,第1段为表示层叠材料的剖面图;第2段为表示凸块形成工序的剖面图;第3段为表示绝缘层形成工序的剖面图;第4段为表示铜箔配置工序的剖面图;第5段为表示铜箔热压着工序的剖面图;第6段为表示铜箔图案化工序的剖面图。
图2为表示热压着工序的温度、压力、真空度的曲线图。
图3为表示热压着后的粘连状态的模式图。
图4为表示在本实施例中不锈钢板的叠加状态的剖面图。
具体实施方式
以下,参照附图详细说明本发明的多层布线基板及其制作方法。
在制作利用凸块连接的多层布线基板时,首先,如图1中第1段所示,准备好将用于层叠的材料:形成凸块的铜箔1、由Ni等形成的蚀刻阻障层2和形成第一布线层的铜箔3。碱性蚀刻液对上述的蚀刻阻障层2和铜箔1具有蚀刻选择性,因此在碱性蚀刻液蚀刻铜箔1时,蚀刻阻障层2可作为蚀刻中止层(etching stop)。此外,虽然铜箔3最终通过图案化形成布线层,但在此阶段,作为支撑体具有支撑通过蚀刻上述铜箔1和蚀刻阻障层2形成的凸块的功能。
因此,如图1中第2段所示,蚀刻上述铜箔1从而形成凸块4。对该铜箔1的蚀刻最好采用酸性蚀刻液和碱性蚀刻液的组合来进行。即,在铜箔1上形成呈遮罩的抵抗膜(图示省略)后,喷洒酸性蚀刻液(例如氯化二铜)。以这种方式对铜箔1蚀刻,该酸性蚀刻液的蚀刻深度要比铜箔1的厚度浅,且在不露出蚀刻阻障层2的范围内。其次,经过水洗(rinse)后,由碱性蚀刻液(例如氢氧化铵)蚀刻铜箔1的剩余部分。碱性蚀刻液几乎不会侵害到构成蚀刻阻障层2的Ni,因此,蚀刻阻障层2就起到了蚀刻中止的作用。另外,此时,碱性蚀刻液的pH值最好是在8.0以下。碱性蚀刻液为上述的pH值,便不会侵害到蚀刻阻障层2,从而能够较快地蚀刻铜箔1。此外,上述凸块4形成后,虽然上述蚀刻阻障层2也被去除,但仅蚀刻去除作为蚀刻阻障层2的Ni,位于其下的铜箔3不会被侵蚀。
其次,如图1中第3段所示,埋设上述凸块4间的形状来形成绝缘层5。绝缘层5,通过涂覆例如聚酰亚胺等的树脂材料,或通过热压着树脂膜形成。这里所使用的树脂材料,特别不需要考虑对电镀的贴合性、玻璃态转变点、线膨胀系数等因素,只需针对必要的特性做选择。此外,其厚度等也不受限制。
上述绝缘层5形成后,可通过例如研磨表面的方式使凸块4的前端面暴露出,如图1的第4段所示,在其上配置形成第二布线层的铜箔6,因此,如图1中的第5段所示,通过热压着将铜箔6贴合在绝缘层5上。
上述贴合(成型)通过所谓的热压着进行。对铜箔6的热压着时,在不锈钢板之间重复配置如图1中第4段或图1中第5段所示的层叠体,一并进行热压着。
加压时的压力在90~150kg/cm2之间,加压温度在335℃左右。图2是加压(热压着)时的温度曲线、压力曲线、真空度曲线的一个例子。在本实施例中,以200℃预热后,升温至335℃,在压力110kg/cm2下加压。真空度为1.3kPa。
如上所述通过不锈钢板夹持产品进行热压着时,温度或压力很高,且由于加压集中在凸块4的前端面上,所以会发生粘连不锈钢板的情形。图3表示产品的粘连状态。如图3所示,热压着后,与凸块4的形成位置所对应铜箔6粘连在不锈钢板ST上。在图3中,粘贴发生位置用点p表示。
这样,铜箔6在粘连状态下将产品从不锈钢板ST上剥离下来时,例如对图中A点上施力拉起,产品伸长,结果导致图中B部分上形成凹凸不平的现象。由于上述粘连是发生在在凸块4,从而在凸块4密集的部分就容易产生上述现象。此外,上述集中加压也给铜箔6和绝缘层5的贴合性带来不良影响。
因此,在本实施方式中,在不锈钢板21和铜箔6之间插入金属箔,以防止上述粘连发生。具体是,如图4所示,与如图1中第4段或图1中第5段所示的层叠体的两面相对应,即在热压着的铜箔6和不锈钢板21之间、以及作为支撑体的铜箔3和不锈钢板21之间分别插入铜箔22。此外,在最外部的不锈钢板21的外侧上,分别配置有缓冲材料23,经由这些缓冲材料23夹入到压机24之间。
另外,上述的层叠至少要在热压着的铜箔6和不锈钢板21之间插入铜箔22,例如,在将铜箔3进行防锈处理等情况下,可以省略铜箔3和不锈钢板21之间的铜箔22。
在此,上述铜箔22也不一定是铜箔,也可以采用任意金属构成的金属箔。但是,使用的铜箔22(金属箔)最好是其表面具有离型性,例如在其表面上形成离型层。
这种情况下的离型层可以是在铜箔22的表面上形成的防锈层。防锈层可以是Ni-Cr电镀层或Ni-Cr-Zn电镀层等,另外,也可以利用在铜箔22的表面上形成的氧化膜来作为上述的离型层。
上述铜箔6热压着后,如图1中第6段所示,表面和背面两面的导体层(铜箔6和铜箔3)以所要求的布线图案进行图案化并形成布线层。上述图案化可通过常规的微影(photolithography)技术和蚀刻技术进行。这样,能够获得两面布线基板,进而可以实现多层化。
在本实施方式的多层布线基板的制作方法中,由于在不锈钢板21和铜箔6之间插入的铜箔22的表面上形成的防锈层或氧化层等具有离型层的功能,能够防止成型(铜箔6贴合)后的产品粘连在不锈钢板21上,从而可以制作出不产生褶皱或凹凸不平、且尺寸稳定性良好的多层布线基板。此外,产品能够容易地从不锈钢板21上剥离下来,也不需要特别的器具,从而可使剥离操作简单化。此外,通过插入上述铜箔22,铜箔6的若干变形成为可能,可以改善铜箔6和绝缘层5的贴合性。
实施例
以下,基于实验结果说明应用本发明的具体实施例。
比较例
首先,通过传统的方法进行成型。即,通常使用不锈钢板将产品夹持,从而对铜箔6的热压着(成型)。制作的工序与实施方式1一样。其结果是,产生了产品的粘连,产品上存在褶皱或凹凸不平。此外,产品的剥离也很困难,必须插入楔子来剥离。在比较例中的尺寸稳定性(偏差)3σ为0.05%(N=50W),偏差值很大。
实施例1
在本实施例中,热压着时在铜箔6和不锈钢板21之间插入经过防锈处理的铜箔22。使用的铜箔22厚度为12μm,剖面为3μm。
另一方面,对铜箔3面对不锈钢板21的面做防锈处理。为了获得与绝缘层5上的聚酰亚胺树脂的贴合,铜箔3进行表面粗糙化处理。在上述表面粗糙化处理时,在与不锈钢板21的相对面上贴附保护膜,进行防锈处理。
本实施例中,在制成的产品上看不到因粘连产生的弯折、褶皱、变形、卷曲、凹凸不平等现象。此外,尺寸稳定性(偏差)3σ为0.037%(N=156W),与之前的比较例相比数值明显降低了。
实施例2
本实施例与实施例1一样插入铜箔,如图4所示,在产品的两侧,即铜箔6和不锈钢板21之间、及铜箔3和不锈钢板21之间插入防锈处理后铜箔22。使用的铜箔22厚度为12μm,剖面为5μm左右。
本实施例中,在制成的产品也看不到因粘连产生的弯折、褶皱、变形、卷曲、凹凸不平等。此外,尺寸稳定性(偏差)3σ为0.016%(N数=30W),与之前的比较例相比数值明显降低,约为实施例1的一半以下。

Claims (4)

1.一种多层布线基板的制作方法,其特征在于,具有:
在形成了用于层间连接的凸块的基材上形成绝缘层的工序;
由不锈钢板夹持将铜箔热压着到所述绝缘层上的工序;和
图案化所述铜箔的工序,
所述铜箔热压着时,至少在所述不锈钢板和所述铜箔之间插入金属箔。
2.根据权利要求1所述的多层布线基板的制作方法,其特征在于,在所述金属箔的表面上提供防锈层或氧化膜,所述金属箔为铜箔。
3.根据权利要求1所述的多层布线基板的制作方法,其特征在于,所述金属箔为铜箔。
4.根据权利要求1至3中任一所述的多层布线基板的制作方法,其特征在于,所述绝缘层由聚酰亚胺树脂构成。
CN200580041604XA 2004-12-03 2005-09-29 多层布线基板的制作方法 Expired - Fee Related CN101288349B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004352060A JP4761762B2 (ja) 2004-12-03 2004-12-03 多層配線基板の製造方法
JP352060/2004 2004-12-03
PCT/JP2005/017926 WO2006059428A1 (ja) 2004-12-03 2005-09-29 多層配線基板の製造方法

Publications (2)

Publication Number Publication Date
CN101288349A CN101288349A (zh) 2008-10-15
CN101288349B true CN101288349B (zh) 2010-06-09

Family

ID=36564868

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200580041604XA Expired - Fee Related CN101288349B (zh) 2004-12-03 2005-09-29 多层布线基板的制作方法

Country Status (7)

Country Link
US (1) US8112881B2 (zh)
EP (1) EP1821588A4 (zh)
JP (1) JP4761762B2 (zh)
KR (1) KR101168879B1 (zh)
CN (1) CN101288349B (zh)
TW (1) TW200621105A (zh)
WO (1) WO2006059428A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2213148A4 (en) 2007-10-10 2011-09-07 Tessera Inc ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED
CN101626660B (zh) * 2008-07-11 2012-08-29 惠阳科惠工业科技有限公司 结构不对称多层板铜面相靠压合工艺
US20120285617A1 (en) * 2009-09-25 2012-11-15 Sumitomo Chemical Company, Limited Method for producing metal foil laminate
KR101089986B1 (ko) * 2009-12-24 2011-12-05 삼성전기주식회사 캐리어기판, 그의 제조방법, 이를 이용한 인쇄회로기판 및 그의 제조방법
KR101048597B1 (ko) * 2010-05-25 2011-07-12 주식회사 코리아써키트 범프가 형성된 인쇄회로기판의 제조방법
TWI572261B (zh) * 2014-10-29 2017-02-21 健鼎科技股份有限公司 線路結構及線路結構的製作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1371240A (zh) * 2001-02-23 2002-09-25 华泰电子股份有限公司 多层式高密度基板的制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3751496T2 (de) * 1986-11-13 1996-05-02 James A Johnston Verfahren und vorrichtung zur herstellung von gedruckten leiterplatten.
US5256474A (en) 1986-11-13 1993-10-26 Johnston James A Method of and apparatus for manufacturing printed circuit boards
JP2556897B2 (ja) * 1989-02-23 1996-11-27 ファナック株式会社 多層プリント配線板の外層材及び製造方法
JPH0946041A (ja) * 1995-07-26 1997-02-14 Toshiba Corp 印刷配線板の製造方法
JP3633136B2 (ja) * 1996-09-18 2005-03-30 株式会社東芝 印刷配線基板
JP3428480B2 (ja) * 1998-12-28 2003-07-22 新神戸電機株式会社 内層回路入り多層金属箔張り積層板の製造法
JP2003008200A (ja) * 2001-06-22 2003-01-10 Matsushita Electric Ind Co Ltd 配線基板とその製造方法
JP3526838B2 (ja) 2001-10-22 2004-05-17 株式会社ノース 銅膜又は銅系膜に対する選択的エッチング方法と、選択的エッチング装置。
JP4045143B2 (ja) * 2002-02-18 2008-02-13 テセラ・インターコネクト・マテリアルズ,インコーポレイテッド 配線膜間接続用部材の製造方法及び多層配線基板の製造方法
JP3952862B2 (ja) * 2002-05-30 2007-08-01 新神戸電機株式会社 内層回路入り金属箔張り積層板の製造法
JP4242623B2 (ja) * 2002-09-18 2009-03-25 北川精機株式会社 配線回路基板の製造方法
JP2004221310A (ja) * 2003-01-15 2004-08-05 Daiwa Kogyo:Kk 配線基板部材及びその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1371240A (zh) * 2001-02-23 2002-09-25 华泰电子股份有限公司 多层式高密度基板的制造方法

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
JP特开2000-196238A 2000.07.14
JP特开2003-347728A 2003.12.05
JP特开2004-221310A 2004.08.05
JP特开平10-93242A 1998.04.10
JP特开平9-46041A 1997.02.14

Also Published As

Publication number Publication date
JP4761762B2 (ja) 2011-08-31
US20080110018A1 (en) 2008-05-15
EP1821588A1 (en) 2007-08-22
CN101288349A (zh) 2008-10-15
KR20070094896A (ko) 2007-09-27
US8112881B2 (en) 2012-02-14
TWI371232B (zh) 2012-08-21
TW200621105A (en) 2006-06-16
WO2006059428A1 (ja) 2006-06-08
EP1821588A4 (en) 2009-11-11
KR101168879B1 (ko) 2012-07-26
JP2006165133A (ja) 2006-06-22

Similar Documents

Publication Publication Date Title
CN101288349B (zh) 多层布线基板的制作方法
EP1180920A3 (en) Circuit board and method of manufacturing same
EP1272021A3 (en) Method for manufacturing metal foil laminated product and method of manufacturing wiring board
JPH06326438A (ja) 単層配線ユニットおよび多層回路配線板ならびにその製法
CN101084703B (zh) 多层布线基板及其制作方法
JP2006313932A (ja) 多層回路基板とその製造方法
JP3946114B2 (ja) 多層回路配線基板の製造方法
JP2002521809A (ja) 銅箔とセパレーター板の接合方法
JP2003068562A (ja) 積層型セラミック電子部品の製造方法
JP5594090B2 (ja) 木製部材の製造方法及び筐体の製造方法
JP5593625B2 (ja) 多層配線基板の製造方法
JP2691714B2 (ja) 多層配線板の製造方法
US20030121146A1 (en) Method for fabricating electrical connecting elements, and connecting element
JP2008172030A (ja) 多層回路基板の製造方法
JPH07221435A (ja) フレキシブルプリント基板
JPH06169147A (ja) 金属ベース回路基板及びその製造方法
JPH01286386A (ja) 回路基板の製法
JP4196125B2 (ja) 回路基板の製造方法
JP2006165132A (ja) 多層配線基板の製造方法
JPH0464451B2 (zh)
JPH0432556B2 (zh)
JP2015119078A (ja) プリント基板の製造方法及びそれに用いる原版
KR100802600B1 (ko) 동박을 갖는 기판 및 이의 제조 방법
JP2006295207A (ja) 回路基板の製造方法
JPH0465893A (ja) 複合回路基板の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100609

Termination date: 20140929

EXPY Termination of patent right or utility model