JP2011096903A - 半導体素子実装配線基板の製造方法 - Google Patents
半導体素子実装配線基板の製造方法 Download PDFInfo
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Abstract
【解決手段】半導体素子21を絶縁層23で被覆した半導体素子封止基板20Aを作製する一方で、これとは別工程で、再配線層を積層した再配線基板30Aを作製する。次に、半導体素子封止基板20Aと再配線基板30Aとを、半導体素子21の電極端子22と最外層の再配線層上の対応する導電性バンプ35とが対向するよう位置合わせして積層し、電極端子22と導電性バンプ35とを接続する。
【選択図】図5
Description
図1は本発明の第1の実施形態に係る半導体素子実装配線基板(パッケージ)の構成を断面図の形態で示したものである。
図7は、本発明の第2の実施形態に係る半導体素子実装配線基板(パッケージ)の製造工程(一部)を断面図の形態で示したものである。
図8は、本発明の第3の実施形態に係る半導体素子実装配線基板(パッケージ)の製造工程(一部)を断面図の形態で示したものである。
20,20a,20b,20c…半導体素子(チップ)封止基板、
21…半導体素子(チップ)、
22…電極パッド(端子)、
23,24…樹脂層(絶縁層)、
25…導体ビア、
26…パッド、
30,30b,30c…再配線基板、
31(31P)…配線層(パッド)、
32,34…樹脂層(絶縁層)、
33(33P)…再配線層(パッド)、
35,38…導電性バンプ、
36…ソルダレジスト層(保護膜/絶縁層)、
37…はんだボール(外部接続端子)、
41…銅板(金属板)、
42…テープ(一時的な支持基材)、
50(52)…仮基板(銅箔)、
VH…ビアホール。
Claims (6)
- 所要の大きさの開口部が形成された金属板を用意し、該金属板を、片面が粘着面とされた支持基材の該粘着面に貼り付ける工程と、
前記支持基材上の、前記金属板の開口部に対応する部分に、半導体素子をフェイスアップの態様で搭載する工程と、
前記支持基材上の前記金属板及び前記半導体素子を被覆するように絶縁層を形成して、半導体素子封止基板を作製する工程と、
仮基板の少なくとも一方の面上に、再配線層を絶縁層を介在させて所要の層数となるまで積層し、最外層の再配線層上に所要個数の導電性バンプを形成して、再配線基板を作製する工程と、
前記半導体素子封止基板と前記再配線基板とを、前記半導体素子の電極端子と前記再配線層上の対応する導電性バンプとが対向するよう位置合わせして積層し、前記電極端子と前記導電性バンプとを接続する工程と、
以上の工程により作製された構造体から、前記支持基材及び前記仮基板を除去する工程と、を含むことを特徴とする半導体素子実装配線基板の製造方法。 - 前記金属板の前記支持基材に貼り付けられる側と反対側の面上の所定の箇所に、パッドを形成する工程を含み、
前記半導体素子封止基板を作製する工程において、前記金属板上の前記パッドも被覆するように前記絶縁層を形成するとともに、
前記再配線基板を作製する工程において、前記最外層の再配線層上に前記導電性バンプを形成する際に、当該再配線層上の、前記半導体素子封止基板における前記パッドの位置に対応する部分に更なる導電性バンプを形成することを特徴とする請求項1に記載の半導体素子実装配線基板の製造方法。 - 前記パッドは、外部接続用として設けられ、他の電子部品の外部接続端子が接合されるよう形成されていることを特徴とする請求項2に記載の半導体素子実装配線基板の製造方法。
- 前記半導体素子封止基板を作製する工程において、前記支持基材上の前記金属板及び前記半導体素子を被覆するように絶縁層を形成した後、該絶縁層の所定の箇所を開口し、前記半導体素子の電極端子に接続される導体ビアを形成する工程を含み、
前記再配線基板を作製する工程に代えて、仮基板の少なくとも一方の面上に、再配線層を絶縁層を介在させて所要の層数となるまで積層し、最外層の再配線層を露出させた再配線基板を作製する工程を含み、
前記半導体素子封止基板と前記再配線基板とを接続する工程に代えて、前記半導体素子封止基板と前記再配線基板とを、前記半導体素子の電極端子上に設けられた前記導体ビアと前記最外層の再配線層上の対応するパッドとが対向するよう位置合わせして積層し、前記導体ビアと前記パッドとを接続する工程を含むことを特徴とする請求項1に記載の半導体素子実装配線基板の製造方法。 - 前記支持基材及び前記仮基板を除去する工程の後に、前記半導体素子が露出している側と反対側の面に露出する再配線層及び絶縁層上に、当該再配線層のパッドの部分を露出させて保護膜を形成する工程を含むことを特徴とする請求項1に記載の半導体素子実装配線基板の製造方法。
- 前記保護膜を形成する工程の後に、前記金属板を選択除去する工程を含むことを特徴とする請求項5に記載の半導体素子実装配線基板の製造方法。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013038361A (ja) * | 2011-08-11 | 2013-02-21 | Fujikura Ltd | 部品内蔵プリント基板及びその製造方法 |
JP2013165157A (ja) * | 2012-02-10 | 2013-08-22 | Denso Corp | 半導体装置の製造方法 |
WO2013140588A1 (ja) * | 2012-03-23 | 2013-09-26 | 住友ベークライト株式会社 | プリント配線基板の製造方法、プリント配線基板および半導体装置 |
JP2014195076A (ja) * | 2013-03-28 | 2014-10-09 | Intel Corp | パッケージ、方法、及び装置 |
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