ATE429032T1 - Direktaufbauschicht auf einer verkapselten chipverpackung - Google Patents

Direktaufbauschicht auf einer verkapselten chipverpackung

Info

Publication number
ATE429032T1
ATE429032T1 AT01962043T AT01962043T ATE429032T1 AT E429032 T1 ATE429032 T1 AT E429032T1 AT 01962043 T AT01962043 T AT 01962043T AT 01962043 T AT01962043 T AT 01962043T AT E429032 T1 ATE429032 T1 AT E429032T1
Authority
AT
Austria
Prior art keywords
microelectronic die
active surface
chip packaging
build layer
encapsulation material
Prior art date
Application number
AT01962043T
Other languages
English (en)
Inventor
Xiao-Chun Mu
Qing Ma
Harry Fujimoto
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE429032T1 publication Critical patent/ATE429032T1/de

Links

Classifications

    • H10W74/019
    • H10W40/778
    • H10W70/09
    • H10W70/614
    • H10W72/0198
    • H10W74/01
    • H10W74/014
    • H10W74/129
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H10W70/099
    • H10W70/60
    • H10W70/655
    • H10W72/07251
    • H10W72/073
    • H10W72/20
    • H10W72/241
    • H10W72/29
    • H10W72/874
    • H10W72/9413
    • H10W90/734
    • H10W90/736

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Micromachines (AREA)
  • Die Bonding (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Chemical Treatment Of Metals (AREA)
  • Air Bags (AREA)
AT01962043T 2000-08-16 2001-08-10 Direktaufbauschicht auf einer verkapselten chipverpackung ATE429032T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US64096100A 2000-08-16 2000-08-16
PCT/US2001/025060 WO2002015266A2 (en) 2000-08-16 2001-08-10 Direct build-up layer on an encapsulated die package

Publications (1)

Publication Number Publication Date
ATE429032T1 true ATE429032T1 (de) 2009-05-15

Family

ID=24570376

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01962043T ATE429032T1 (de) 2000-08-16 2001-08-10 Direktaufbauschicht auf einer verkapselten chipverpackung

Country Status (7)

Country Link
EP (1) EP1354351B1 (de)
CN (1) CN100426492C (de)
AT (1) ATE429032T1 (de)
AU (1) AU2001283257A1 (de)
DE (1) DE60138416D1 (de)
MY (1) MY141327A (de)
WO (1) WO2002015266A2 (de)

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CN100389494C (zh) * 2002-05-23 2008-05-21 威盛电子股份有限公司 集成电路封装的制作工艺
DE10320579A1 (de) * 2003-05-07 2004-08-26 Infineon Technologies Ag Halbleiterwafer, Nutzen und elektronisches Bauteil mit gestapelten Halbleiterchips, sowie Verfahren zur Herstellung derselben
FR2857157B1 (fr) * 2003-07-01 2005-09-23 3D Plus Sa Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant
DE10343053A1 (de) * 2003-09-16 2005-04-07 Siemens Ag Elektronisches Bauelement und Anordnung mit einem elektronischen Bauelement
US7338836B2 (en) * 2003-11-05 2008-03-04 California Institute Of Technology Method for integrating pre-fabricated chip structures into functional electronic systems
DE102004022884B4 (de) 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
JP4343044B2 (ja) 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
CN100578771C (zh) * 2006-11-22 2010-01-06 南亚电路板股份有限公司 嵌入式芯片封装结构
JP5193898B2 (ja) 2009-02-12 2013-05-08 新光電気工業株式会社 半導体装置及び電子装置
JP5535494B2 (ja) 2009-02-23 2014-07-02 新光電気工業株式会社 半導体装置
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
FR2943176B1 (fr) * 2009-03-10 2011-08-05 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
JP5106460B2 (ja) 2009-03-26 2012-12-26 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
JP5330065B2 (ja) 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
FR2946795B1 (fr) * 2009-06-12 2011-07-22 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
JP5296636B2 (ja) * 2009-08-21 2013-09-25 新光電気工業株式会社 半導体パッケージの製造方法
JP5541618B2 (ja) 2009-09-01 2014-07-09 新光電気工業株式会社 半導体パッケージの製造方法
JP5325736B2 (ja) 2009-10-06 2013-10-23 新光電気工業株式会社 半導体装置及びその製造方法
JP5249173B2 (ja) 2009-10-30 2013-07-31 新光電気工業株式会社 半導体素子実装配線基板及びその製造方法
JP5543754B2 (ja) 2009-11-04 2014-07-09 新光電気工業株式会社 半導体パッケージ及びその製造方法
JP5581519B2 (ja) 2009-12-04 2014-09-03 新光電気工業株式会社 半導体パッケージとその製造方法
EP2330618A1 (de) 2009-12-04 2011-06-08 STMicroelectronics (Grenoble 2) SAS Wiederhergestellte Wafereinheit
JP5584011B2 (ja) 2010-05-10 2014-09-03 新光電気工業株式会社 半導体パッケージの製造方法
JP5826532B2 (ja) 2010-07-15 2015-12-02 新光電気工業株式会社 半導体装置及びその製造方法
US9064883B2 (en) 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
US9082825B2 (en) 2011-10-19 2015-07-14 Panasonic Corporation Manufacturing method for semiconductor package, semiconductor package, and semiconductor device
KR101332916B1 (ko) * 2011-12-29 2013-11-26 주식회사 네패스 반도체 패키지 및 그 제조 방법
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US8912670B2 (en) * 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
CN107256848A (zh) * 2017-05-25 2017-10-17 日月光封装测试(上海)有限公司 半导体封装件及其制造方法
WO2019103676A1 (en) * 2017-11-24 2019-05-31 Fingerprint Cards Ab Ultra-thin fingerprint sensor component and manufacturing method
CN112582287A (zh) * 2019-09-30 2021-03-30 中芯长电半导体(江阴)有限公司 晶圆级芯片封装结构及封装方法
CN115148615B (zh) * 2022-09-05 2022-11-15 长电集成电路(绍兴)有限公司 芯片封装结构的修复方法

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US5291066A (en) * 1991-11-14 1994-03-01 General Electric Company Moisture-proof electrical circuit high density interconnect module and method for making same
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US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers

Also Published As

Publication number Publication date
EP1354351A2 (de) 2003-10-22
AU2001283257A1 (en) 2002-02-25
EP1354351B1 (de) 2009-04-15
HK1055844A1 (en) 2004-01-21
MY141327A (en) 2010-04-16
CN1535479A (zh) 2004-10-06
WO2002015266A3 (en) 2003-08-14
WO2002015266A2 (en) 2002-02-21
CN100426492C (zh) 2008-10-15
DE60138416D1 (de) 2009-05-28

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Legal Events

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