FR2599893B1 - Procede de montage d'un module electronique sur un substrat et carte a circuit integre - Google Patents

Procede de montage d'un module electronique sur un substrat et carte a circuit integre

Info

Publication number
FR2599893B1
FR2599893B1 FR8707247A FR8707247A FR2599893B1 FR 2599893 B1 FR2599893 B1 FR 2599893B1 FR 8707247 A FR8707247 A FR 8707247A FR 8707247 A FR8707247 A FR 8707247A FR 2599893 B1 FR2599893 B1 FR 2599893B1
Authority
FR
France
Prior art keywords
substrate
mounting
integrated circuit
electronic module
circuit card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8707247A
Other languages
English (en)
Other versions
FR2599893A1 (fr
Inventor
Shindo Toshikazu Yosh Masahiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP61119944A external-priority patent/JPS63260041A/ja
Priority claimed from JP61227395A external-priority patent/JPS6381095A/ja
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Publication of FR2599893A1 publication Critical patent/FR2599893A1/fr
Application granted granted Critical
Publication of FR2599893B1 publication Critical patent/FR2599893B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
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    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
FR8707247A 1986-05-23 1987-05-22 Procede de montage d'un module electronique sur un substrat et carte a circuit integre Expired - Fee Related FR2599893B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11994286 1986-05-23
JP61119944A JPS63260041A (ja) 1986-05-23 1986-05-23 集積回路装置の実装方法
JP61227395A JPS6381095A (ja) 1986-09-25 1986-09-25 Icチツプの実装方法

Publications (2)

Publication Number Publication Date
FR2599893A1 FR2599893A1 (fr) 1987-12-11
FR2599893B1 true FR2599893B1 (fr) 1996-08-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR8707247A Expired - Fee Related FR2599893B1 (fr) 1986-05-23 1987-05-22 Procede de montage d'un module electronique sur un substrat et carte a circuit integre

Country Status (2)

Country Link
US (1) US5048179A (fr)
FR (1) FR2599893B1 (fr)

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DE3924439A1 (de) * 1989-07-24 1991-04-18 Edgar Schneider Traegerelement mit wenigstens einem integrierten schaltkreis, insbesondere zum einbau in chip-karten, sowie verfahren zur herstellung dieser traegerelemente
US5531020A (en) * 1989-11-14 1996-07-02 Poly Flex Circuits, Inc. Method of making subsurface electronic circuits
JPH03211757A (ja) * 1989-12-21 1991-09-17 General Electric Co <Ge> 気密封じの物体
JP3280394B2 (ja) * 1990-04-05 2002-05-13 ロックヒード マーティン コーポレーション 電子装置
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
FR2674682A1 (fr) * 1991-03-26 1992-10-02 Thomson Csf Module hybride et procede de realisation.
US5278442A (en) * 1991-07-15 1994-01-11 Prinz Fritz B Electronic packages and smart structures formed by thermal spray deposition
DE9113601U1 (fr) * 1991-10-31 1993-03-04 Schneider, Edgar, 8057 Guenzenhausen, De
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
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