FR2553576B1 - Dispositif a circuits integres a semi-conducteurs et procede de fabrication d'un tel dispositif - Google Patents

Dispositif a circuits integres a semi-conducteurs et procede de fabrication d'un tel dispositif

Info

Publication number
FR2553576B1
FR2553576B1 FR8414335A FR8414335A FR2553576B1 FR 2553576 B1 FR2553576 B1 FR 2553576B1 FR 8414335 A FR8414335 A FR 8414335A FR 8414335 A FR8414335 A FR 8414335A FR 2553576 B1 FR2553576 B1 FR 2553576B1
Authority
FR
France
Prior art keywords
manufacturing
integrated circuit
semiconductor integrated
circuit device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8414335A
Other languages
English (en)
Other versions
FR2553576A1 (fr
Inventor
Daisuke Okada
Akihisa Uchida
Toshihiko Takakura
Shinji Nakashima
Nobuhiko Ohno
Katsumi Ogiue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of FR2553576A1 publication Critical patent/FR2553576A1/fr
Application granted granted Critical
Publication of FR2553576B1 publication Critical patent/FR2553576B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
FR8414335A 1983-10-14 1984-09-19 Dispositif a circuits integres a semi-conducteurs et procede de fabrication d'un tel dispositif Expired FR2553576B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58190779A JPS6083346A (ja) 1983-10-14 1983-10-14 半導体集積回路装置

Publications (2)

Publication Number Publication Date
FR2553576A1 FR2553576A1 (fr) 1985-04-19
FR2553576B1 true FR2553576B1 (fr) 1986-06-27

Family

ID=16263588

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8414335A Expired FR2553576B1 (fr) 1983-10-14 1984-09-19 Dispositif a circuits integres a semi-conducteurs et procede de fabrication d'un tel dispositif

Country Status (7)

Country Link
US (2) US4700464A (fr)
JP (1) JPS6083346A (fr)
KR (1) KR920006851B1 (fr)
DE (1) DE3437512C2 (fr)
FR (1) FR2553576B1 (fr)
GB (1) GB2148591B (fr)
IT (1) IT1176957B (fr)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
JPH07105436B2 (ja) * 1986-07-18 1995-11-13 株式会社東芝 半導体装置の製造方法
GB2200794A (en) * 1986-11-19 1988-08-10 Plessey Co Plc Semiconductor device manufacture
JPS63236343A (ja) * 1987-03-25 1988-10-03 Toshiba Corp 半導体装置及びその製造方法
US5189501A (en) * 1988-10-05 1993-02-23 Sharp Kabushiki Kaisha Isolator for electrically isolating semiconductor devices in an integrated circuit
US5059550A (en) * 1988-10-25 1991-10-22 Sharp Kabushiki Kaisha Method of forming an element isolating portion in a semiconductor device
US5148257A (en) * 1989-12-20 1992-09-15 Nec Corporation Semiconductor device having u-groove
US5250836A (en) * 1989-12-20 1993-10-05 Fujitsu Limited Semiconductor device having silicon-on-insulator structure
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
KR920020676A (ko) * 1991-04-09 1992-11-21 김광호 반도체 장치의 소자분리 방법
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5644157A (en) * 1992-12-25 1997-07-01 Nippondenso Co., Ltd. High withstand voltage type semiconductor device having an isolation region
JPH07254640A (ja) * 1993-12-30 1995-10-03 Texas Instr Inc <Ti> スタック・トレンチ・コンデンサ形成工程におけるトレンチ分離構造形成方法
KR0131723B1 (ko) * 1994-06-08 1998-04-14 김주용 반도체소자 및 그 제조방법
WO1996002070A2 (fr) * 1994-07-12 1996-01-25 National Semiconductor Corporation Procede de formation d'un circuit integre comprenant une tranchee d'isolation et une couche-barriere d'oxygene
JP3304621B2 (ja) * 1994-07-29 2002-07-22 三菱電機株式会社 半導体装置の製造方法
JP3180599B2 (ja) * 1995-01-24 2001-06-25 日本電気株式会社 半導体装置およびその製造方法
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
FR2761810A1 (fr) * 1997-02-28 1998-10-09 Int Rectifier Corp Dispositif a semi-conducteur et son procede de fabrication
SE512813C2 (sv) * 1997-05-23 2000-05-15 Ericsson Telefon Ab L M Förfarande för framställning av en integrerad krets innefattande en dislokationsfri kollektorplugg förbunden med en begravd kollektor i en halvledarkomponent, som är omgiven av en dislokationsfri trench samt integrerad krets framställd enligt förfarandet
KR100492790B1 (ko) * 1997-06-28 2005-08-24 주식회사 하이닉스반도체 반도체소자의소자분리절연막형성방법
US6022788A (en) * 1997-12-23 2000-02-08 Stmicroelectronics, Inc. Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby
KR100459332B1 (ko) * 1997-12-30 2005-04-06 주식회사 하이닉스반도체 반도체소자의금속배선형성방법
US6140208A (en) * 1999-02-05 2000-10-31 International Business Machines Corporation Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications
US6335247B1 (en) * 2000-06-19 2002-01-01 Infineon Technologies Ag Integrated circuit vertical trench device and method of forming thereof
EP1220312A1 (fr) * 2000-12-29 2002-07-03 STMicroelectronics S.r.l. Procédé d'intégration d'un dispositif semiconducteur dans un substrat du type SOI comprenant au moins un puits diélectriquement isolé

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US104102A (en) * 1870-06-14 Improvement in elevating apparatus
US3969168A (en) * 1974-02-28 1976-07-13 Motorola, Inc. Method for filling grooves and moats used on semiconductor devices
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
JPS5642367A (en) * 1979-09-14 1981-04-20 Toshiba Corp Manufacture of bipolar integrated circuit
UST104102I4 (en) 1980-03-24 1984-04-03 Polysilicon-base self-aligned bipolar transistor process and structure
US4353086A (en) * 1980-05-07 1982-10-05 Bell Telephone Laboratories, Incorporated Silicon integrated circuits
DE3174468D1 (en) * 1980-09-17 1986-05-28 Hitachi Ltd Semiconductor device and method of manufacturing the same
JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
JPS57204144A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Insulating and isolating method for semiconductor integrated circuit
CA1188418A (fr) * 1982-01-04 1985-06-04 Jay A. Shideler Procede d'isolement par oxyde pour memoires vives ou memoires mortes programmables standard avec memoire vive comprenant un transistor pnp lateral
US4661832A (en) * 1982-06-30 1987-04-28 International Business Machines Corporation Total dielectric isolation for integrated circuits
JPS5961045A (ja) * 1982-09-29 1984-04-07 Fujitsu Ltd 半導体装置の製造方法
JPS5992546A (ja) * 1982-11-19 1984-05-28 Hitachi Ltd バイポ−ラ集積回路装置
US4538343A (en) * 1984-06-15 1985-09-03 Texas Instruments Incorporated Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
US4528047A (en) * 1984-06-25 1985-07-09 International Business Machines Corporation Method for forming a void free isolation structure utilizing etch and refill techniques
US4663832A (en) * 1984-06-29 1987-05-12 International Business Machines Corporation Method for improving the planarity and passivation in a semiconductor isolation trench arrangement

Also Published As

Publication number Publication date
GB2148591B (en) 1987-07-01
IT8423138A0 (it) 1984-10-12
FR2553576A1 (fr) 1985-04-19
US4700464A (en) 1987-10-20
GB8416885D0 (en) 1984-08-08
DE3437512C2 (de) 1996-01-25
US4907063A (en) 1990-03-06
KR920006851B1 (ko) 1992-08-20
GB2148591A (en) 1985-05-30
JPS6083346A (ja) 1985-05-11
KR850003068A (ko) 1985-05-28
DE3437512A1 (de) 1985-04-25
IT1176957B (it) 1987-08-26

Similar Documents

Publication Publication Date Title
FR2553576B1 (fr) Dispositif a circuits integres a semi-conducteurs et procede de fabrication d&#39;un tel dispositif
FR2524201B1 (fr) Procede de fabrication d&#39;un dispositif semi-conducteur du type multicouche
FR2499749B1 (fr) Dispositif de memoire a semiconducteurs et procede de fabrication d&#39;un tel dispositif
FR2532784B1 (fr) Dispositif a circuits integres a semiconducteurs comprenant une gorge profonde remplie d&#39;un materiau isolant et procede de fabrication d&#39;un tel dispositif
FR2555364B1 (fr) Procede de fabrication de connexions d&#39;un dispositif a circuits integres a semi-conducteurs comportant en particulier un mitset
DE3379621D1 (en) Semiconductor integrated circuit device and a method for manufacturing the same
FR2614168B1 (fr) Dispositif a circuits electroniques multicouches et son procede de fabrication
FR2494021B1 (fr) Dispositif a circuits integres a semiconducteurs
GB2163901B (en) A semiconductor integrated circuit device and a process for manufacturing such a device
DE3571535D1 (en) Integrated circuit semiconductor device formed on a wafer
FR2483127B1 (fr) Procede de fabrication d&#39;un dispositif semi-conducteur
KR100199259B1 (en) Fabrication method of semiconductor integrated circuit device
FR2550012B1 (fr) Dispositif a circuits integres a semi-conducteurs
FR2604562B1 (fr) Dispositif semi-conducteur silicium-sur-isolant et procede de fabrication
FR2525388B1 (fr) Procede de fabrication d&#39;un circuit integre planaire
FR2675311B1 (fr) Dispositif semi-conducteur du type bicmos pour circuits integres et son procede de fabrication.
FR2516723B1 (fr) Dispositif a circuits integres a semi-conducteurs
FR2531812B1 (fr) Dispositif a circuits integres a semiconducteurs du type &#34; bi-cmos-ic &#34; et son procede de fabrication
FR2299725A1 (fr) Composant de circuit integre et procede de fabrication d&#39;un tel composant
FR2491679B1 (fr) Methode d&#39;isolation d&#39;un dispositif a semi-conducteurs et dispositif ou circuit integre obtenu
FR2513440B1 (fr) Dispositif a circuits integres a semi-conducteurs
FR2589279B1 (fr) Dispositif semi-conducteur electronique pour proteger des circuits integres contre des decharges electrostatiques et procede pour le fabriquer
FR2625037B1 (fr) Procede de fabrication d&#39;un circuit integre a base de silicium
FR2589278B1 (fr) Dispositif electronique pour proteger des circuits integres des charges electrostatiques et procede pour le fabriquer
FR2582446B1 (fr) Dispositif semi-conducteur photosensible et procede de fabrication d&#39;un tel procede

Legal Events

Date Code Title Description
ST Notification of lapse
ST Notification of lapse