KR920020676A - 반도체 장치의 소자분리 방법 - Google Patents

반도체 장치의 소자분리 방법 Download PDF

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Publication number
KR920020676A
KR920020676A KR1019910005647A KR910005647A KR920020676A KR 920020676 A KR920020676 A KR 920020676A KR 1019910005647 A KR1019910005647 A KR 1019910005647A KR 910005647 A KR910005647 A KR 910005647A KR 920020676 A KR920020676 A KR 920020676A
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South Korea
Prior art keywords
insulating film
conductive layer
trench
substrate
exposed
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KR1019910005647A
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English (en)
Inventor
조현진
양수길
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910005647A priority Critical patent/KR920020676A/ko
Priority to FR9107131A priority patent/FR2675310A1/fr
Priority to ITMI911743A priority patent/IT1248545B/it
Priority to DE4121129A priority patent/DE4121129A1/de
Priority to GB9114158A priority patent/GB2254731A/en
Priority to JP3167076A priority patent/JPH0689884A/ja
Publication of KR920020676A publication Critical patent/KR920020676A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

반도체 장치의 소자분리 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 단면도.
제2도(a)-(i)는 본 발명에 따른 제조 공정도.

Claims (11)

  1. 반도체 장치의 소자분리 방법에 있어서, 제1도전형의 반도체 기판(10)상면에 제1절연막(12)과 제2절연막(14)과 제1도전층(16)을 순차적으로 형성하는 제1공정과, 소정의 분리영역에 해당하는 상기 제1도전층(16)을 선택적으로 제거한 후 잔류하는 상기 제1도전층을 열산화시키는 제2공정과, 상기 열산화된 제1도전층(20)을 마스크로 하여 상기 제2절연막(14)과 제1절연막(12)을 기판의 표면이 노출될 때까지 식각하는 제3공정과, 상기 제3공정에 의해 노출된 기판(10)영역을 식각하여 트렌치(22)를 형성하는 제4공정과, 상기 트렌치(22)의 내벽에 버퍼절연막(24)을 형성한 후 상기 기판(10)표면에 제2도전층(26)을 형성하는 제5공정과, 상기 제2도전층(26)을 연산화시킨 후 상기 기판(10)전면에 제3절연막(30)을 도포하여 상기 트렌치(22) 내부를 채우는 제6공정과, 상기 제2절연막(14)이 충분히 노출될 때까지 에치백 공저아을 실시한 후 노출된 상기 제2절연막(14)을 제거하는 제7공정이 연속적으로 이루어짐을 특징으로 하는 반도체 장치의 소자분리 방법.
  2. 제1항에 있어서, 상기 제2공정에서 소정의 분리영역에 해당하는 상기 제1도전층(16)이 사진식각 공정의 한계값으로 패턴 형성됨을 특징으로 하는 반도체 장치의 소자분리 방법.
  3. 제1항에 있어서, 상기 트렌치가 상기 제1도전층(16)의 두께에 의해 그 폭이 조절됨을 특징으로 하는 반도체장치의 소자분리 방법.
  4. 제3항에 있어서, 상기 제1도전층(16)이 다결정 실리콘임을 특징으로 하는 반도체 장치의 소자분리 방법.
  5. 제1항에 있어서, 상기 제1절연막(12)이 실리콘 산화막임을 특징으로 하는 반도체 장치의 소자분리 방법.
  6. 제1항에 있어서, 상기 제2절연막(14)이 실리콘 질화막임을 특징으로 하는 반도체 장치의 소자분리 방법.
  7. 제1항에 있어서, 상기 버퍼 절연막(24)이 산화막 임을 특징으로 하는 반도체 장치의 소자분리 방법.
  8. 제1항에 있어서, 상기 제2도전층(26)이 다결정 실리콘임을 특징으로 하는 반도체 장치의 소자분리 방법.
  9. 제1항에 있어서, 상기 제3절연막(30)이 실리콘 질화막을 제외한 절연막임을 특징으로 하는 반도체 장치의 소자분리 방법.
  10. 제1항에 있어서, 상기 제6공정에서 상기 제2도전층(26)의 열산화 공정이 상기 트렌치 내부를 완전히 채울때까지 진행됨을 특징으로 하는 반도체 장치의 소자분리 방법.
  11. 제1항에 있어서, 상기 제6공정이 상기 제2도전층(26)을 열산화시킨후 상기 기판 전면에 도핑되지 않은 다결정 실리콘으로 된 제3절연막을 형성하여 상기 다결정 실리콘을 열산화시킴에 의해 상기 트렌치 내부를 채우는 것임을 특징으로 하는 반도체 장치의 소자분리 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910005647A 1991-04-09 1991-04-09 반도체 장치의 소자분리 방법 KR920020676A (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019910005647A KR920020676A (ko) 1991-04-09 1991-04-09 반도체 장치의 소자분리 방법
FR9107131A FR2675310A1 (fr) 1991-04-09 1991-06-12 Processus d'isolation d'elements de dispositifs semiconducteurs.
ITMI911743A IT1248545B (it) 1991-04-09 1991-06-25 Procedimento di isolamento di elementi di un dispositivo a semiconduttori.
DE4121129A DE4121129A1 (de) 1991-04-09 1991-06-26 Elementisolationsverfahren fuer halbleitervorrichtungen
GB9114158A GB2254731A (en) 1991-04-09 1991-07-01 Element-isolating process for a semiconductor device
JP3167076A JPH0689884A (ja) 1991-04-09 1991-07-08 半導体装置の素子分離方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910005647A KR920020676A (ko) 1991-04-09 1991-04-09 반도체 장치의 소자분리 방법

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KR920020676A true KR920020676A (ko) 1992-11-21

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KR1019910005647A KR920020676A (ko) 1991-04-09 1991-04-09 반도체 장치의 소자분리 방법

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JP (1) JPH0689884A (ko)
KR (1) KR920020676A (ko)
DE (1) DE4121129A1 (ko)
FR (1) FR2675310A1 (ko)
GB (1) GB2254731A (ko)
IT (1) IT1248545B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100308510B1 (ko) * 1997-04-11 2001-11-07 다니구찌 이찌로오, 기타오카 다카시 반도체 장치 및 트렌치형 소자 분리 구조

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EP0631306B1 (de) * 1993-06-23 2000-04-26 Siemens Aktiengesellschaft Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien
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FR2800515B1 (fr) 1999-11-03 2002-03-29 St Microelectronics Sa Procede de fabrication de composants de puissance verticaux
US7238588B2 (en) 2003-01-14 2007-07-03 Advanced Micro Devices, Inc. Silicon buffered shallow trench isolation
US7422961B2 (en) 2003-03-14 2008-09-09 Advanced Micro Devices, Inc. Method of forming isolation regions for integrated circuits
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US6962857B1 (en) 2003-02-05 2005-11-08 Advanced Micro Devices, Inc. Shallow trench isolation process using oxide deposition and anneal
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US7462549B2 (en) 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
CN110137082A (zh) * 2018-02-09 2019-08-16 天津环鑫科技发展有限公司 一种功率器件沟槽形貌的优化方法

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Publication number Priority date Publication date Assignee Title
KR100308510B1 (ko) * 1997-04-11 2001-11-07 다니구찌 이찌로오, 기타오카 다카시 반도체 장치 및 트렌치형 소자 분리 구조

Also Published As

Publication number Publication date
IT1248545B (it) 1995-01-19
GB2254731A (en) 1992-10-14
DE4121129A1 (de) 1992-10-22
JPH0689884A (ja) 1994-03-29
FR2675310A1 (fr) 1992-10-16
GB9114158D0 (en) 1991-08-21
ITMI911743A0 (it) 1991-06-25
ITMI911743A1 (it) 1992-12-25

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