GB2254731A - Element-isolating process for a semiconductor device - Google Patents

Element-isolating process for a semiconductor device Download PDF

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Publication number
GB2254731A
GB2254731A GB9114158A GB9114158A GB2254731A GB 2254731 A GB2254731 A GB 2254731A GB 9114158 A GB9114158 A GB 9114158A GB 9114158 A GB9114158 A GB 9114158A GB 2254731 A GB2254731 A GB 2254731A
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United Kingdom
Prior art keywords
trench
conductive layer
semiconductor device
isolating
layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9114158A
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GB9114158D0 (en
Inventor
Hyeon-Jin Cho
Soo-Gil Yang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9114158D0 publication Critical patent/GB9114158D0/en
Publication of GB2254731A publication Critical patent/GB2254731A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A process for forming isolation trenches for a semiconductor device includes the stops of: etching a part of a first conductive layer corresponding to the trench region. and thermally oxidizing the remainder of the first conductive layer, to form an oxidized first conductive layer; removing a portion of a second 14 and first 12 insulating layer formed over the substrate, by using the oxidized first conductive layer as a mask, and thereafter etching the exposed substrate, to form a trench; depositing a buffer oxide layer and a second conductive layer of polycrystalline silicon on the inner wall of the trench and above the insulating layers respectively; and filling the interior of trench with only the oxidised second conductive layer 28 or additionally with an insulating material 30 other than a nitride layer. Thus the trench may have a width smaller than that obtained by photo-etching techniques. Further, because the interior of trench may be filled with only oxidised polycrystalline silicon the trench may have a width of 0. 3 mu m - 0. 4 mu m without bird's beak phenomenon. <IMAGE>

Description

ELEMENT-ISOLATING PROCESS FOR A SEMICONDUCTOR DEVICE The present invention relates to an element-isolating process for a semiconductor device, and particularly to a process for forming elementisolating regions by means of a trench structure.
Element-isolating regions of semiconductor devices play a role of providing electrical isolation between elements thereof. However the increase of density of semiconductor device makes the electrical isolation process very difficult. That is, VLSI (Very Large Scale Integrated Circuit) technology requires element-isolating regions in the 0.3,um - 0.4#m range, but current photo-etching techniques are not capable of overcoming a limit of 0.5cm.
Therefore, a new process suitable for VLSI devices is in urgent demand. On the other hand, even if element-isolating regions having a trench width below 0.5#m were to realized, the bird's beak phenomenon, which is liable to occur in the oxidization process after the etching of the trench, can not be inhibited.
Preferred embodiments of the present invention aim to provide a process of forming element-isolating regions in a semiconductor device, the element-isolating regions being provided with a trench width below the trench width released by current photo-etching techniques.
Another aim is to provide an element-isolating process for a semiconductor device, being capable of filling the interior of a trench without the bird's beak phenomenon accompanied by an etching of the trench.
According to a first aspect of the present invention, there is provided an element-isolating process for a semiconductor device, comprising the steps of: successively depositing a first insulating layer, a second insulating layer and a first conductive layer over a top surface of a semiconductor substrate of a first conduction type; subjecting a selected portion of said first conductive layer, corresponding to an element-isolating region, to an etching process, and thereafter subjecting the remainder of said first conductive layer to a thermal oxidation process so as to form an oxidized first conductive layer; subjecting selected portions of said second insulating layer and said first insulating layer to an etching process until a selected top surface of said substrate is exposed, by using said oxidized first conductive layer as a mask;; forming a trench through an etching process applied to the exposed top surface of said substrate; forming a buffer insulating layer on an inner wall of said trench, and thereafter depositing a second conductive layer over a remainder of whole surface of said substrate and said inner wall of said trench; filling an interior of said trench with an insulating material; and carrying out an etch-back process until a selected top surface of said second insulating layer is sufficiently exposed, and thereafter, removing an exposed portion of said second insulating layer through an etching process.
Preferably, formation of a pattern by said etching process for said selected portion of said first conductive layer, said pattern corresponding to said element-isolating region, is preferably carried out at a dimension corresponding to the minimum dimension obtainable by photo-etching technique.
Preferably, the width of said trench is controlled by the thickness of said first conductive layer.
Preferably, said first conductive layer is a polycrystalline silicon.
Preferably, said first insulating layer is a silicon oxide layer.
Preferably, said second insulating layer is a silicon nitride layer.
Preferably, said buffer insulating layer is an oxide layer.
Preferably, said second conductive layer is a polycrystalline silicon.
Preferably, said filling process comprises the steps of: subjecting said second conductive layer to a thermal oxidation process; and depositing a third insulating layer over said whole surface to a thickness sufficient to completely fill said interior of said trench.
Preferably, said filling process comprises a step of thermally oxidizing said second conductive layer until said interior of said trench is completely filled.
Preferably, said filling process comprises the steps of: subjecting said second conductive layer to a thermal oxidation; depositing an undoped polycrystalline silicon over said whole surface of said substrate; and thermally oxidizing said undoped polycrystalline silicon sufficiently to completely fill said interior of said trench.
According to another aspect, the invention provides an element isolating process for a semiconductor substrate, comprising the steps of forming a trench in a semiconductor substrate and filling the trench with an insulating material.
Such a process may further comprise any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
According to a flirther aspect of the present invention, there is provided an element-isolating process for a semiconductor device, the process comprising the steps of: successively depositing a first insulating layer made of an oxide layer, a second insulating layer made of a nitride layer, and a first conductive layer made of a polycrystalline silicon layer, upon a semiconductor substrate of a first conduction type; etching a selected portion of the first conductive layer corresponding to an element-isolating region, and subjecting the remainder of the first conductive layer to a thermal oxidation; successively removing the second and first insulating layers by using the oxidized first conductive layer as a mask; and forming a trench by subjecting the exposed substrate to etching.
The process may ftirther comprise the steps of: forming a buffer insulating layer on the inner wall of the trench to stabilize a surface contacted with the silicon substrate; then depositing a second conductive layer of polycrystalline silicon over the surface of the silicon substrate; and filling the interior of the trench with only an oxidized second conductive layer by adjusting the oxidation of the second conductive layer, or filling the interior of the trench with an insulating material other than a nitride layer after the oxidation of the second conductive layer.
The invention also extends to a semiconductor device manufactured by a process as above, according to any of the above aspects of the invention.
For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a sectional view showing one example of a semiconductor device produced in accordance with a process which embodies of the present invention; and Figures 2A - 21 illustrate respective steps in one example of such a manufacturing process.
Figure 1 is a sectional view showing trench isolating regions. The illustrated semiconductor device includes: an isolating-trench 22 having a width smaller than that provided with current photo-etching techniques, the trench 22 being formed in a selected position of a semiconductor substrate 10 of a first conduction type 10: an oxidized polycrystalline silicon layer 28 positioned adjacent to the inner wall of the trench 22; an insulating material 30 filling the interior of the trench; and a gate oxide layer 12 formed upon the selected portion of the substrate and connected to the oxidized polycrystalline silicon layer 28.
Figures 2A - 21 illustrate one example of a manufacturing process for the semiconductor device of Figure 1. In Figures 1 and 2, like reference numerals denote like or corresponding parts.
As shown in Figure 2A, a pad oxide layer 12, a nitride layer 14 and a first polycrystalline silicon layer 16 are successively deposited on the silicon substrate 10 of the first conduction type in thicknesses of 200 - 500 A, 500 - 1500 A and 1000 - 1500 A respectively. Then a photoresist is deposited on the polycrystalline silicon layer 16, and a photoresist pattern 18 is formed by a photo-etching process. Thus a given portion of the polycrystalline silicon layer 16, corresponding to an element-isolating region, is exposed. Then the exposed polycrystalline silicon layer is etched. Here, the pattern width of the element-isolating region is 0.5 im, which is the limit of the photo-etching method.
As shown in Figure 2B, the photoresist pattern 18 is removed, and then, the remainder of the first polycrystalline silicon layer 16 is subjected to a thermal oxidation, to form an oxidized polycrystalline silicon layer 20, the oxidized polycrystalline silicon layer 20 swelling upwardly and sidewardly.
The amount of swelling caused by the thermal oxidation is about 500 A. A distance d between the inner sides of the oxidized polycrystalline silicon 20 is about 0.4 Ccm, and is controlled by the thickness of the original first polycrystalline silicon layer 16.
As shown in Figure 2C, a dry etching is applied to an exposed portion of the nitride layer 14 and the oxide layer 12, to remove them through the oxidized polycrystalline silicon layer 20 which serves as the mask. Thus a selected surface of the semiconductor substrate is exposed. As shown in Figure 2D, the exposed portion of the silicon substrate 10 is vertically etched to a depth of 0.5 - 3 Cim by employing the oxidized polycrystalline silicon layer 20 as a mask, thereby forming the trench 22.
As shown in Figure 2E, a thermal oxidation is performed on the inner surface of the trench 22 to form a buffer oxide layer 24, and then, first conduction type impurities are ion-implanted thereinto, thereby forming an ion-implanted region for a field- stop.
As shown in Figure 2F, a second polycrystalline silicon layer 26 of a given thickness is formed upon the whole surface of the semiconductor device and inner wall of the trench. Then, as shown in Figure 2G, a thermal oxidation is applied to the second polycrystalline silicon layer 26, thereby forming an oxidized polysilicon layer 28 which swells upwardly and sidewardly.
As shown in Figure 2H, an insulating layer 30 is deposited over the whole surface of the substrate 10, sufficient to completely fill the interior of the trench, and is then flattened. In forming the insulating layer 30, a nitride layer should not be used, because the oxidized silicon layer 28 and the insulating layer 30 will be simultaneously etched back by employing the nitride layer 14 as an etch-stop layer in the following step.
As shown in Figure 21, the oxidized polycrystalline silicon layer 28 and the insulating layer 30 are sufficiently etched until the surface of the nitride layer 14 is sufficiently exposed. Then, the nitride layer 14 is removed by receiving a wet etching, thereby completing the formation of the elementisolating region in the form of a trench.
In the above described embodiment of the present invention, the interior of the trench is occupied with an insulating layer other than a nitride layer as shown in Figure 2H. However, in another embodiment according to the present invention, instead of the nitride layer, undoped polycrystalline silicon occupies the interior of the trench, and then the undoped polycrystalline silicon is oxidized. In the illustrated embodiment, an insulating layer is deposited after oxidizing the second polycrystalline silicon layer as shown in Figure 2G. However, in still another embodiment of the present invention, the interior of the trench can be filled with only the second polycrystalline silicon without additionally depositing a insulating layer, by adequate control of the oxidation of the second polycrystalline silicon layer.
According to the example of the present invention as described above, the width of the photoresist pattern is formed up to the limit-width of photo-etching technique, and then by utilizing the volume expansion based on a thermal oxidation of the polycrystalline layer, finally an element-isolating region of 0.3 - 0.4 #m is achieved. Further, since a buffer oxide layer and a polycrystalline silicon layer are successively formed on the inner wall of the trench and thereafter a thermal oxidation is carried out on the polycrystalline silicon layer, a trench type element-isolating region, in which the occurrence of bird's beak phenomenon is suppressed, is formed. As a result, such embodiments of the present invention may greatly assist an increase in density of semiconductor devices.
While preferred embodiments of the invention have been particularly shown and described, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the spirit and scope of the invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (15)

CLAIMS:
1. An element-isolating process for a semiconductor device, comprising the steps of: successively depositing a first insulating layer, a second insulating layer and a first conductive layer over a top surface of a semiconductor substrate of a first conduction type; subjecting a selected portion of said first conductive layer, corresponding to an element-isolating region, to an etching process, and thereafter subjecting the remainder of said first conductive layer to a thermal oxidation process so as to form an oxidized first conductive layer; subjecting selected portions of said second insulating layer and said first insulating layer to an etching process until a selected top surface of said substrate is exposed, by using said oxidized first conductive layer as a mask;; forming a trench through an etching process applied to the exposed top surface of said substrate; forming a buffer insulating layer on an inner wall of said trench, and thereafter depositing a second conductive layer over a remainder of whole surface of said substrate and said inner wall of said trench; filling an interior of said trench with an insulating material; and carrying out an etch-back process until a selected top surface of said second insulating layer is sufficiently exposed, and thereafter, removing an exposed portion of said second insulating layer through an etching process.
2. An element-isolating process for a semiconductor device as claimed in claim 1, wherein formation of a pattern by said etching process for said selected portion of said first conductive layer, said pattern corresponding to said element-isolating region is preferably carried out at a dimension corresponding to the min imunl (I i mens ion obtainable by photo-etching technique.
3. An element-isolating process for a semiconductor device as claimed in claim 1 or 2, wherein the width of said trench is controlled by the thickness of said first conductive layer.
4. An element-isolating process for a semiconductor device as claimed in any of claims 1 to 3, wherein said first conductive layer is a polycrystalline silicon.
5. An element-isolating process for a semiconductor device as claimed in any of the preceding claims wherein said first insulating layer is a silicon oxide layer.
6. An element-isolating process for a semiconductor device as claimed in any of the preceding claims, wherein said second insulating layer is a silicon nitride layer.
7. An element-isolating process for a semiconductor device as claimed in any of the preceding claims, wherein said buffer insulating layer is an oxide layer.
8. An element-isolating process for a semiconductor device as claimed in any of the preceding claims, wherein said second conductive layer is a polycrystalline silicon.
9. An element-isolating process for a semiconductor device as claimed in any of the preceding claims, wherein said filling process comprises the steps of: subjecting said second conductive layer to a thermal oxidation process; and depositing a third insulating layer over said whole surface to a thickness sufficient to completely fill said interior of said trench.
10. An element-isolating process for a semiconductor device as claimed in any of claims 1 to 8, wherein said filling process comprises a step of thermally oxidizing said second conductive layer until said interior of said trench is completely filled.
11. An element-isolating process for a semiconductor device as claimed any of claims 1 to 8, wherein said filling process comprises the steps of: subjecting said second conductive layer to a thermal oxidation; depositing an undoped polycrystalline silicon over said whole surface of said substrate; and thermally oxidizing said undoped polycrystalline silicon sufficiently to completely fill said interior of said trench.
12. An element isolating process for a semiconductor substrate, comprising the steps of forming a trench in a semiconductor substrate and filling the trench with an insulating material.
13. A process according to claim 12, further comprising any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
14. An element-isolating process for a semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
15. A semiconductor device manufactured by a process according to any of the preceding claims.
GB9114158A 1991-04-09 1991-07-01 Element-isolating process for a semiconductor device Withdrawn GB2254731A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910005647A KR920020676A (en) 1991-04-09 1991-04-09 Device Separation Method of Semiconductor Device

Publications (2)

Publication Number Publication Date
GB9114158D0 GB9114158D0 (en) 1991-08-21
GB2254731A true GB2254731A (en) 1992-10-14

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GB9114158A Withdrawn GB2254731A (en) 1991-04-09 1991-07-01 Element-isolating process for a semiconductor device

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JP (1) JPH0689884A (en)
KR (1) KR920020676A (en)
DE (1) DE4121129A1 (en)
FR (1) FR2675310A1 (en)
GB (1) GB2254731A (en)
IT (1) IT1248545B (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5496765A (en) * 1993-06-23 1996-03-05 Siemens Aktiengesellschaft Method for manufacturing an insulating trench in a substrate for smart-power technologies
US5700712A (en) * 1993-06-23 1997-12-23 Siemens Aktiengesellschaft Method for manufacturing an insulating trench in an SOI substrate for smartpower technologies
WO2004084299A2 (en) * 2003-03-14 2004-09-30 Advanced Micro Devices, Inc. Shallow trench isolation in processes with strained silicon
US6921709B1 (en) 2003-07-15 2005-07-26 Advanced Micro Devices, Inc. Front side seal to prevent germanium outgassing
US6962857B1 (en) 2003-02-05 2005-11-08 Advanced Micro Devices, Inc. Shallow trench isolation process using oxide deposition and anneal
US7105536B2 (en) 1999-07-02 2006-09-12 Smithkline Beecham Plc Compounds
US7238588B2 (en) 2003-01-14 2007-07-03 Advanced Micro Devices, Inc. Silicon buffered shallow trench isolation
US7462549B2 (en) 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
US7648886B2 (en) 2003-01-14 2010-01-19 Globalfoundries Inc. Shallow trench isolation process

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3904676B2 (en) * 1997-04-11 2007-04-11 株式会社ルネサステクノロジ Method for manufacturing trench type element isolation structure and trench type element isolation structure
DE19717363C2 (en) * 1997-04-24 2001-09-06 Siemens Ag Manufacturing process for a platinum metal structure using a lift-off process and use of the manufacturing process
FR2800515B1 (en) * 1999-11-03 2002-03-29 St Microelectronics Sa PROCESS FOR MANUFACTURING VERTICAL POWER COMPONENTS
CN110137082A (en) * 2018-02-09 2019-08-16 天津环鑫科技发展有限公司 A kind of optimization method of power device groove pattern

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0020994A1 (en) * 1979-06-14 1981-01-07 International Business Machines Corporation Method for making isolation trenches
EP0072966A2 (en) * 1981-08-27 1983-03-02 International Business Machines Corporation Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
EP0107902A2 (en) * 1982-09-29 1984-05-09 Fujitsu Limited A method for fabricating isolation regions in semiconductor devices
EP0139371A1 (en) * 1983-08-12 1985-05-02 Tektronix, Inc. Process for manufacturing a MOS integrated circuit employing a method of forming refractory metal silicide areas
GB2148593A (en) * 1983-10-14 1985-05-30 Hitachi Ltd Process for manufacturing the isolating regions of a semiconductor integrated circuit device
GB2148591A (en) * 1983-10-14 1985-05-30 Hitachi Ltd Semiconductor device isolation grooves
EP0178649A2 (en) * 1984-10-17 1986-04-23 Hitachi, Ltd. Complementary semiconductor device
WO1987004856A1 (en) * 1986-02-05 1987-08-13 Ncr Corporation Process for forming isolation trenches in a semiconductor substrate
GB2217909A (en) * 1988-04-26 1989-11-01 Mitsubishi Electric Corp Integrated circuits
EP0349107A2 (en) * 1988-06-30 1990-01-03 Sony Corporation Semiconductor devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2035468B (en) * 1978-10-11 1982-09-15 Pi Specialist Engs Ltd Vertical axis wind turbine
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
JPS5965446A (en) * 1982-10-06 1984-04-13 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS61107736A (en) * 1984-10-31 1986-05-26 Toshiba Corp Manufacture of semiconductor device
FR2598557B1 (en) * 1986-05-09 1990-03-30 Seiko Epson Corp METHOD FOR MANUFACTURING A MEMBER ISOLATION REGION OF A SEMICONDUCTOR DEVICE
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
US4707218A (en) * 1986-10-28 1987-11-17 International Business Machines Corporation Lithographic image size reduction
JPH01129439A (en) * 1987-11-16 1989-05-22 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0020994A1 (en) * 1979-06-14 1981-01-07 International Business Machines Corporation Method for making isolation trenches
EP0072966A2 (en) * 1981-08-27 1983-03-02 International Business Machines Corporation Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
EP0107902A2 (en) * 1982-09-29 1984-05-09 Fujitsu Limited A method for fabricating isolation regions in semiconductor devices
EP0139371A1 (en) * 1983-08-12 1985-05-02 Tektronix, Inc. Process for manufacturing a MOS integrated circuit employing a method of forming refractory metal silicide areas
GB2148593A (en) * 1983-10-14 1985-05-30 Hitachi Ltd Process for manufacturing the isolating regions of a semiconductor integrated circuit device
GB2148591A (en) * 1983-10-14 1985-05-30 Hitachi Ltd Semiconductor device isolation grooves
EP0178649A2 (en) * 1984-10-17 1986-04-23 Hitachi, Ltd. Complementary semiconductor device
WO1987004856A1 (en) * 1986-02-05 1987-08-13 Ncr Corporation Process for forming isolation trenches in a semiconductor substrate
GB2217909A (en) * 1988-04-26 1989-11-01 Mitsubishi Electric Corp Integrated circuits
EP0349107A2 (en) * 1988-06-30 1990-01-03 Sony Corporation Semiconductor devices

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5700712A (en) * 1993-06-23 1997-12-23 Siemens Aktiengesellschaft Method for manufacturing an insulating trench in an SOI substrate for smartpower technologies
US5496765A (en) * 1993-06-23 1996-03-05 Siemens Aktiengesellschaft Method for manufacturing an insulating trench in a substrate for smart-power technologies
US7105536B2 (en) 1999-07-02 2006-09-12 Smithkline Beecham Plc Compounds
US7648886B2 (en) 2003-01-14 2010-01-19 Globalfoundries Inc. Shallow trench isolation process
US7238588B2 (en) 2003-01-14 2007-07-03 Advanced Micro Devices, Inc. Silicon buffered shallow trench isolation
US6962857B1 (en) 2003-02-05 2005-11-08 Advanced Micro Devices, Inc. Shallow trench isolation process using oxide deposition and anneal
WO2004084299A3 (en) * 2003-03-14 2004-11-04 Advanced Micro Devices Inc Shallow trench isolation in processes with strained silicon
US7422961B2 (en) 2003-03-14 2008-09-09 Advanced Micro Devices, Inc. Method of forming isolation regions for integrated circuits
WO2004084299A2 (en) * 2003-03-14 2004-09-30 Advanced Micro Devices, Inc. Shallow trench isolation in processes with strained silicon
US7713834B2 (en) 2003-03-14 2010-05-11 Globalfoundries Inc. Method of forming isolation regions for integrated circuits
US6921709B1 (en) 2003-07-15 2005-07-26 Advanced Micro Devices, Inc. Front side seal to prevent germanium outgassing
US7462549B2 (en) 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
US7732336B2 (en) 2004-01-12 2010-06-08 Globalfoundries Inc. Shallow trench isolation process and structure with minimized strained silicon consumption

Also Published As

Publication number Publication date
JPH0689884A (en) 1994-03-29
DE4121129A1 (en) 1992-10-22
ITMI911743A0 (en) 1991-06-25
KR920020676A (en) 1992-11-21
FR2675310A1 (en) 1992-10-16
GB9114158D0 (en) 1991-08-21
ITMI911743A1 (en) 1992-12-25
IT1248545B (en) 1995-01-19

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