GB2148593A - Process for manufacturing the isolating regions of a semiconductor integrated circuit device - Google Patents

Process for manufacturing the isolating regions of a semiconductor integrated circuit device Download PDF

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Publication number
GB2148593A
GB2148593A GB08422520A GB8422520A GB2148593A GB 2148593 A GB2148593 A GB 2148593A GB 08422520 A GB08422520 A GB 08422520A GB 8422520 A GB8422520 A GB 8422520A GB 2148593 A GB2148593 A GB 2148593A
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United Kingdom
Prior art keywords
oxide film
silicon oxide
grooves
region
semiconductor
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Granted
Application number
GB08422520A
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GB2148593B (en
GB8422520D0 (en
Inventor
Mikinori Kawaji
Toshihiko Takakura
Akihisa Uchida
Shigeo Kuroda
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Hitachi Ltd
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Hitachi Ltd
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Publication date
Priority claimed from JP58190779A external-priority patent/JPS6083346A/en
Priority claimed from JP58210834A external-priority patent/JPS60103642A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB8422520D0 publication Critical patent/GB8422520D0/en
Publication of GB2148593A publication Critical patent/GB2148593A/en
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Publication of GB2148593B publication Critical patent/GB2148593B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)

Abstract

A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves 9 which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors, and a silicon oxide film 12 formed in the U-shaped grooves simultaneously with the formation of a silicon oxide film 4 by thermal oxidation is used to form isolation regions 10 between each collector contact region and base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges. i.e., at its boundaries with the U-shaped grooves. so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. <IMAGE>

Description

SPECIFICATION Process for manufacturing a semiconductor integrated circuit device The present invention relates to a process for manufacturing a semiconductor integrated circuit, and is particular to a process involving the formation of isolating regions for isolating elements of the device.
It is known to isolate elements in semiconductor integrated circuit devices by a method known as pn junction isolation, which uses diffusion layers, or by a method known as oxidation film isolation, which uses local oxidation films formed over the surface of the substrate. The widths of the isolation regions formed by such isolation methods, are relatively wide. Therefore, as the size of the elements becomes smaller, the isolation regions occupy proportionally larger areas. This makes it difficult to obtain large-scale integrated circuits (LSI circuits) in a very densely integrated form. The applicants have therefore proposed an isolation technique called Ugroove isolation in which portions that act as isolation regions between active regions of elements are cut to form U-shaped grooves (moats or trenches, hereinafter referred to as U-grooves).A silicon dioxide film is formed within the U-groves which are then filled with polycrystalline silicon. These form elementisolating regions.
This technique has been disclosed in, for example, the journal "NIKKEI ELECTRON ICS", March 29, 1982, No. 287, pp.
90-101.
Bipolar transistors are the main elements in the construction of a bipolar type of semiconductor integrated circuit device. However, bipolar transistors must be isolated from each other by U-grooves when they are very densely arranged on a semiconductor substrate.
To reduce the size of a bipolar transistor, however, an n±type semiconductor region that acts as a collector contact region must be isolated by an insulating material from a p+type base region.
The inventors have discovered that a problem arises when an attempt is made to satisfy these two requirements simultaneously.
When deep U-grooves isolating individual transistors and shallow U-grooves isolating each base region and collector region are used, the manufacturing process is complicated, and increased collector resistance makes the switching speed drop.
When U-grooves are used to isolate individual transistors, and when a field oxide film is used to isolate each base region and collector region, the breakdown voltage at the pn junction between the base region and the collector region drops due to "bird's beaks" formed in the field oxide film.
The object of the present invention is to increase the degree of integration of bipolar semiconductor integrated circuit devices, without impairing their electrical characteristics.
Another object of the present invention is to improve the electrical characteristics of semiconductor elements formed on a semiconductor body.
A further object of the present invention is to provide a process of manufacturing a semiconductor integrated circuit device in which semiconductor regions that act as collector contact regions and base regions are sufficiently isolated from each other, without increasing the number of processing steps.
These and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
The invention disclosed in this specification is described below briefly.
In a bipolar type of semiconductor integrated circuit device in which elements are isolated by U-groove isolation regions, an oxide film providing isolation is formed between a semiconductor region that acts as a collector contact region and a base region, simultaneously with the formation of a silicon oxide film within the U-shaped isolation grooves. This eliminates the necessity of providing a step of forming a new isolation oxide film. The thusformed isolation oxide film does not reach the n±type buried layer, and possesses sufficiently thick end portions even at its boundaries with the U-groove isolation regions.
Figures 1, 2, 4 to 6, and 8 to 16 are crosssectional views showing various steps in the manufacture of a bipolar type semiconductor integrated circuit device according to the present invention; Figure 3 is a plan view of the bipolar type semiconductor integrated circuit device during the step corresponding to Fig. 4, the section of Fig. 4 being along the line A-A in Fig. 3; and Figure 7 is a plan view of the device during the step corresponding to Figs. 8 and 9, the section of Fig. 8 being along the line B-B in Fig. 7 and the section of Fig. 9 being along the line C-C.
Figs. 1 to 1 6 illustrate an embodiment of the present invention, being a bipolar type of semiconductor integrated circuit device. The figures illustrate the sequence of steps in the manufacture of the device.
According to this embodiment, it is necessary first to form a semiconductor body 24.
Holes for the formation of buried layers are formed at suitable positions in a silicon oxide film formed over a semiconductor substrate 1 which consists of p-type monocrystalline silicon. Using the silicon oxide film as a mask, ntype impurities are thermally diffused into the substrate 1 to form a local n ±type buried layer 2. After the silicon oxide film is re moved, an n--type epitaxial layer 3 is grown onto the substrate 1 by a vapour growth method, and the resultant structure forms the semiconductor body 24.
A silicon oxide film (SiO2 film) 4 and a silicon nitride film (Si3N4 film) 5 are formed on a main surface of the semiconductor body 24.
The silicon nitride film 5 is removed from portions where wiring will be formed, around the periphery of the chip. Using the silicon nitride film 5 as a mask, the main surface of the substrate 1 is cut by e.g. a conventional isoplanar technique, followed by thermal oxidation, to form a field oxide film 6 of a thickness of between 1,um to 1.2pom, as shown in Fig. 1. Since the field oxide fillm 6 is so thick, it is possible to reduce the electrostatic capacity of the wiring provided in the wiring regions.
The silicon nitride film 5 is removed, and another silicon nitride film 25 is formed over the whole surface of the semiconductor body 24.
The silicon nitride film 25 is etched to remove it from portions at which isolation regions will be formed, i.e., from the peripheries of bipolar transistors and from regions between the base region and the collector contact region of each transistor. Using the silicon nitride film 25 as a mask, the surface of the semiconductor body 24 is locally oxidized by heating. Silicon oxide films 26a, 26b with a thickness between 300 mm and 350 mm are then formed over the portions at which the isolation regions will be formed, as shown in Fig. 2. The isolation region, base region, collector contact region, and the isolation region between the base region and the collector contact region are defined by the silicon nitride film 25.
The region between the base region and the collector contact region is covered with a photoresist film 27 and the exposed oxide films 26a are then removed by wet etching.
The silicon oxide film 26b is left between the base region and the collector contact region, and is used as a mask for the etching of the semiconductor body 24 and for the implantation of ions. After the photoresist film 27 is removed, the openings of the grooves are tapered, as shown in Figs. 3 and 4, by etching with hydrazine. The silicon oxide film 26b is not etched by the hydrazine. If the surface of the semiconductor body 24 has been sufficiently tapered after the silicon oxide films 26a have been removed, etching with hydrazine is not necessary.
4 pm deep grooves 7 are formed by dry etching using the silicon nitride film 25 and silicon oxide film 26b as masks so that the grooves 7 extend into the semiconductor body 24 as far as the substrate 1, as shown in Fig.
5. The etching reduces the thickness of the silicon oxide film 26b to about 200 mm.
Using the silicon nitride film 25 and silicon oxide film 26b as masks, boron ions are implanted into the bases of the U-grooves 7, and p±type channel-stopper layers 8 shown in Fig. 6 are then formed by heat treatment.
The boron ions are not introduced into the surface of the semiconductor substrate 24 in the regions where the silicon oxide film 26b has been formed. The breakdown voltage at the pn junction between the base region and the collector region is increased by the introduction of the boron ions. If the silicon oxide film 26b is about 100 mm thick, it is capable of preventing the boron ions being introduced into the semiconductor body 24.
Using the silicon nitride film 25 as a mask, the surface of the semiconductor body 24 is thermally oxidized, which forms a silicon oxide film 9 of a thickness of about 600 mm in each U-groove 7. Since the nitride film 25 has been removed from the portion between the base region and the collector contact region, a relatively thick isolation oxide film 10 with a thickness between about 700 mm and 800 mm is formed at this portion. The thickness of the silicon oxide film increases since oxygen reaches the surface of the semiconductor body 24 through the silicon oxide film 26b. The silicon oxide film 10 is thicker than the silicon oxide film 9 by the thickness of the silicon oxide film 26b.
The device in this state is shown in Figs. 7, 8 and 9, where Figs. 8 and 9 are sections taken along the lines B-B and C-C of Fig. 7, respectively. In Fig. 7, dot-dash lines 21a, 21b and 21c denote the positions of contact holes that will be formed in a subsequent step.
As shown in Fig. 9, the silicon oxide film 10 has end portions that continue from the silicon oxide film 9, at the same thickness, so that the base region and the collector contact region are reliably isolated from each other.
No stress concentrations (which would generate crystal defects) occur at the boundaries between the U-grooves 7 and the silicon oxide film 10.
A silicon nitride film is deposited over the whole surface of the semiconductor body 24 by e.g. a CVD method, so that a silicon nitride film 11 is formed over the oxide film 9 within the U-grooves 7, as shown in Fig. 10.
Polycrystalline silicon is deposited thickly over the whole surface of the semiconductor substrate 24 by a CVD method, so that the Ugrooves 7 are filled with polycrystalline silicon. The layer of polycrystalline silicon on the surface of the substrate is removed by dry etching to flatten the surface, leaving polycrystalline silicon 12 within the U-grooves 7, as shown in Fig. 11.
Using the silicon nitride film 25 as a mask, the surface of the polycrystalline silicon 12 in each U-groove is thermally oxidized to form a silicon oxide film 13 with a thickness of 600 mm on top of the polycrystalline silicon 12.
Then, as shown in Fig. 12, the silicon nitride film 25 is removed from the collector contact region. Using the silicon nitride film 25 as a mask, n-type impurities are implanted and are thermally diffused into the semiconductor body 24 to an n±type semiconductor region 14 that acts as a collector contact region.
The silicon nitride film 25 is removed using the silicon oxide film 13 as a mask, and ptype impurities are implanted into the whole main surface of the semiconductor body 24 to form a base region. A new silicon nitride film 15 is formed over the semiconductor body 24, and a p±type semiconductor region 16 that acts as a base region is formed by a heat treatment. Then, as shown in Fig. 13, the silicon nitride film 15 is removed from the portion that will be the emitter region.
The oxide film 4 is removed by etching from the surface of the portion that will be the emitter region, and a thin layer of polycrystalline silicon is deposited over the whole surface of the semiconductor body 24 by a CVD method. N-type impurities such as arsenic ions are implanted into the polycrystalline silicon layer, and are then diffused from the polycrystalline silicon layer by a heat treatment to form an n ±type semiconductor region 18 that acts as an emitter region. The majority of the polycrystalline silicon layer is thus removed by photolithography, the remaining polycrystalline silicon forming an electrode 19 on the emitter region 18. The resultant structure is shown in Fig. 14.
In this device, the emitter region 18 is formed by the diffusion of ions from the polycrystalline silicon layer. It is, however, also possible to implant ions and effect a heat treatment to form the emitter region prior to the deposition of the polycrystalline silicon.
Alternatively, the emitter region can be formed by implanting the diffusing ions, and by making the ions diffuse from the polycrystalline silicon, before depositing the polycrystalline silicon.
A PSG film (phosphosilicate glass film) is formed over the semiconductor body 24 by a CVD method to form an intermediate insulation film 20. Using a photoresist film as a mask, contact holes 21 a and 21 c are formed through the intermediate insulation film 20, the silicon nitride film 15 and the silicon oxide film 4, by etching, as shown in Fig. 15, to reach the base region, emitter region and collector region.
A wiring material such as aluminium is vapourized onto the whole surface of the semiconductor body 24, and aluminium electrodes 22a to 22c and aluminium wiring are formed by e.g. photolithography. A final passivation film 23, such as an SiO2 film, is then formed over the device as shown in Fig. 16.
Fig. 16 shows only one bipolar transistor with an epitaxial layer 3 to its right instead of other transistors. This is also true for Figs. 12 to 15.
In this embodiment, the isolation oxide film 10 is formed between the collector contact region 14 and the base region 16, simultaneously with the formation of the silicon oxide film 9 in each U-groove isolation region.
Therefore, no separate step is required for the formation of the isolation oxide film 10. Furthermore, when each collector contact region 14 and base region 16 are isolated from each other by a shallow U-groove, it is necessary to cut the U-grooves using two steps. In this embodiment, however, the U-grooves 7 may be formed by a single step, simplifying the manufacturing process.
The isolation oxide film 10 is formed simultaneously with the formation of the silicon oxide film 9, so that the isolation oxide film 10 is approximately uniform from the central portion to the edge portions thereof, as shown in Fig. 9. On the other hand, when the silicon oxide film 9 and the isolation oxide film 10 are formed by separate steps, the boundaries between the edges of the oxide film 10 and the U-groove isolation regions 7 become so thin that there is a drop in the breakdown voltage at the junction between the base region and the collector region. According to the embodiment of the present invention described above, however, the breakdown voltage does not decrease but is kept sufficiently high.
It is easier to control the thickness of the oxide film 10 than the depth of the U-shape isolation regions, so that variations in the electrical characteristics of the transistors may be reduced. The method in which the collector contact region 14 is isolated by a Ugroove isolation region from the base region 16 has the disadvantage that the collector resistance increases as the U-groove reaches the buried layer 3 through the epitaxial layer 2. When the U-groove is shallow, on the other hand, the breakdown voltage at the junction between the base region and the collector region drops. According to the embodiment of the present invention discussed above, however, the electrical characteristics of the transistors are greatly improved.
In this embodiment, the thick field oxide film 6 is formed over the regions where there are no transistors. A wiring layer, for instance, may be formed over the thick field oxide film 6, so that the regions covered by the field oxide film 6 may be used as wiring channels.
The emitter region 18 may be formed by implanting n-type impurities into the main surface of the substrate, without forming the polycrystalline silicon electrode 19, and the collector contact region can be formed after the base region and the emitter region have been formed.
The field oxide film 6 for the wiring region may be formed simultaneously with the formation of the silicon oxide film 9 in the U groove, in the same way as the formation of the isolation oxide film 10.
An isolation oxide film (an insulating material providing isolation) is formed between the collector contact region and the base region simultaneously with the formation of an oxide film (insulating material) in the Ugrooves used for isolation. Therefore, the isolation oxide film (the insulating material providing isolation) between the collector contact region and the thickness of the base region is nearly uniform from the central portion to the edge portions, so that the base region and the collector region are completely isolated from each other, and the thickness of the isolation oxide film (the insulating material providing isolation) does not vary much, and consequently, the transistors exhibit an improved performance.Moreover, there is no need for there to be a separate step of forming an isolation oxide film between the collector contact region and the base region, and the process can thus be simplified.
The present invention has been described above in connection with a specific embodiment. However, the invention should not be limited to this embodiment alone, but can be modified in various ways.
For instance, the field oxide film provided over the wiring region in this embodiment need not be limited to one formed by an isoplanar technique. The field oxide film can be obtained by selective oxidation, without subjecting the surface of the semiconductor substrate to etching. A p±type buried layer can be formed just under the field insulation film, or the field insulation film need not be formed at all.
The foregoing description has dealt with the case in which the present invention was adapted to a bipolar type of semiconductor integrated circuit. The invention, however, is not limited to this type of device alone, but can be utilized in any semiconductor device that requires isolation regions on the main surface of a semiconductor substrate.

Claims (13)

1. A process for manufacturing a semiconductor integrated circuit, comprising: forming a semiconductor body having a substrate of a first conductivity type, a buried layer of a second conductivity type, and an epitaxial layer of the second conductivity type; forming grooves in the semiconductor body, the grooves extending through the epitaxial and buried layers to the substrate, thereby to divide the epitaxial and buried layers into a plurality of isolated regions; forming a silicon oxide film on the surface of the semiconductor body, the silicon oxide film having a first part within the grooves and a second part on at least a part of the surface of at least one isolated region, such that the surface of the epitaxial layer of the or each such isolated region is divided into a first and a second part by the second part of the oxide film; forming isolation regions in the grooves; and forming a semiconductor element in at least some of the isolated region.
2. A process according to claim 1, wherein at least some of the semiconductor elements are bipolar transistors, each bipolar transistor having a base region of the first conductivity type formed in the first part of the corresponding isolated region, an emitter region of the second conductivity type formed in the base region, and a collector region formed from parts of the buried layer, the epitaxial layer and from a collector contact layer of the second conductivity type formed in the second part of the corresponding isolated region.
3. A process according to claim 1 wherein the grooves are formed by etching.
4. A process according to any one of the preceding claims, wherein the first and second parts of the silicon oxide film are formed by selectively thermally oxidizing the semiconductor body.
5. A process according to any one of the preceding claims, wherein the first and second parts of the silicon oxide film have substantially the same thickness.
6. A process according to any one of the preceding claims, wherein the isolation regions are formed by filling the grooves with polycrystalline silicon and by covering the surface of the polycrystalline silicon with a silicon oxide film.
7. A process of manufacturing a semiconductor integrated circuit device according to any one of the preceding claims further including forming a first mask on one main surface of the semiconductor body, except for the regions at which the grooves will be formed and the regions where the second parts of the silicon oxide will be formed; and forming a second mask on the regions where the second parts of the silicon oxide film will be formed; wherein the grooves are formed using the first and second masks, and the first and second silicon oxide films are formed using the first mask.
8. A process according to claim 7, wherein the first mask consists of a silicon nitride film, and the first and second parts of the silicon oxide films are formed by selectively and thermally oxidizing the semiconductor body.
9. A process according to claim 7 or claim 8, wherein the second mask consists of a silicon oxide film that is formed by selectively thermally oxidizing the semiconductor body using the first mask.
10. A process according to any one of claims 7 to 9, wherein a silicon oxide film is formed simultaneously with the formation of the second mask over the regions where the grooves will be formed, and the silicon oxide film is removed during the formation of the second mask.
11. A process according to any one of claims 7 to 10, wherein the first and second silicon oxide films are formed after the formation of the grooves by thermally oxidizing the semiconductor substrate using the first mask whilst the second mask is still in place, the second silicon oxide film being thicker than the first silicon oxide film.
1 2. A process according to any one of claims 7 to 11 wherein, after the formation of the grooves, semiconductor regions of the first conductivity type are formed in the semiconductor body in the bottoms of at least some of the grooves, the semiconductor region having an impurity concentration higher than that of the semiconductor substrate, and the impurities are introduced into the semiconductor body by ion implantation using the first and second masks, while said second mask is still in place.
13. A process for forming a semiconductor integrated circuit device substantially as any one herein described with reference to the accompanying drawings.
GB08422520A 1983-10-14 1984-09-06 Process for manufacturing the isolating regions of a semiconductor integrated circuit device Expired GB2148593B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58190779A JPS6083346A (en) 1983-10-14 1983-10-14 Semiconductor integrated circuit device
JP58210834A JPS60103642A (en) 1983-11-11 1983-11-11 Semiconductor device and manufacture thereof

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GB8422520D0 GB8422520D0 (en) 1984-10-10
GB2148593A true GB2148593A (en) 1985-05-30
GB2148593B GB2148593B (en) 1987-06-10

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HK (1) HK30789A (en)
SG (1) SG77388G (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686763A (en) * 1985-10-02 1987-08-18 Advanced Micro Devices, Inc. Method of making a planar polysilicon bipolar device
US4688314A (en) * 1985-10-02 1987-08-25 Advanced Micro Devices, Inc. Method of making a planar MOS device in polysilicon
US4707456A (en) * 1985-09-18 1987-11-17 Advanced Micro Devices, Inc. Method of making a planar structure containing MOS and bipolar transistors
EP0288691A1 (en) * 1987-04-13 1988-11-02 International Business Machines Corporation Bipolar transistor structure with self-aligned device and isolation and fabrication process therefor
GB2217909A (en) * 1988-04-26 1989-11-01 Mitsubishi Electric Corp Integrated circuits
EP0349107A2 (en) * 1988-06-30 1990-01-03 Sony Corporation Semiconductor devices
GB2254731A (en) * 1991-04-09 1992-10-14 Samsung Electronics Co Ltd Element-isolating process for a semiconductor device
US5232874A (en) * 1992-06-22 1993-08-03 Micron Technology, Inc. Method for producing a semiconductor wafer having shallow and deep buried contacts
GB2322736A (en) * 1997-02-28 1998-09-02 Int Rectifier Corp Forming trench isolation regions in integrated circuits

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0013508A1 (en) * 1978-12-30 1980-07-23 Fujitsu Limited Semiconductor device and a method of producing the same
EP0020994A1 (en) * 1979-06-14 1981-01-07 International Business Machines Corporation Method for making isolation trenches
EP0039411A2 (en) * 1980-05-05 1981-11-11 International Business Machines Corporation Process for fabricating an integrated PNP and NPN transistor structure
EP0072966A2 (en) * 1981-08-27 1983-03-02 International Business Machines Corporation Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
GB2128400A (en) * 1982-09-06 1984-04-26 Hitachi Ltd Isolation and wiring of a semiconductor integrated circuit device and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0013508A1 (en) * 1978-12-30 1980-07-23 Fujitsu Limited Semiconductor device and a method of producing the same
EP0020994A1 (en) * 1979-06-14 1981-01-07 International Business Machines Corporation Method for making isolation trenches
EP0039411A2 (en) * 1980-05-05 1981-11-11 International Business Machines Corporation Process for fabricating an integrated PNP and NPN transistor structure
EP0072966A2 (en) * 1981-08-27 1983-03-02 International Business Machines Corporation Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
GB2128400A (en) * 1982-09-06 1984-04-26 Hitachi Ltd Isolation and wiring of a semiconductor integrated circuit device and method of manufacturing the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4707456A (en) * 1985-09-18 1987-11-17 Advanced Micro Devices, Inc. Method of making a planar structure containing MOS and bipolar transistors
US4686763A (en) * 1985-10-02 1987-08-18 Advanced Micro Devices, Inc. Method of making a planar polysilicon bipolar device
US4688314A (en) * 1985-10-02 1987-08-25 Advanced Micro Devices, Inc. Method of making a planar MOS device in polysilicon
EP0288691A1 (en) * 1987-04-13 1988-11-02 International Business Machines Corporation Bipolar transistor structure with self-aligned device and isolation and fabrication process therefor
GB2217909A (en) * 1988-04-26 1989-11-01 Mitsubishi Electric Corp Integrated circuits
GB2217909B (en) * 1988-04-26 1991-07-17 Mitsubishi Electric Corp Method of manufacturing a semiconductor memory device
EP0349107A2 (en) * 1988-06-30 1990-01-03 Sony Corporation Semiconductor devices
EP0349107A3 (en) * 1988-06-30 1991-10-09 Sony Corporation Semiconductor devices
GB2254731A (en) * 1991-04-09 1992-10-14 Samsung Electronics Co Ltd Element-isolating process for a semiconductor device
US5232874A (en) * 1992-06-22 1993-08-03 Micron Technology, Inc. Method for producing a semiconductor wafer having shallow and deep buried contacts
GB2322736A (en) * 1997-02-28 1998-09-02 Int Rectifier Corp Forming trench isolation regions in integrated circuits
GB2322736B (en) * 1997-02-28 2002-06-26 Int Rectifier Corp Integrated photovoltaic switch with integrated power device

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HK30789A (en) 1989-04-21
SG77388G (en) 1991-01-04
GB2148593B (en) 1987-06-10
GB8422520D0 (en) 1984-10-10

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