JPS60103642A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To simplify the process and thus improve the characteristics of transistors by a method wherein an isolating region in an element is composed of insulator. CONSTITUTION:An isolating oxide film 10 is formed between a diffused layer 14 serving as the collector outlet and a base diffused layer 16 at the same time with an oxide film 9 in the U-goove isolation region. As a result, the process only for forming the oxide film 10 is unnecessitated. Besides, as in the case of isolation between the collector outlet 14 and the base diffused layer 16 by means of a shallow U-groove, deep U-grooves 7a and 7b can be formed at once without the need of cutting the U-grooves by twice, and the process simplifies thereby. Since the formed bi-polar transistor has the oxide film 10 between the collector outlet and the base diffused layer formed at the same time with the oxide film in the U-groove, this oxide film 10 becomes almost uniform in thickness from its center to both ends.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to semiconductor technology, and relates to a technology effective for use in forming isolation regions in semiconductor devices, for example.

[Background Art] As a method for isolating elements in a semiconductor integrated circuit, a junction isolation method using a diffusion layer and an oxide film isolation method using a selective oxide film called LOGO8 on a substrate surface are used.

However, in these isolation methods, the width of the element isolation region is made relatively large, and as elements become smaller, the ratio occupied by the element isolation region increases.
This poses an obstacle to increasing the density of large-scale integrated circuits.

Therefore, the present applicant cut away the part that will become the element isolation region to form a U-shaped groove c (hereinafter referred to as TJ groove), formed an oxide film inside this U groove, and then cut the inside of the TJ groove. He proposed an isolation technique called the U-groove isolation method in which element isolation regions are created by filling polysilicon (polycrystalline silicon) (Japanese Patent Application No. 168355/1982).

In the above-mentioned prior invention, as shown in FIG.
a, 27b, and the diffusion layer 1 serves as the collector outlet.
4 and the base diffusion layer 16 is achieved by a shallow U-groove isolation region 27c that penetrates only the epitaxial layer 3 and reaches the surface of the buried layer 2. Alternatively, as shown in FIG.
a, 27b, and is separated from the collector outlet 14 by a relatively thick oxide film 10.

However, the deep U-groove isolation regions 27a, 27 as described above
In the isolation structure using the shallow U-groove isolation region 27c, a deep U-groove and a shallow U-groove must be formed.
The process becomes more complicated. In addition, in the U-groove separation method, since it is difficult to control the depth of the U-groove, there is a risk that the U-groove 27c will become too deep.If the U-groove 27c becomes deep and digs into the buried layer 2, the collector resistance will increase. This has the disadvantage that the operating speed of the transistor becomes slow.

On the other hand, in a structure in which the collector outlet 14 and the base diffusion layer are separated by the oxide film 10, the oxide film 10
Providing a separate process for forming the wafer would complicate the process. Therefore, it is conceivable to form an isolation oxide film 0 at the same time as a thick field oxide film using LOGO8 or isoplanar technology, which is formed in an inactive area around the chip. 1
-3= When ○ is formed, bird's beaks are formed at both ends of the oxide film 10 as shown in FIG.
The oxide film 10 becomes thinner at the boundary between the groove isolation regions 27d and 27e. As a result, it was found that there was an inconvenience in that the collector outlet 14 and the base diffusion layer were short-circuited at a location indicated by the symbol A, and were not sufficiently separated from each other.

Note that FIG. 3 is a cross-sectional view taken along the line ■-■ in FIG. 2.

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that exhibits remarkable effects compared to the prior art.

Another object of the invention is to improve the characteristics of elements formed on a semiconductor substrate.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device that can sufficiently isolate a diffusion layer serving as a collector outlet and a base diffusion layer without increasing the number of process steps.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, in a bipolar integrated circuit in which elements are isolated by a U-groove isolation region, an oxide film is formed in the U-groove for isolation, and at the same time an oxide film is formed between the collector outlet and the base region for isolation. By forming an oxide film, there is no need to provide a new process for forming an isolation oxide film, and the formed isolation oxide film does not reach the buried layer, and both ends of the isolation oxide film are prevented from reaching the buried layer. The above object of simplifying the process and improving the characteristics of the transistor is achieved by making it possible to have a sufficient thickness even at the boundary between the U-groove isolation region and the U-groove isolation region.

[Embodiment] FIGS. 4 to 14 show an embodiment in which the present invention is applied to a bipolar integrated circuit in the order of manufacturing steps.

In this embodiment, an oxide film is formed on a semiconductor substrate 1 made of P-type silicon, although it is not particularly limited, and holes for buried diffusion patterns are formed at appropriate positions in this oxide film, and a hole made of this oxide film is inserted. Then, an N-type impurity is thermally diffused to partially form an N0 buried layer 2. After removing the oxide film, an N-type epitaxial layer 3 is grown by vapor phase growth, and an oxide film (SiO2 film) 4 and a nitride film (Si3N4 film) 5 are formed on its surface.

Then, the nitride film 5 in the portions that will become inactive areas such as around the chip is removed, and using this nitride film 5 as a mask, the main surface of the substrate 1 is shaved using normal isoplanar technology, and then thermal oxidation is performed. As shown in FIG. 2, a relatively thick field oxide film 6 is formed. This makes it possible to reduce the capacitance of wiring arranged on the inactive region. Thereafter, the nitride film 5 is once removed, and then a nitride film 5' is again formed over the entire substrate.

Next, after removing the nitride film 5' in the portion where the isolation region is to be formed (the periphery of the bipolar transistor and the boundary between the base region and the collector extraction port) by etching,
Thermal oxidation is performed using the nitride film 5' as a mask, and slightly thicker oxide films 4a, 4a, . . . are formed in the areas where isolation regions are to be formed.
(Figure 5). Thereafter, the boundary between the base region and the collector outlet is covered with a photoresist (indicated by a chain line C), and the exposed oxide film 4a is removed by wet etching, and then the photoresist C is removed. After that, hydrazine etching is performed to form a taper at the entrance of the groove. Next, dry etching is performed to form relatively deep U grooves 7a, 7 that reach the P type substrate 1.
When b is formed, the state shown in FIG. 6 is obtained.

Next, the U groove 7a formed as described above.

A channel stopper layer 8 is formed by implanting boron or other ions into 7b and performing heat treatment.
figure).

Thereafter, an insulating film 9 such as a 7-oxide film is formed to a thickness of about 6000 Å inside the U grooves 7a and 7b by thermal oxidation. Then, since the nitride film 5' between the base region and the collector outlet is removed at this time, a relatively thick isolation oxide film lO of about 6000 to 7000 λ is formed in this portion. Then, when a nitride film is deposited over the entire substrate by CVD or the like, a nitride film 11 is formed inside the oxide film 9 of the U grooves 7a and 7b as shown in FIG.
is formed.

After the state shown in FIG. 8, a relatively thick layer of polysilicon (polycrystalline silicon) is deposited over the entire substrate by the CVD method (chemical vapor deposition method).
, 7b are filled with polysilicon. Then, the polysilicon layer on the surface of the substrate is removed and planarized by dry etching, so that polysilicon 12 remains in the U grooves 7a and 7b (FIG. 9).

Then, thermal oxidation is performed to remove the polysilicon 12 inside the U-groove.
An oxide film 13 is formed on the polysilicon 12 by oxidizing the surface of the polysilicon 12.
After forming the nitride film 5' on the collector outlet, as shown in FIG. Form layer 14.

After the state shown in FIG. 10, the nitride film 5' is removed and P-type impurity ions are implanted to form a base region over the entire main surface of the substrate. Then, a nitride film 15 is formed again on the oxide films 4 and 6, and then heat treatment is performed to form a base diffusion layer 16, and then the nitride film 15 in the portion that will become the emitter region is removed (FIG. 11). .

Thereafter, the oxide film 4 on the surface of the portion that will become the emitter region is removed by etching, and then CV etching is applied to the entire nitride film 15.
Deposit a thin layer of polysilicon using method D. This polysilicon layer is then treated with N such as arsenic.
After ion implantation of type impurities, heat treatment is performed to form an emitter diffusion layer 18 by diffusion from the polysilicon layer. Next, the polysilicon layer is photoetched to remove unnecessary portions, leaving a polysilicon electrode 19 on the emitter diffusion layer 18, as shown in FIG.

In the above case, the emitter diffusion layer 18 is formed by diffusion from the polysilicon layer, but ion implantation and heat treatment for forming the emitter are performed before the polysilicon deposition. The emitter may be formed by performing ion implantation and diffusion twice before and after the position.

After forming the emitter diffusion layer 18, a PSG film (phosphorus silicate glass film) is formed on the nitride film 15 by the CVD method, and an interlayer insulating film 20 is formed.

Then, etching is performed using a photoresist as a mask to form contact holes 21a to 21c for each of the base, emitter, and collector electrode portions, resulting in the state shown in FIG. 13.

After that, a wiring material such as aluminum is deposited on the entire surface of the substrate, and then the aluminum electrodes 228 to 22 are formed by photo-etching.
C and aluminum wiring are formed, and a final passivation film 23 such as a 5in2 film is formed thereon to obtain a completed state as shown in FIG. 14.

In the above embodiment, the isolation oxide film 10 is formed between the diffusion layer 14, which becomes the collector outlet, and the base diffusion layer 16 at the same time as the formation of the oxide film 9 in the U-groove isolation region. , a step only for forming the isolation oxide film 10 is unnecessary.

Moreover, as in the case where the collector outlet 14 and the base diffusion layer 16 are separated by a shallow U groove,
There is no need to cut the groove in two parts, and the U groove 7a is deep.
, 7b can be formed all at once.

This simplifies the process.

Furthermore, in the bipolar transistor formed by the process described in the above embodiment, the isolation oxide film 10 between the collector extraction port 14 and the base diffusion layer 16 is formed at the same time as the oxide film in the U-groove. , this isolation oxide film 1
0 has a substantially uniform thickness from the center to both ends, as shown in FIG.

Therefore, as in the case where the isolation oxide film 10 is formed at the same time as the =11- field oxide film by LOGO8 or isoplanar (FIG. 3), the boundaries between the U-groove isolation regions 27d and 27e at both ends of the oxide film 10 The part becomes thinner and the base
The collectors will not be short-circuited, and the base and collector will be sufficiently insulated. In addition, the controllability of the thickness of the oxide film 10 is better than the controllability of the depth of the U-groove isolation region. As a result, variations in transistor characteristics are reduced, and the U-groove does not penetrate through the epitaxial layer 2, as in the case where the collector extraction port 14 and the base diffusion layer 16 are separated by the U-groove isolation region. There is no fear that the collector resistance will increase due to reaching the buried layer 3.

As a result, the characteristics of the transistor are greatly improved.

In the above embodiment, the U-groove isolation region is formed to surround the region where the transistor is formed. When another transistor is formed adjacently, a part of the U-groove isolation region is also used as an isolation region for this transistor 12-. In addition, in a region nearby where another transistor is not formed, a 14th transistor is formed.
A thick field oxide film 6 is formed as shown in the figure. For example, a wiring layer is formed on this thick field oxide film.

Further, in the above embodiment, the emitter region is formed by diffusion from the polysilicon electrode 19 formed thereon, but the emitter region is formed by diffusion from the polysilicon electrode 19 formed thereon.
The emitter diffusion layer 18 may be formed by directly implanting N-type impurity ions into the main surface of the substrate.

Furthermore, in the above embodiment, the N-type diffusion layer 14 serving as the collector outlet is formed before the base and emitter regions are formed, but the collector outlet may be formed after the base and emitter are formed. good.

Furthermore, in the embodiment described above, the field oxide film 6 in the inactive region is formed by isoplanar technology, but in the same way as the isolation oxide film 10 between the collector extraction port 14 and the base diffusion layer 16. , may be performed simultaneously with the formation of the oxide film 9 in the U-groove.

[Effects] (1) In a bipolar integrated circuit in which element isolation is performed by a U-groove isolation region, the isolation formed at the same time as the formation of the oxide film (insulator) formed in the U-groove for isolation. Since the isolation oxide film (isolation insulator) is provided between the collector outlet and the base region, the isolation oxide film (isolation insulator) between the collector outlet and the base region is The thickness becomes almost uniform from the center to both ends, and the base and collector are completely isolated, and there is little variation in the thickness of the isolation oxide film (isolation insulator), which makes the transistor This has the effect of improving characteristics.

(2) In a bipolar integrated circuit in which elements are isolated by a U-groove isolation region, the collector lead-out port and the base region are Since an isolation oxide film (isolation insulator) is formed between the collector outlet and the base region, the isolation oxide film (isolation insulator) is
Since there is no need to provide a separate process for forming the , there is an effect that the process becomes simpler.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the field oxide film provided in the inactive region in the above embodiment is not limited to one formed by eye-planar technology;
It may also be O8 or the like.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to bipolar integrated circuits, which is the field of application that formed the background of the invention, but the invention is not limited to this. It can be used in general semiconductor devices that require an oxide film on the main surface of a semiconductor substrate.

-15=

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a configuration example of a bipolar transistor in a semiconductor device of a prior application applying the U-groove isolation method, FIG. 2 is a sectional view showing another configuration example, and FIG.
A sectional view taken along the line ■-■ in FIG. 2, FIGS. 4 to 14 are sectional views showing one embodiment of the present invention in the order of manufacturing steps, and FIG. 15 is a sectional view taken along the line BB in FIG. 11. FIG. l... Semiconductor substrate, 2... N0 buried layer, 3...
...Epitaxial layer, 4...Oxide film, 5.5'
. 15...Nitride film, 6...Field oxide film, 7
a, 7b...Groove (U groove), 8...Channel stopper layer, 9...Insulating film (oxide film), 10...
Isolation insulating film (isolation oxide film), 11... Insulating film (
nitride film), 12...dielectric (polysilicon), 13
... Oxide film, 14... Diffusion layer serving as collector outlet, 16... Diffusion layer for base, 1816-... Diffusion layer for emitter, 19... Polysilicon electrode, 20... Interlayer insulating film, 21a to 21c...
・Contact hole, 22a-22c...aluminum electrode, 23...passivation film, 278-27e
...U groove separation area.

Claims (1)

[Claims] 1. A semiconductor in which an isolation region is formed by digging a trench between the active regions of an element formed on the main surface of a semiconductor substrate, forming an insulating film on the inside, and then filling it with a dielectric. A semiconductor device, wherein at least the isolation region within the element is made of an insulator. 2. The insulator constituting the isolation region within the element is formed to have a substantially uniform thickness from its center to the boundary with the groove formed so as to surround the outside of the element. A semiconductor device according to claim 1, characterized in that: 3. A method for manufacturing a semiconductor device, in which a groove is dug between active regions of elements formed on the main surface of a semiconductor substrate, an insulating film is formed inside, and then a dielectric is filled to form an isolation region, A method for manufacturing a semiconductor device, characterized in that an isolation insulating film is simultaneously formed in the isolation region in the element by the same process as an insulating film formed inside the isolation groove. 4. The insulating film formed inside the isolation groove is an oxide film, and the isolation groove is formed between the diffusion layer serving as the collector outlet of the bipolar transistor as the element and the base diffusion layer. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the isolation oxide film is formed at the same time as the oxide film formed inside the semiconductor device.