IT1248545B - Procedimento di isolamento di elementi di un dispositivo a semiconduttori. - Google Patents

Procedimento di isolamento di elementi di un dispositivo a semiconduttori.

Info

Publication number
IT1248545B
IT1248545B ITMI911743A ITMI911743A IT1248545B IT 1248545 B IT1248545 B IT 1248545B IT MI911743 A ITMI911743 A IT MI911743A IT MI911743 A ITMI911743 A IT MI911743A IT 1248545 B IT1248545 B IT 1248545B
Authority
IT
Italy
Prior art keywords
layer
conductive layer
groove
semiconductor device
substrate
Prior art date
Application number
ITMI911743A
Other languages
English (en)
Inventor
Hyeon-Jin Cho
Soo-Gil Yang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI911743A0 publication Critical patent/ITMI911743A0/it
Publication of ITMI911743A1 publication Critical patent/ITMI911743A1/it
Application granted granted Critical
Publication of IT1248545B publication Critical patent/IT1248545B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

E' descritto un procedimento di isolamento di elementi di un dispositivo a semiconduttore. Il procedimento di isolamento di elementi include le tesi di: incidere la parte di un primo strato conduttore (16) corrispondente alla regione di isolamento di elementi e ossidare termicamente il resto del primo strato conduttore, per formare un primo strato conduttore ossidato (20); rimuovere un secondo e primo strato isolante formato sul substrato, impiegando il primo strato conduttore ossidato (20) come una maschera, e successivamente incidere il substrato esposto, per formare un solco; depositare uno strato (24) di isolamento tampone di uno strato di ossido e un secondo strato conduttore di silicio policristallino sulla parete interna del solco e sulla superficie del substrato rispettivamente; e riempire l'interno del solco con solamente il secondo strato conduttore regolando l'ossidazione di esso, o con un materiale isolante diverso da uno strato di nitruro dopo l'ossidazione del secondo strato conduttore. Pertanto, il solco ha una larghezza inferiore a quella ottenuta mediante la tecnica di fotoincisione. Inoltre, poiché l'interno del solco è riempimento con solamente il silicio policristallino tramite l'ossidazione di esso, il solco presenta una larghezza di 0,3 /um - 0,4 / um senza il fenomeno dei cosiddetti becchi d'uccello.
ITMI911743A 1991-04-09 1991-06-25 Procedimento di isolamento di elementi di un dispositivo a semiconduttori. IT1248545B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910005647A KR920020676A (ko) 1991-04-09 1991-04-09 반도체 장치의 소자분리 방법

Publications (3)

Publication Number Publication Date
ITMI911743A0 ITMI911743A0 (it) 1991-06-25
ITMI911743A1 ITMI911743A1 (it) 1992-12-25
IT1248545B true IT1248545B (it) 1995-01-19

Family

ID=19313051

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI911743A IT1248545B (it) 1991-04-09 1991-06-25 Procedimento di isolamento di elementi di un dispositivo a semiconduttori.

Country Status (6)

Country Link
JP (1) JPH0689884A (it)
KR (1) KR920020676A (it)
DE (1) DE4121129A1 (it)
FR (1) FR2675310A1 (it)
GB (1) GB2254731A (it)
IT (1) IT1248545B (it)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59409300D1 (de) * 1993-06-23 2000-05-31 Siemens Ag Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien
DE59405680D1 (de) * 1993-06-23 1998-05-20 Siemens Ag Verfahren zur Herstellung eines Isolationsgrabens in einem Substrat für Smart-Power-Technologien
JP3904676B2 (ja) * 1997-04-11 2007-04-11 株式会社ルネサステクノロジ トレンチ型素子分離構造の製造方法およびトレンチ型素子分離構造
DE19717363C2 (de) * 1997-04-24 2001-09-06 Siemens Ag Herstellverfahren für eine Platinmetall-Struktur mittels eines Lift-off-Prozesses und Verwendung des Herstellverfahrens
GB9915589D0 (en) 1999-07-02 1999-09-01 Smithkline Beecham Plc Novel compounds
FR2800515B1 (fr) * 1999-11-03 2002-03-29 St Microelectronics Sa Procede de fabrication de composants de puissance verticaux
US7422961B2 (en) * 2003-03-14 2008-09-09 Advanced Micro Devices, Inc. Method of forming isolation regions for integrated circuits
US7648886B2 (en) 2003-01-14 2010-01-19 Globalfoundries Inc. Shallow trench isolation process
US7238588B2 (en) 2003-01-14 2007-07-03 Advanced Micro Devices, Inc. Silicon buffered shallow trench isolation
US6962857B1 (en) 2003-02-05 2005-11-08 Advanced Micro Devices, Inc. Shallow trench isolation process using oxide deposition and anneal
US6921709B1 (en) 2003-07-15 2005-07-26 Advanced Micro Devices, Inc. Front side seal to prevent germanium outgassing
US7462549B2 (en) 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
CN110137082A (zh) * 2018-02-09 2019-08-16 天津环鑫科技发展有限公司 一种功率器件沟槽形貌的优化方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2035468B (en) * 1978-10-11 1982-09-15 Pi Specialist Engs Ltd Vertical axis wind turbine
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
JPS5961045A (ja) * 1982-09-29 1984-04-07 Fujitsu Ltd 半導体装置の製造方法
JPS5965446A (ja) * 1982-10-06 1984-04-13 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
JPS6083346A (ja) * 1983-10-14 1985-05-11 Hitachi Ltd 半導体集積回路装置
GB2148593B (en) * 1983-10-14 1987-06-10 Hitachi Ltd Process for manufacturing the isolating regions of a semiconductor integrated circuit device
CN1004736B (zh) * 1984-10-17 1989-07-05 株式会社日立制作所 互补半导体器件
JPS61107736A (ja) * 1984-10-31 1986-05-26 Toshiba Corp 半導体装置の製造方法
US4671970A (en) * 1986-02-05 1987-06-09 Ncr Corporation Trench filling and planarization process
FR2598557B1 (fr) * 1986-05-09 1990-03-30 Seiko Epson Corp Procede de fabrication d'une region d'isolation d'element d'un dispositif a semi-conducteurs
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
US4707218A (en) * 1986-10-28 1987-11-17 International Business Machines Corporation Lithographic image size reduction
JPH01129439A (ja) * 1987-11-16 1989-05-22 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0727974B2 (ja) * 1988-04-26 1995-03-29 三菱電機株式会社 半導体記憶装置の製造方法
JP2666384B2 (ja) * 1988-06-30 1997-10-22 ソニー株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH0689884A (ja) 1994-03-29
DE4121129A1 (de) 1992-10-22
ITMI911743A0 (it) 1991-06-25
KR920020676A (ko) 1992-11-21
FR2675310A1 (fr) 1992-10-16
GB9114158D0 (en) 1991-08-21
ITMI911743A1 (it) 1992-12-25
GB2254731A (en) 1992-10-14

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