KR970008473A - 반도체장치의 소자격리방법 - Google Patents

반도체장치의 소자격리방법 Download PDF

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Publication number
KR970008473A
KR970008473A KR1019950019680A KR19950019680A KR970008473A KR 970008473 A KR970008473 A KR 970008473A KR 1019950019680 A KR1019950019680 A KR 1019950019680A KR 19950019680 A KR19950019680 A KR 19950019680A KR 970008473 A KR970008473 A KR 970008473A
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South Korea
Prior art keywords
substrate
forming
oxide film
trench
silicon
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KR1019950019680A
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English (en)
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KR0156151B1 (ko
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한정수
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문정환
Lg 반도체 주식회사
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Priority to KR1019950019680A priority Critical patent/KR0156151B1/ko
Publication of KR970008473A publication Critical patent/KR970008473A/ko
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Publication of KR0156151B1 publication Critical patent/KR0156151B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체장치의 소자격리방법에 관한 것으로, 새부리현상을 방지하고 평탄화에 유리하도록 한 얕은 트렌치형 소자격리방법에 관한 것이다.
본 발명은 필드산화막이 형성될 소자격리영역에 해당하는 실리콘 기판부위를 선택적으로 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 내측면에 산화막측벽을 형성하는 공정, 필드산화공정을 행하여 노출된 기판부위와 상기 산화막측벽과기판이 접촉되는 부위에 열산화막을 성장시키는 공정, 기판 전면에 실리콘 산화물을 형성하는 공정, 및 상기 실리콘 산화막을 에치백하는 공정을 포함하여 이루어지는 반도체장치의 소자격리방법을 제공한다.

Description

반도체장치의 소자격리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의한 소자격리방법을 도시한 공정순서도.

Claims (4)

  1. 필드산화막이 형성될 소자격리영역에 해당하는 실리콘 기판부위를 선택적으로 식각하여 트렌치를 형성하는공정과, 상기 트렌치 내측면에 산화막측벽을 형성하는 공정, 필드산화공정을 행하여 노출된 기판부위와 상기 산화막측벽과 기판이 접촉되는 부위에 열산화막을 성장시키는 공정, 기판 전면에 실리콘 산화물을 형성하는 공정, 및 상기 실리콘산화막을 에치백하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 소자격리방법.
  2. 제1항에 있어서, 상기 기판을 식각하여 트렌치를 형성하는 공정전에 실리콘 기판상에 초기산화막을 형성하는 공정이 더 포함되는 것을 특징으로 하는 반도체장치의 소자격리방법.
  3. 제1항에 있어서, 상기 트렌치를 형성하는 공정후에 필드 이온주입을 실시하는 공정이 더 포함되는 것을 특징으로 하는 반도체장치의 소자격리방법.
  4. 제1항에 있어서, 상기 산화막 측벽은 상기 트렌치를 형성한 후, 기판 전면에 실리콘산화막을 증착하고 이를 에치백하여 형성하는 것을 특징으로 하는 반도체장치의 소자격리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950019680A 1995-07-05 1995-07-05 반도체장치의 소자격리방법 KR0156151B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019680A KR0156151B1 (ko) 1995-07-05 1995-07-05 반도체장치의 소자격리방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019680A KR0156151B1 (ko) 1995-07-05 1995-07-05 반도체장치의 소자격리방법

Publications (2)

Publication Number Publication Date
KR970008473A true KR970008473A (ko) 1997-02-24
KR0156151B1 KR0156151B1 (ko) 1998-12-01

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KR1019950019680A KR0156151B1 (ko) 1995-07-05 1995-07-05 반도체장치의 소자격리방법

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KR0156151B1 (ko) 1998-12-01

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