KR960026951A - 트랜지스터 및 그 제조 방법 - Google Patents

트랜지스터 및 그 제조 방법 Download PDF

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KR960026951A
KR960026951A KR1019940036937A KR19940036937A KR960026951A KR 960026951 A KR960026951 A KR 960026951A KR 1019940036937 A KR1019940036937 A KR 1019940036937A KR 19940036937 A KR19940036937 A KR 19940036937A KR 960026951 A KR960026951 A KR 960026951A
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film
semiconductor substrate
forming
layer
transistor
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KR1019940036937A
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KR0143713B1 (ko
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서정원
노광명
황성민
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김주용
현대전자산업 주식회사
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Priority to KR1019940036937A priority Critical patent/KR0143713B1/ko
Priority to US08/554,891 priority patent/US5693542A/en
Priority to DE19543859A priority patent/DE19543859B4/de
Priority to CN95120590A priority patent/CN1093687C/zh
Priority to GB9526141A priority patent/GB2296817B/en
Priority to JP7339626A priority patent/JP2894680B2/ja
Publication of KR960026951A publication Critical patent/KR960026951A/ko
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Publication of KR0143713B1 publication Critical patent/KR0143713B1/ko

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Abstract

본 발명은 반도체 기판 상의 게이트 절연층, 상기 게이트 절연층 상의 게이트 전도층, 상기 게이트 전도층 패턴 측 및 타측 하부의 반도체 기판 상에 일정깊이 형성된 소오스 전합층 및 드레인 접합층을 구비하여 상기 게이트 전도층 하부의 소소오스 접합층과 드레인 접합층 사이의 반도체 기판에 채널을 형성하는 트랜지스터에 있어서, 상기 소오스 전합층 및 드레인 접합층 사이의 채널영역 반도체 기판에 형성되어 채널 역할을 하는 전도층과, 상기 전도층 하부의 반도체 기판에 형성되어 숏채널에 의해 발생하는 펀치쓰루(Punchthrough)를 방지하는 절연층을 더 구비하는 것을 특징으로 하는 트랜지스터 및 그 제조 방법에 관한 것으로, SOI 구조 트랜지스터의 장점을 갖으면서, 채널 밑에 절연막이 존재하므로, 깊은 서브마이크론 트랜지스터의 숏 채널에 의해 발생하는 펀치쓰루(Punchtrough)를 방지하여 트랜지스터가 안정된 동작 특성을 갖는 효과가 있다.

Description

트랜지스터 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1J도는 본 발명의 일실시예에 따른 트랜지스터 제조 공정도.

Claims (15)

  1. 반도체 기판 상의 게이트 절연층, 상기 게이트 절연층 상의 게이트 전도층, 상기 게이트 전도층 패턴 측벽일측 및 타측 하부의 반도체 기판 상에 일정깊이 형성된 소오스 전합층 및 드레인 접합층을 구비하여 상기 게이트 전도층 하부의 소오스 접합층과 드레인 접합층을 구비하여 상기 게이트 전도층 하부의 소오스접합층과 드레인 접합층 사이의 반도체 기판에 채널을 형성하는 트랜지스터에 있어서, 상기 소오스 전합층 및 드레인 접합층 사이의 채널영역 반도체 기판에 형성되어 채널 역할을 하는 전도층과, 상기 전도층 하부의 반도체기판에 형성되어 숏채널에 의해 발생하는 펀치쓰루(Punchthrough)를 방지하는 절연층을 더 구비하는 것을 특징으로 하는 트랜지스터.
  2. 트랜지스터 제조 방법에 있어서, 트랜지스터의 채널이 형성될 예정된 부위의 반도체 기판을 식각하여 트렌치를 형성하는 단계, 상기 반도체 기판 표면으로 부터 예정된 채널폭 정도의 일정깊이를 제외한 상기 트렌치 내부에 절연막을 형성하는 단계, 상기 반도체 기판 표면으로부터 절연막에 의해 채워지지 않은 트렌치 내부에 전도막을 형성하는단계, 트랜지스터의 패널이 형성될 예정된 부위의 반도체 기판 및 상기 전도막 상에 게이트 절연막과 게이트 전도막을 차례로 형성하는 단계, 및 상기 이온주입을 통해 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 제조 방법.
  3. 제 2 항에 있어서, 상기 반도체 기판 표면으로부터 예정된 채널폭 정도의 일정깊이를 제외한 상기 트렌치 내부에 절연막을 형성하는 단계는, 전체구조 상부에 절연막을 증착하는 단계, 상기 절연막을 예정된 타켓으로 에치백하는 단계를 포함하는 것을 특징으로 하는 트랜지스터의 제조 방법.
  4. 제 2 항에 있어서, 상기 반도체 기판 표면으로부터 절연막에 의해 채워지지 않은 트렌치 내부에 폴리실리콘막을 형성하는 단계는, 폴리실리콘막을 전체 구조상부에 증착하는 단계, 예정된 타켓으로 산화 공정을 수행하여 상기반도체 기판 표면 상부의 폴리실리콘막을 산화막으로 형성하는 단계, 상기 반도체 기판 표면의 상부의 산화막을 제거하는단계를 포함하는 것을 특징으로 하는 트랜지스터의 제조 방법.
  5. 제 4 항에 있어서, 상기 전도막은 실리콘막 또는 폴리실리콘막인 을 특징으로 하는 트랜지스터의 제조 방법.
  6. 트랜지스터의 제조 방법에 있어서, 반도체 기판 표면에서부터 일정 깊이에 기판과 다른 타입(Type)의 저농도 불순물을 이온주입하여 저농도 도핑영역을 형성하는 단계, 트랜지스터의 채널이 형성될 예정된 부위의 반도체 기판 표면이 오픈 되도록 제1절연막 패턴을 형성하는 단계, 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계, 상기 제1절연막과 식각선택비 차이가 큰 제2절연막을 전체구조 상부에 형성하는 단계, 상기 제2절연막을 식각하여 상기 반도체 기판표면으로부터 예정된 채널폭 정도의 일정깊이를 제외한 상기 트렌치 내부에만 제2절연막을 형성하는 단계, 상기 반도체 기판 표면으로부터 제2절연막에 의해 채워지지 않은 트렌치내부에 전도막을 형성하는 단계,상기 제1절연막을 제거하는 단계, 트렌지스터의 채널이 형성될 예정된 부위의반도체 기판 및 상기 전도막 상에 게이트 절연막과 게이트 전도막을 차례로 형성하는 단계, 및 이온주입을 통해 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징으로 하는 트랜지스터의 제조 방법.
  7. 제 6항에 있어서, 상기 제1절연막은 질화막인 것을 특징으로 하는 트랜지스터의 제조 방법.
  8. 제 7항에 있어서, 상기 제2절연막은 산화막인 것을 특징으로 하는 트랜지스터의 제조 방법.
  9. 제 6항에 있어서, 상기 전도막은 실리콘막 또는 폴리실리콘막인 것을 특징으로 하는 트랜지스터의 제조 방법.
  10. 제 9 항에 있어서, 상기 반도체 기판 표면으로부터 제2절연막에 의해 채워지지 않은 트렌치 내부에 폴리실리콘막을 형성하는 단계는, 전체구조 상부에 폴리실리콘막을 형성하는 단계, 상기 폴리실리콘막을 에치백하는 단계를포함하는 것을 특징으로 하는 트랜지스터 제조 방법.
  11. 트랜지스터 제조 방법에 있어서, 트랜지스터의 채널이 형성될 예정된 부위의 반도체 기판이 오픈되도록제1절연막 및 제2절여막을 차례로 패터닝하는 단계, 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계, 산화공정을 통해 트렌치에 의해 노출된 반도체 기판을 산화시켜 트렌치 부위에 산화막을 형성하는 단계, 상기 제2절연막을 제거하고 제1절연막 및 산화막을 식각하여 상기 반도체 기판 표면으로부터 예정된 채널폭 정도의 일정깊이를 제외한 상기트렌치 내부에 산화막을 남기고 반도체 기판 표면 상부에 잔류 제1절연막을 형성하는 단계, 상기 반도체 기판 표면으로부터 산화막에 의해 채워지지 않은 트렌치 내부에 전도막을 형성하는 단계, 상기 전도막 상에 게이트 절연막을 형성하고 게이트 전도막을 형성하는 단계, 이온주입을 통해 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징하는 트랜지스터의 제조 방법.
  12. 제 11 항에 있어서, 상기 반도체 기판 표면으로부터 산화막에 의해 채워지지 않은 트렌치 내부에 전도막을 형성하는 단계는, 에피텍시(Epitaxy) 공정으로 전도막을 성장시키는 것을 특징으로 하는 트랜지스터의 제조 방법.
  13. 제 11항에 있어서, 상기 제1절연막은 산화막인 것을 특징으로 하는 트랜지스터의 제조 방법.
  14. 제 11항에 있어서, 상기 제2절연막은 질화막인 것을 특징으로 하는 트랜지스터의 제조 방법.
  15. 제 11항에 있어서, 상기 전도막은 실리콘막 또는 폴리실리콘막인 것을 특징으로 하는 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940036937A 1994-12-26 1994-12-26 트랜지스터 및 그 제조 방법 KR0143713B1 (ko)

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US08/554,891 US5693542A (en) 1994-12-26 1995-11-09 Method for forming a transistor with a trench
DE19543859A DE19543859B4 (de) 1994-12-26 1995-11-24 Transistor und Transistorherstellungsverfahren
CN95120590A CN1093687C (zh) 1994-12-26 1995-12-08 晶体管及其制造方法
GB9526141A GB2296817B (en) 1994-12-26 1995-12-21 A transistor and a method of manufacture thereof
JP7339626A JP2894680B2 (ja) 1994-12-26 1995-12-26 トランジスタ及びその製造方法

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US5693542A (en) 1997-12-02
GB9526141D0 (en) 1996-02-21

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