CN1131344A - 晶体管及其制造方法 - Google Patents

晶体管及其制造方法 Download PDF

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CN1131344A
CN1131344A CN95120590A CN95120590A CN1131344A CN 1131344 A CN1131344 A CN 1131344A CN 95120590 A CN95120590 A CN 95120590A CN 95120590 A CN95120590 A CN 95120590A CN 1131344 A CN1131344 A CN 1131344A
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insulating barrier
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CN1093687C (zh
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徐祯源
卢光明
黄圣敏
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SK Hynix Inc
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Abstract

一种形成晶体管的方法，包含以下各步骤：在一块衬底内形成深槽；使绝缘层填入除上部外的所述深槽的下部中；使导电层填入所述深槽上部暨所述绝缘层之上，作为所述晶体管的沟道；在所得结构上形成栅氧化层；以及在所述栅氧化层上形成栅电极；以及使杂质离子注入到所述衬底中，形成源、漏区。

Description

晶体管及其制造方法
本发明涉及一种带有SOI(绝缘体基外延硅(Silicon-On-Insu-lator))结构的晶体管及其制造方法。
带有SOI结构的晶体管一般包括在一块衬底上形成氧化层的步骤以及在其下已形成氧化层的硅衬底上形成晶体管的步骤。带有SOI结构的晶体管改善了器件的特性，在于使源、漏结层的电容减至最小。
另一方面，因其尺寸按比例缩小的晶体管使短沟道效应和热载流子效应增加，为了改善这些效应就要按晶体管规模和LDD(轻掺杂漏)结构理论来设计该晶体管。
在深亚微米晶体管中，尽管对晶体管开发了一些改进，但由于短沟道效应，例如穿通使晶体管的工作特性变坏。
本发明的目的在于，提供一种能防止产生短沟道效应(尤其是，PMOS晶体管的穿通)并能改善其工作特性的晶体管及其制造方法。
根据本发明，形成一种晶体管的方法包含以下各步骤：在一块衬底上形成一深槽；将绝缘层填入除该深槽上部以外的该深槽的下部；将导电层填入所说的深槽的上部暨所说的绝缘层之上，作为所说的晶体管的沟道；在所得结构上形成栅氧化层；在所说的栅氧化层上形成栅电极；以及使杂质离子注入到所说衬底内形成源、漏区。
根据本发明，形成一种晶体管的方法包含以下各步骤：在一块衬底上形成轻掺杂层；在所说的轻掺杂层上形成第一绝缘层并使所说的第一绝缘层构图；用所说的已构图的第一绝缘层作腐蚀掩模来腐蚀所说的轻掺杂层和所说的衬底，在所说的衬底内形成深槽；将第二绝缘层填入所说深槽除上部以外的下部内，其中的所说的第二绝缘层的选择腐蚀速率远低于所说的第一绝缘层的选择腐蚀速率；将导电层填入所说的深槽的上部之内暨所说的第二绝缘层之上，作为所说的晶体管的沟道；去掉所说的第一绝缘层；在所得结构上形成栅氧化层；在所说的栅氧化层上形成栅电极；以及使杂质离子注入到所说的衬底内形成源、漏区。
根据本发明，形成一种晶体管的方法包含以下各步骤：在一块衬底上依次形成第一和第二绝缘层；使所说的第一和第二绝缘层构图，露出所说的衬底；用所说的已构图的第二绝缘层作腐蚀掩模在所说的衬底内形成深槽；通过氧化所说的裸露的衬底使氧化层充满所说的深槽；去掉所说的第二绝缘层；深腐蚀所说的氧化层，在所说的深槽的下部留下剩余部；将导电层填入所说的深槽的上部暨所说的氧化层之上，作为所说的晶体管的沟道；去掉所说的第一绝缘层；在所得结构上形成栅氧化层；在所说的栅氧化层上形成栅电极；以及使杂质离子注入到所说衬底形成源、漏区。
根据本发明，一种具有在衬底上的栅绝缘层，栅电极和源、漏区的晶体管包含：在所说的源区和所说的漏区之间的所说的衬底之内所形成的深槽；填入所说的深槽下部的绝缘层；填在所说的深槽的上部暨所说的绝缘层之上的用以形成所说晶体管沟道的硅层；因而所说的绝缘层是形成在所说的晶体管的沟道之下，改善了其穿通特性。
参照如下的附图，可使本领域的技术人员对本发明有更好的理解，其目的和优点将变得更加明显。
图1A～1J是表明根据本发明的一个实施例形成晶体管的方法的剖面图。
图2A～2I是表明根据本发明的另一实施例形成晶体管的方法的剖面图。
图3A～3H是表明根据本发明的又一实施例形成晶体管的方法的剖面图。
以下，参照附图将描述本发明。
首先，参照附图1A～1J描述本发明的一实施例。
如图1A所示，在一块硅衬底101上淀积氧化层102，再经掩模工艺腐蚀掉氧化层102的一部分，在该硅衬底101内进行形成深槽的腐蚀工艺。
如图1B所示，为了形成其宽度比经图1A的掩模工艺的氧化层图形的宽度还窄的深槽，在氧化层102的侧壁上形成氧化调宽层103，并用氧化层102所氧化调宽层103作腐蚀掩模，通过裸露的硅衬底101的腐蚀形成深槽104。因为氧化调宽层103是用来减小深槽104的宽度的，所以根据制作条件可以省略形成该氧化调宽层103的步骤。
如图1C所示，去掉硅衬底101上剩余的氧化层102和103，再在所得结构上形成氧化层105(即第三氧化层)，以此填入深槽104中。
接着，如图1D所示，深腐蚀氧化层105，只留下深槽104内的氧化层105′。另外，必须控制腐蚀速率，以便能在深槽104内形成自硅衬底101的表面至氧化层105′的表面的深度“d”。该深度“d”是为形成MOS晶体管的沟道所需要的，这一点将在以下工艺中给以描述。
参照图1E，在所得结构上形成多晶硅层106，填入尚未被氧化层105′填充的深槽104内。该多晶硅层106也可用硅层替代。
如图1F所示，用常规半导体工艺中所用的氧化工艺来氧化硅衬底101表面上的多晶硅106。经该氧化工艺就形成了氧化层107，而留下在深槽104内的自硅衬底101的表面至氧化层105′表面的多晶硅层106′。此时的多晶硅106′起着衬底的作用。
去掉氧化层107，再进行离子注入，以调节晶体管的阈值电压，如图1G所示。
图1H表明依次形成氧化层108和作为栅电极的多晶硅层109的步骤。
图1I表明使氧化层108和多晶硅层109按预定的尺寸构图，而形成栅氧化层108′和栅电极109′的步骤。
最后，如图1J所示，经离子注入形成源、漏区110。
如上所述，为了改善晶体管的穿通特性，根据本发明一实施例，该晶体管有硅衬底101内形成氧化层105′和多晶硅106′是有别于常规晶体管。
现在，参照图2A～2I描述本发明的另一实施例。
如图2A所示，使低浓度离子(n-或p-)，其杂质类型不同于衬底201的导电类型，注入到硅衬底201中，于是在硅衬底201上就形成了掺杂区202。
如图2B所示，在掺杂区202上形成氮化层203，再用掩模工艺和腐蚀工艺使氮化层203构图，以便露出硅衬底201的一部分。
如图2C所示，用氮化层203作腐蚀掩模，通过对掺杂层202和被暴露的硅衬底201的腐蚀形成深槽204。当然，可以使用图1B所示的氧化调宽层来减小深槽204的宽度。在形成深槽204之后，在所得结构上形成氧化层205，以此填入深槽204。
接着，如图2D所示，深腐蚀氧化层205，只留下深槽204内的氧化层205′。另外，必须控制腐蚀速率，以便能在深槽204内形成自硅衬底201的表面至氧化层205′的表面的深度“d”。该深度“d”是为形成MOS晶体管的沟道所需要的，这点将在下面的工艺中加以描述。
现在参照图2E，在所得结构上形成多晶硅206，填入尚未被氧化层205′填充的深槽204内。
如图2F所示，深腐蚀多晶硅层206，以使仅在深槽204内形成起衬底作用的多晶硅层206′，再进行离子注入，以调节晶体管的阈值电压。
图2G表明依次形成氧化层207和作为栅电极的多晶硅层208的步骤，图2H表明按预定尺寸构成栅氧化层207′和栅电极208′图形的步骤。
最后，如图2I所示，经离子注入形成重掺杂的源、漏区209。
如上所述，此实施例表明，由掺杂区202完成了在图1J的SOI结构上具有LDD结构的晶体管。
此外，参照图3A～3H，描述本发明的又一实施例。
如图3A所示，在一块硅衬底301上依次淀积氧化层302和氮化层303，然后经掩模工艺和腐蚀工艺腐蚀掉氧化层302和氮化层303的一部分，以便在硅衬底301内形成一深槽。
如图3B所示，为了形成其宽度比经图3A的掩模工艺构成的氧化层和氮化层图形的宽度还窄的深槽，在氧化层302和氮化层303的侧壁上形成氮化调宽层304。
如图3C所示，用氮化层303和氮化调宽层304作腐蚀掩模，经对裸露的硅衬底的腐蚀而形成一深槽305。当然，因为氮化调宽层304是用来减小深槽305的宽度的，因而可以根据制造条件，如图1B所示，而省略形成该氮化调宽层304的步骤。
接着，如图3D所示，用氮化层303和氮化调宽层304作氧化掩模，使裸露的衬底301氧化，以便在深槽305内形成氧化层306。
在去掉氮化层303和氮化调宽层304之后，深腐蚀氧化层306，只留下深槽305内的氧化层306′，如图3E所示。此时，应控制腐蚀速率，以便在深槽内形成自硅衬底301表面至氧化层306′表面的深度“d”。该深度“d”是形成MOS晶体管的沟道所需要的，这点将通过下述工艺来描述。
参照图3F，对裸露的硅衬底301实施外延工艺，以使硅层307填入尚未被氧化层306′填充的深槽305内。在形成硅层307之后，用氧化层302作离子注入掩模，使控制阈值电压的杂质离子注入到硅层307内。
如图3G所示，在经外延工艺生长的多晶硅层307上形成栅氧化层308，再在所得结构上形成作为栅电极的多晶硅层309。
参照图3H，按预定尺寸构成多晶硅层309′和氧化层302的图形，再经离子注入形成源、漏区310。
如上所述，本发明可有效地形成带有SOI结构的晶体管，更具体地讲，改善了具有短沟道、在该沟道下形成有绝缘层，因而对晶体管工作的稳定性有作用的PMOS晶体管的穿通特性。
按照法则，已对本发明在结构上和方法上的特点用文字在不同程度上作了具体地描述。但应予理解，虽然本文所公开的措施包括使发明付诸实践的优选形式，但本发明不限于图示和描述的具体特点。所以请求本发明以根据等同原则在适当解释所附权利要求的固有范畴内的任何形式或任何改型都得以保护。

Claims (21)

1、一种形成晶体管的方法，包含以下各步骤：
在一块衬底内形成一深槽；
使绝缘层填入除上部以外的所述深槽的下部中；
使导电层填入所述深槽上部中暨在绝缘层之上，作为所述晶体管的沟道；
在所得的结构上形成栅氧化层；
在所述栅氧化层上形成栅电极；以及
使杂质离子注入到所述衬底中，形成源、漏区。
2、根据权利要求1的方法，其中使导电层填入所述深槽上部中暨在所述绝缘层之上的步骤还包含使杂质离子注入到所述导电层中来调节阈值电压的步骤。
3、根据权利要求1的方法，其中形成所述深槽的步骤包含以下步骤：
在所述衬底上形成第一氧化层；
使所述第一氧化层构成图形；
在所得结构上形成第二氧化层；
对所述第二氧化层施实均厚腐蚀工艺，以便形成调宽氧化层；以及
用所述第一氧化层和所述调宽氧化层作腐蚀掩模，腐蚀所述衬底。
4、根据权利要求1的方法，其中使所述绝缘层填入所述深槽的下部的步骤包含以下各步骤：
在带有所述深槽的所述衬底上形成第三氧化层；以及
深腐蚀所述第三氧化层，使其剩余部分留在所述深槽下部。
5、根据权利要求1的方法，其中使所述导电层填入所述深槽上部的步骤包含：
在所得结构上形成硅层，填入所述深槽的上部暨所述绝缘层之上；
氧化所述衬底上面的所述硅层；以及
去掉所述已氧化的硅层。
6、根据权利要求5的方法，其中所述的硅层是由多晶制成的。
7、一种形成晶体管的方法，包含以下各步骤：
在一块衬底上形成轻掺杂层；
在所述轻掺杂层上形成第一绝缘层，再使所述第一绝缘层构成图形；
用所述已构图的第一绝缘层作腐蚀掩模，经对所述轻掺杂层和所述衬底进行腐蚀，在衬底内形成深槽；
使第二绝缘层填入除深槽上部以外的所述深槽的下部中，其中所述第二绝缘层的选择腐蚀速率远远小于所述第一绝缘层的选择腐蚀速率；
使导电层填入所述深槽的上部中暨所述第二绝缘层上，作为所述晶体管的沟道；
去掉所述第一绝缘层；
在所得结构上形成栅氧化层；
在所述栅氧化层上形成栅电极；以及
使杂质离子注入到所述衬底，形成源、漏区。
8、根据权利要求7的方法，其中使导电层填入所述深槽的上部中暨所述第二绝缘层之上的步骤还包含使杂质离子注入到所述导电层中以调节阈值电压的步骤。
9、根据权利要求7的方法，其中所述的第一绝缘层是氮化层。
10、根据权利要求7的方法，其中所述的第二绝缘层是氧化层。
11、根据权利要求7的方法，其中在所述衬底中形成所述深槽的步骤还包含在所述已构图的第一绝缘层的侧壁上形成调宽氮化层的步骤。
12、根据权利要求7的方法，其中使所述绝缘层填入所述深槽的下部的步骤包含以下各步骤：
在所得结构上形成氧化层；以及
深腐蚀所述第一氧化层，使剩余部分留在所述深槽的下部。
13、根据权利要求7的方法，其中使所述导电层填入所述深槽的上部的步骤包含以下各步骤：
在所得结构上形成硅层，填入所述深槽的上部；
氧化在所述衬底上面的所述硅层；以及
去掉所述已氧化的硅层。
14、根据权利要求13的方法，其中所述的硅层是由多晶制成的。
15、一种形成晶体管的方法，包含以下各步骤：
在一块衬底上依次形成第一和第二绝缘层；
使所述第一和第二绝缘层构成图形，露出所述衬底；
用所述已构图的第二绝缘层作掩模，在所述衬底内形成深槽；
经使所述裸露的衬底氧化，使氧化层填充于所述深槽内；
去掉所述第二绝缘层；
深腐蚀所述氧化层，使剩余部分留在所述深槽的下部；
使导电层填入所述深槽上部暨所述氧化层之上，用作所述晶体管的沟道；
去掉所述第一绝缘层；
在所得结构上形成栅氧化层；
在所述栅氧化层上形成栅电极；以及
使杂质离子注入到所述衬底中，形成源、漏区。
16、根据权利要求15的方法，其中使导电层填入所述深槽上部暨所述绝缘层之上的步骤还包含使杂质离子注入到导电层中以调节阈值电压的步骤。
17、根据权利要求15的方法，其中所述的导电层是外延层。
18、根据权利要求15的方法，其中所述的第一绝缘层是氧化层。
19、根据权利要求15的方法，其中所述的第一绝缘层是氮化层。
20、根据权利要求15的方法，其中使所述第一和第二绝缘层构成图形露出所述衬底的步骤还包含在所述第一和第二绝缘层的侧壁上形成调宽氮化层的步骤。
21、一种具有在衬底上的栅绝缘层、栅电极及源、漏区的晶体管，包括：
在介于所述源区和漏区之间的所述衬底中所形成的深槽；
填入所述深槽的下部的绝缘层；以及
填充到所述深槽上部暨所述绝缘层之上的用来形成所述晶体管的沟道的硅层；
因而使所述绝缘层形成在所述晶体管沟道的下方，改善了其穿通特性。
CN95120590A 1994-12-26 1995-12-08 晶体管及其制造方法 Expired - Fee Related CN1093687C (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102479706A (zh) * 2010-11-24 2012-05-30 中芯国际集成电路制造(北京)有限公司 晶体管及其制作方法
CN108417632A (zh) * 2017-02-10 2018-08-17 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3762136B2 (ja) 1998-04-24 2006-04-05 株式会社東芝 半導体装置
FR2791178B1 (fr) * 1999-03-19 2001-11-16 France Telecom NOUVEAU DISPOSITIF SEMI-CONDUCTEUR COMBINANT LES AVANTAGES DES ARCHITECTURES MASSIVE ET soi, ET PROCEDE DE FABRICATION
US6683345B1 (en) 1999-12-20 2004-01-27 International Business Machines, Corp. Semiconductor device and method for making the device having an electrically modulated conduction channel
JP2002134634A (ja) * 2000-10-25 2002-05-10 Nec Corp 半導体装置及びその製造方法
DE10122064A1 (de) * 2001-05-07 2002-11-21 Infineon Technologies Ag Verfahren und Vorrichtung zur Herstellung eines Wafers mit zumindest teilweise mit einer Schutzschicht versehenen Vertiefungen
KR100493018B1 (ko) * 2002-06-12 2005-06-07 삼성전자주식회사 반도체 장치의 제조방법
KR100473476B1 (ko) * 2002-07-04 2005-03-10 삼성전자주식회사 반도체 장치 및 그 제조방법
KR100558041B1 (ko) * 2003-08-19 2006-03-07 매그나칩 반도체 유한회사 반도체 소자의 트랜지스터 및 그 제조 방법
JP2005257778A (ja) * 2004-03-09 2005-09-22 Alps Electric Co Ltd 微細格子作製方法
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132998A (en) * 1977-08-29 1979-01-02 Rca Corp. Insulated gate field effect transistor having a deep channel portion more highly doped than the substrate
JPS59138377A (ja) * 1983-01-28 1984-08-08 Agency Of Ind Science & Technol Ｍｉｓトランジスタ及びその製造方法
EP0164094A3 (en) * 1984-06-08 1987-02-04 Eaton Corporation Isolated bidirectional power fet
FR2566179B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement
JPS62165364A (ja) * 1986-01-17 1987-07-21 Nec Corp 半導体装置
JPH0779127B2 (ja) * 1989-12-27 1995-08-23 株式会社半導体プロセス研究所 半導体装置の製造方法
JPH04291956A (ja) * 1991-03-20 1992-10-16 Fujitsu Ltd 半導体記憶装置の製造方法
KR960005553B1 (ko) * 1993-03-31 1996-04-26 현대전자산업주식회사 필드산화막 형성 방법
US5362669A (en) * 1993-06-24 1994-11-08 Northern Telecom Limited Method of making integrated circuits
US5494837A (en) * 1994-09-27 1996-02-27 Purdue Research Foundation Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102479706A (zh) * 2010-11-24 2012-05-30 中芯国际集成电路制造(北京)有限公司 晶体管及其制作方法
CN102479706B (zh) * 2010-11-24 2014-04-02 中芯国际集成电路制造(北京)有限公司 晶体管及其制作方法
CN108417632A (zh) * 2017-02-10 2018-08-17 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

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