CN1047872C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1047872C
CN1047872C CN96106746A CN96106746A CN1047872C CN 1047872 C CN1047872 C CN 1047872C CN 96106746 A CN96106746 A CN 96106746A CN 96106746 A CN96106746 A CN 96106746A CN 1047872 C CN1047872 C CN 1047872C
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朴賛光
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Abstract

一种半导体器件及其制造方法，其中在第二硅基片的边缘部分上形成厚的侧壁氧化膜或多晶硅层。在氧化膜或多晶硅层的侧壁上，有效半导体基片在其边缘部分的厚度增加了，由此在该边缘部分获得提高的阈值电压。即，通过实施侧壁氧化膜的形成来防止半导体器件栅氧化膜直接形成在有效硅基片的每侧壁上。结果，可防止因由有效半导体基片在其边缘部分的厚度减小而导致阈值电压下降所引起的电性能的下降。

Description

半导体器件及其制造方法
本发明涉及具有绝缘层上硅(SOI)结构半导体器件及其制造方法，特别是涉及制造一种半导体器件的方法，在该半导体器件中，在绝缘膜的边缘形成侧壁氧化物膜或多晶硅层，该绝缘膜适用于把半导体器件的有效半导体基片的侧壁同半导体器件的栅氧化膜相绝缘。
在半导体器件的制造中，SOI结构的形成涉及在相邻元件间获得绝缘，由此获得优良的电特性。通过在下硅基片上形成硅氧化膜作为绝缘层和在硅氧化膜上形成另一个硅基片(将被用作为有效基片)，例如单晶硅层来制成SOI结构。
参照图1A和1B描述现有的SOI结构。
图1A是表示具有SOI结构的金属氧化物硅场效应晶体管(MOSFET)的构型的示图。在图1A中表示出了用于硅基片(未示出)上的有源区1和栅电极2的掩模的各个位置。
图1B是沿图1A的I—I线剖开的截面图。硅氧化膜4淀积在硅基片3上。在硅氧化膜4上形成具有梯形截面结构。在生成的结构的所需部分上顺序形成栅氧化膜6和栅电极7。
如图1B所示，第二硅基片5具有倾斜结构，其中，其在有源区边缘处的厚度小于其在有源区中部的厚度。由于这种结构，耗尽区被限于第二硅基片5的厚度上。结果，耗尽块的电荷QB受到第二硅基片5的厚度的限制，由此减小了半导体器件的阀值电压，如下列等式所表示：
VT＝VFB＋QB/COX……(1)
COX＝εOX/tOX
其中，VT代表阈值电压，VFB代表平带电压，QB代表块电荷，COX代表氧化膜的电容，εOX代表氧化膜的介电常数，tOX代表栅氧化膜的厚度。
等式(1)表示：即使当在该部分上的掺杂率升高也不可能提高在第二硅基片5的下边缘部8处的阈值电压。这意味着，在第二硅基片5的中部和边缘部分之间在阈值电压上存在差值。如图2所示，当漏电流随着栅电压的变化而变化时，漏电流特性就会存在转折点。其结果，就难于控制具有SOI结构的半导体器件的阈值电压。进而，SOI元件的特性取于第二硅基片的边缘形状。这引起了半导体器件的特性上的很大变化。
因此，本发明的目的就是为了解决上述问题而提供一种半导体器件及其制造方法，其中在第二硅基片的边缘部分形成厚的侧壁氧化膜或多晶硅膜，由此提高该部分的阈值电压。
根据本发明的一个方案，具有绝缘层上硅结构的半导体器件包括：第一硅基片；在第一硅基片上形成的第一硅氧化膜；具有形成在有源区的第一硅氧化膜上的梯形截面结构的第二硅基片；在第二硅基片的每个侧壁上形成的侧壁绝缘膜；在第二硅基片的需要区域形成栅氧化膜；在栅氧化膜上形成的栅电极；分别被确定在第二基片的不同栅极相重叠的部分上的源/漏掺杂扩散区。
侧壁绝缘膜由掺入了具有与第二硅基片的相反的导电类型的杂质离子的材料所制成。掺杂区可以被确定在第二硅基片的侧壁与侧壁绝缘膜之间。侧壁多晶硅层也可以置入在第二硅基片的侧壁与侧壁绝缘膜之间。
根据本发明的另一个方案，具有绝缘层上硅结构的半导体器件包括：第一硅基片；在第一硅基片上形成的第一硅氧化膜；具有形成在有源区的第一硅氧化膜上的梯形截面结构的第二硅基片；在第二硅基片的每个侧壁上形成的侧壁氧化膜；在侧壁氧化膜上形成的侧壁多晶硅膜，该侧壁多晶硅膜具有与第二硅基片相反的导电类型；在第二硅基片的所需部分上形成的栅氧化膜；在栅氧化膜上形成的栅电极；分别确定在第二基片的不与栅电极相重叠的部分上的源/漏掺杂扩散区。
根据本发明的另一个方案，用于制造具有绝缘层上硅结构的半导体器件的方法包括下列步骤：在第一硅基片上淀积第一硅氧化膜，然后在第一硅氧化膜上淀积硅基片层；使硅基片层构图，由此形成具有梯形截面结构并布置在有源区的第一硅氧化膜上的第二硅基片；在第二硅基片的每个侧壁上形成掺入了具有不同于第二硅基片的导电类型的杂质离子的侧壁绝缘膜；使侧壁绝缘膜退火以把掺在侧壁绝缘膜中的杂质离子扩散到第二硅基片的侧壁中，由此形成掺杂区；依次在第二硅基片的所需部分上形成栅氧化膜和栅电极；把高浓度杂质离子注入第二基片的不与栅电极重叠的部分，由此形成源/漏掺杂扩散区。
根据本发明的又一个方案，用于制造具有绝缘层上硅结构的半导体的方法包括下列步骤：在第一硅基片上淀积第一硅氧化膜，然后在第一硅氧化膜上淀积硅基片层，对硅基片层构图，由此形成具有梯形截面结构并布置在有源区的第一硅氧化膜上的第二硅基片；在第二硅基片的形成之后在所得到的生成结构上淀积掺入了杂质离子的绝缘膜和多晶硅层；各向异性地刻蚀多晶硅层和绝缘膜，由此形成分别形成在第二硅基片的相对侧壁上的侧壁氧化膜和侧壁多晶硅层；依次在第二硅基片的所需部分上形成栅氧化膜和栅电极；把高浓度的杂质离子注入第二基片的不与栅电极相重叠的部分，由此形成源/漏掺杂扩散区。
侧壁多晶硅层由掺入了具有与第二硅基片相反导电类型的杂质离子的材料制成。淀积掺杂多晶硅层的步骤可以由在绝缘膜上淀积未掺杂多晶硅层并然后把杂质离子注入未掺杂多晶硅层中的步骤所构成。
根据本发明，由在第二硅基片的边缘上厚厚地形成了侧壁氧化膜或多晶硅层，就能在第二硅基片的边缘上获得提高的阈值电压。
下面通过参照附图对实施例的描述可以更清楚地了解本发明其他目的和方案。
图1A是表示具有现有SOI结构的MOSFET的构型的示图；
图1B是沿图1A的I—I线剖的截面图；
图2是表示具有现有SOI结构的MOSFET的工作特性的曲线图；
图3A至3E表示根据本发明第一实施例的制造具有SOI结构的MOSFET的方法的连续步骤的截面图；
图4是沿图1的II—III线剖的截面图，但表示的是根据图3A至3E的方法而制造的MOSFET；
图5是类似于图4的示图，表示根据本发明的第二实施例的具有SOI结构的MOSFET；
图6是类似于图4的示图，表示根据本发明的第二实施例的具有SOI结构的MOSFET。
图3A至3E和图4表示根据本发明第一实施例的制造具有SOI结构的MOSFET的方法。
根据该方法，首先制备第一硅基片11，然后如图3A所示，依次形成第一硅氧化膜12和第二硅基片13。
然后使用可以是图1A所示的有效区掩模的一个掩模来各向异性地刻蚀第二硅基片13，以使其成为具有图3B所示的倾斜侧壁的梯形图形。
然后在图3B所示的生成结构上淀积第二硅氧化膜18，如图3C所示那样。
以后，各向异性地刻蚀第二硅氧化膜18，由此分别在第二硅基片13的倾斜侧壁上形成侧壁硅氧化膜16，以便于在第二硅基片12的每个侧壁的边缘获得提高的阈值电压，如图3D所示。
然后如图3E所示，在生成结构的所需部分上形成栅氧化膜14。再在栅氧化膜14上形成栅电极15。
使用栅氧化膜14和栅电极15作为一个掩模，杂质离子被高浓度地注入到第二硅基片13的不与栅电极15重叠的部分中，由此在第二硅基片13中形成源/漏掺杂扩散区17。图4表示出生成结构。图4是沿图1A的II—III线剖的截面图，而图3E是沿图1A的I—I线剖的截面图。
该结构分别在使用绝缘膜的第二硅基片的边缘上具有侧壁膜。因此，可以通过增加绝缘膜的厚度来获得提高的阈值电压，这可以从等式(2)中看出(在等式(2)中，tOX＝cOX·εOX)。
图5表示根据本发明的第二实施例的具有SOI结构的MOSFET。
如图5所示，通过在第一硅基片21上首先淀积第一硅氧化膜22而形成该结构。具有梯形截面结构的第二硅基片23然后形成在第一硅氧化膜22上。使用例如磷硅酸玻璃(PSG)或硼硅酸玻璃(BSG)的材料，在第二硅基片23的每个侧壁上形成侧壁绝缘膜29。为了在第二硅基片23的边缘上获得提高的阈值电压，则以800℃至1，100℃的温度范围来使侧壁绝缘膜29退火。通过退火，在侧壁绝缘膜29中的杂质离子被扩散到第二硅基片23的侧壁中，由此，形成的掺杂区30分别沿着第二硅基片23的侧壁延伸到所需深度。然后在生成结构的所需部分上形成栅氧化膜24。再在栅氧化膜24上形成栅电极25。
根据这实施例，侧壁绝缘膜29具有与第二硅基片23相反的导电类型。其退火步骤以同栅电极25形成后的用于源/漏掺杂扩散区的退火步骤同时进行。
另一方面，图6表示根据本发明第三实施例的具有另一个SOI结构的MOSFET。
如图6所示，通过在第一硅基片31上首先淀积第一硅氧化膜32而形成该结构。然后在第一硅氧化膜32上形成具有梯形截面结构的第二硅基片33。之后，在第二硅基片33上依次淀积掺入了具有与第二硅基片33相反导电类型的杂质离子的氧化膜和多晶硅层。接着，以在第二硅基片33的两侧壁上仅留下其的方式来非均质地刻蚀氧化膜和多晶硅层。结果，在第二硅基片33的两侧壁上分别形成侧壁氧化膜40和侧壁多晶硅层39。然后在生成结构的所需部分上形成栅氧化膜34。再在栅氧化膜34上形成栅电极35。
可以使用未掺杂的多晶硅层来代替该掺杂的多晶硅层。在此情况下，将接着把杂质离子掺入未掺杂的多晶硅层。
如从上述所了解的，根据本发明在第二硅基片上厚厚地形成侧壁氧化膜或侧壁多晶硅层。因此，能在第二硅基片的边缘获得提高的阈值电压。换句话说，实现侧壁氧化膜的形成是为了防止栅氧化膜直接形成在第二硅基片的每个侧壁上。结果，就能防止因阈值电压的下降而造成的电特性的下降。
虽然为了说明而描述本发明的优选实施例，但本领域普通技术人员在不背离权利要求所描述的内容及范围的条件下可以进行各种改型、添加和代换。

Claims (10)

1.一种具有绝缘层上硅结构的半导体器件，包括：
第一硅基片；
在第一硅基片上形成的第一硅氧化膜；
具有形成在有源区的第一硅氧化膜上的梯形截面结构的第二硅基片；
该半导体器件的特征在于：
在第二硅基片的每个侧壁上形成的侧壁绝缘膜；
在第二硅基片的所需部分上形成的栅氧化膜；
在栅氧化膜上形成的栅电极；和
分别确定在第二基片的不与栅电极重叠的部分中的源/漏掺杂扩散区。
2.根据权利要求1的半导体器件，其特征在于侧壁绝缘膜由掺入了具有与第二硅基片相反导电类型的杂质离子的材料所制成。
3.根据权利要求1的半导体器件，其特征在于进一步包括确定在第二硅基片的侧壁和侧壁绝缘膜之间的掺杂区。
4.根据权利要求1的半导体器件，其特征在于进一步包括：置入第二硅基片的侧壁和侧壁绝缘膜之间的侧壁多晶硅层。
5.根据权利要求1的半导体器件，其特征在于还包括形成在侧壁绝缘膜上的侧壁多晶硅膜，该侧壁多晶硅膜的导电类型与第二硅基片的导电类型相反。
6.用于制造具有绝缘层上硅结构的半导体器件的方法，包括下列步骤：
在第一硅基片上淀积第一硅氧化膜，然后在第一硅氧化膜上淀积硅基片层；
使硅基片层构图，由此形成具有梯形截面结构并布置在有源区的第一硅氧化膜上的第二硅基片；
在第二硅基片的每个侧壁上形成掺入了具有与第二硅基片不同导电类型的杂质离子的侧壁绝缘膜；
以把掺在侧壁绝缘膜中的杂质离子扩散到第二硅基片的侧壁中的方式使侧壁绝缘膜退火，由此形成掺杂区；
依次在第二硅基片的所需部分上形成栅氧化膜和栅电极；以及
在第二基片的不与栅电极重叠的部分中注入高浓度的杂质离子，由此形成源/漏掺杂扩散区。
7.根据权利要求6的用于制造具有绝缘层上硅结构的半导体器件的方法，还包括以下步骤：在侧壁绝缘膜上淀积掺杂的侧壁多晶硅膜，掺入的杂质离子的导电类型与第二硅基片的导电类型相反。
8.根据权利要求6的用于制造具有绝缘层上硅结构的半导体器件的方法，还包括以下步骤：在侧壁绝缘膜上淀积未掺杂的侧壁多晶硅膜；将其导电类型与第二硅基片的导电类型相反的杂质离子掺入到未掺杂的多晶硅膜中。
9.根据权利要求6的用于制造具有绝缘层上硅结构的半导体器件地，其中退火步骤在800℃到1000℃的温度范围内进行。
10.根据权利要求6的用于制造具有绝缘层上硅结构的半导体器件的方法，其中用于形成掺杂区的退火步骤可以与用于形成源/漏杂质扩散区的退火步骤同时进行。
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