CN100359701C - 具有改进的驱动电流特性的晶体管及其制作方法 - Google Patents

具有改进的驱动电流特性的晶体管及其制作方法 Download PDF

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CN100359701C
CN100359701C CNB028179102A CN02817910A CN100359701C CN 100359701 C CN100359701 C CN 100359701C CN B028179102 A CNB028179102 A CN B028179102A CN 02817910 A CN02817910 A CN 02817910A CN 100359701 C CN100359701 C CN 100359701C
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semiconductor substrate
insulating barrier
drain electrode
source electrode
grid
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CN1555579A (zh
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J·P·斯尼德尔
J·M·拉森
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Spinnaker Semiconductor Inc
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Abstract

本发明致力于用于调节电流的器件及其制造方法,该器件具有高介电常数的栅绝缘层,其源极和/或漏极和衬底形成肖特基接触或类肖特基区域。在一个实施例中,栅绝缘层具有大于硅的介电常数。在另一个实施例中,电流调节器件可以是MOSFET器件,可任选的平面P型或N型MOSFET具有任何取向。在另一个实施例中,源和/或漏可以部分或全部由硅化物构成。

Description

具有改进的驱动电流特性的晶体管及其制作方法
技术领域
本发明涉及调节电流的器件及其制造方法。更具体地说,本发明涉及肖特基势垒源极和/或漏极晶体管。
背景技术
诸如图1中的现有技术半导体器件100(例如晶体管)的电流调节器件可以包括一个硅衬底110,该衬底带有掺杂的源极120和掺杂的漏极130。源极120和漏极130由一个沟道区域140分隔。沟道区域140的顶部是一个绝缘层150。绝缘层150通常由介电常数为3.9的二氧化硅构成。导电材料制成的栅极160位于绝缘层150的顶部。
当电压VG施加到栅极160上时,电流通过沟道区域140流过源极120和漏极120之间。该电流被称为驱动电流,或ID。对于数字应用,电压VG可以施加到栅极160上,使半导体器件100“导通”。在该状态下,半导体器件将有较大的驱动电流,理想情况下只受沟道区域140的电阻限制。可对栅极160施加不同的电压VG,使半导体器件100“截止”。在该状态,理想的漏电流为零。但是,在实际应用中,“导通”状态中的驱动电流不是理想的驱动电流,因为与该半导体器件100的其他部分有关的寄生阻抗。例如,源极和漏极区域有一个有限的阻抗,导致一个叠加到沟道区域电阻上的寄生阻抗。还有,在实际应用中,当半导体器件“截止”时存在一定有限量的漏电流。
在现有技术的电流调节器件中,驱动电流和绝缘层150的介电常数K成线性正比,和绝缘层150的厚度Tins成线性反比。驱动电流ID接近于关系式:
ID~K/Tins
式中K是绝缘层的介电常数,Tins是绝缘层的厚度。
在电流调节器件的设计中的一个考虑是减小达到要求驱动电流所需要的功率量。减小功耗的一个方法是通过应用金属源极和漏极以及一个简单的均匀注入的沟道掺杂剖面,如申请于1999年12月16日,申请号为09/465357,题为“具有肖特基势垒源极和漏极接触的短沟道FET的制造方法”,和申请于2001年2月6日,申请号为09/777,536,题为“MOSFET器件及其制造方法”的共同待批美国专利申请中叙述的那样,该申请的内容通过引用而结合在本文中。
电流调节器件的设计的另一个考虑是其制造性能。改进具有用高介电常数材料的栅绝缘层的电流调节器件的制造性能的一个方法是用诸如用于形成肖特基或类肖特基源极和漏极的低温工艺形成源极和漏极,如申请于2002年5月16日,申请号为60/381,320,题为“用于MOSFET器件制造的低温源极和漏极形成加工步骤”的美国临时专利申请中叙述的那样,该申请的内容通过引用而结合在本文中。
在技术上存在对用于调节电流的器件的需要,该器件表现出在“导通”状态下改进的驱动电流。在技术上进一步存在对在减低温度下制造这样的器件的方法的需要。
发明内容
通过应用本文揭示的本发明,可以改进驱动电流性能,导致驱动电流ID和绝缘层的介电常数K与绝缘层的厚度Tins两者之间的非线性关系。所得到的关系导致和现有技术相比对K和Tins的变化更敏感的电流调节器件。另外,通过应用本文揭示的本发明,新栅极绝缘层材料的制造性能得到实质性的改进。
在一个方面,本发明提供了一种制造用于调节电流的器件的方法。该方法包括的步骤有,提供一个半导体衬底;提供一个和该半导体衬底接触的电绝缘层,该绝缘层具有大于4.0的介电常数;提供和该绝缘层的至少一部分接触的栅极;和提供和该半导体衬底接触和靠近栅极的源极和漏极,其中至少源极和漏极之一和该半导体衬底形成肖特基接触或类肖特基区域。在一个方面,用于调节电流的器件可以是金属氧化物半导体场效应晶体管(MOSFET)器件。在另一方面,介电常数可以大于7.6或大于15。
在另一方面,源极和漏极可用由硅化铂,硅化钯和硅化铱构成的组中的一个形成。在另一方面,源极和漏极可用由多个稀土硅化物构成的组中的一个形成。在另一方面,绝缘层可用由多个金属氧化物构成的组中的一个形成。在另一方面,肖特基接触或类肖特基区域可以至少在相邻沟道的区域中。在另一方面,至少源极和漏极之一和半导体衬底之间的整个界面可以和半导体衬底形成肖特基接触或类肖特基区域。在另一方面,沟道区域可以掺杂。
在另一方面,本发明提供一种制造用于调节电流的器件的方法。该方法包括的步骤有,提供一个半导体衬底;提供一个和该半导体衬底接触的电绝缘层,该绝缘层具有大于4.0的介电常数;提供位于和该绝缘层的至少一部分接触的栅极;在一个或多个靠近栅极的区域暴露半导体衬底;在被暴露的半导体衬底的至少一部分上提供一层金属薄膜;和使该金属和暴露的半导体衬底反应而在半导体衬底上形成肖特基或类肖特基的源极和漏极。在一个方面,用于调节电流的器件可以是MOSFET器件。在另一个方面,介电常数可以大于7.6或大于15。
在另一方面,栅极可以用下述步骤提供:在绝缘层上淀积一层导电薄膜;对该导电薄膜加图形并刻蚀以形成栅极;在该栅极的一个或多个侧壁上形成一层或多层薄绝缘层。在另一方面,该方法可以包括去除在反应过程中没有反应的金属的步骤。在另一方面,该反应可以包括热退火。在另一方面,源极和漏极可用由硅化铂,硅化钯和硅化铱构成的组中的一个形成。在另一方面,源极和漏极可用由多个稀土硅化物构成的组中的一个形成。在另一方面,绝缘层可用由多个金属氧化物构成的组中的一个形成。在另一方面,肖特基接触或类肖特基区域可以至少在相邻沟道的区域中。在另一方面,至少源极和漏极之一和半导体衬底之间的整个界面可以和半导体衬底形成肖特基接触或类肖特基区域。在另一方面,掺杂物可以被引入沟道区域。
在另一方面,本发明提供一种用于调节电流的器件。该器件包括半导体衬底;栅极;位于该栅极和半导体衬底之间的电绝缘层,该绝缘层具有大于4.0的介电常数;和与半导体衬底接触并靠近栅极的源极和漏极,其中至少源极和漏极之一和半导体衬底形成肖特基接触或类肖特基区域。在一个方面,用于调节电流的器件可以是MOSFET器件。在另一个方面,介电常数可以大于7.6或大于15。
在另一个方面,源极和漏极可以用由硅化铂,硅化钯和硅化铱构成的组中的一个形成。在另一个方面,源极和漏极可以用由多个稀土硅化物构成的组中的一个形成。在另一个方面,绝缘层可以用由多个金属氧化物构成的组中的一个形成。在另一个方面,肖特基接触或类肖特基区域可以至少在相邻沟道的区域中。在另一个实施例中,至少源极和漏极之一和半导体衬底之间的整个界面可以和半导体衬底形成肖特基接触或类肖特基区域。在另一个发明,沟道区域可以掺杂。
本发明的各个方面可以包括一个或多个下述优点。常规的场效应晶体管(FET)和其他电流调节器件需要比根据本发明制造的器件更高的电压以产生从源极到漏极的相似的驱动电流。在一个优化的常规FET或电流调节器件中,驱动电流通常线性地随绝缘层的介电常数和其厚度的比而变化。本发明的一个优点是,驱动电流对介电常数K比对厚度Tins更敏感这样一个意料之外的结果,这意味着,对于更大的K和恒定的K/Tins之比要更大的驱动电流。这些结果通过将肖特基或类肖特基源和/或漏极和用高介电常数材料形成的绝缘层耦合而获得。更低的电压被用来产生高极至漏漏电流,导致采用该结构的微电子器件有更低的功耗。
另外,在本发明中仍然将看出通过应用更大的K和恒定的K/Tins之比获得较小的栅极漏电流(栅极和源/漏极之间)的众所周知的好处。对于常规结构的器件,该特定的好处是对极栅绝缘层使用有比其介电常数为3.9的二氧化硅更高的介电常数K的材料的唯一的原因。这些材料被称为“高K”材料。并不希望或看到其他显著的好处。通过使用结合更大的K的肖特基或类肖特基源极/漏极器件,除了减小栅极漏电流外,在驱动电流ID方面还得到意外的巨大的改进。
虽然因为栅极漏电流的问题而在工业上对采用新的高K栅绝缘材料有强烈的兴趣,但在技术还有障碍,使高K栅极绝缘层的生产更具挑战性。最重要的问题之一是在形成杂质掺杂的源极和漏极区域所需要的高温加工期间对高K栅绝缘层材料的降解(degradation)。这种降解由与诸如沟道区域的硅或栅极的邻近材料的反应引起。和形成杂质掺杂的源极和漏极需要的1000℃相比,用于形成肖特基或类肖特基源漏区域的工艺步骤在低得多的诸如400℃的温度下进行。作为用于形成肖特基或类肖特基源极和漏极区域的显著低温工艺步骤的结果,高K材料基本不会和邻近材料发生反应。因此,应用和高K栅极绝缘层材料相结合的肖特基或类肖特基源极/漏极器件的另一个好处,是高K栅极绝缘层的制造特性的改进。
虽然揭示了多个实施例,通过下文示出和叙述本发明的例示性的实施例的详尽叙述,对于在本技术领域熟练的人士而言,本发明的其他实施例是显而易见的。如将认识到的那样,对本发明在各个明显的方面能作出各种修改,所有的修改都不背离本发明的精神和范围。因此,附图和详尽叙述将被认为是性能上的说明而不是限制。
附图说明
图1是现有技术半导体晶体管的剖面图。
图2是带有肖特基接触源极和漏极、与栅极和沟道区域之间的非二氧化硅绝缘层相结合的半导体衬底的剖面图。
图3a是带有肖特基接触源极和漏极、与栅极和沟道区域之间的非二氧化硅绝缘层相结合的半导体器件的剖面图。这是用于数字模拟的器件结构。
图3b是示出在K/Tins比值保持恒定,对于各个K值驱动电流ID和栅电压VG之间的经模拟的关系的对数曲线图。
图3c是用和图3b相同数据的线性曲线图。
图4a是带有肖特基接触源极和漏极、与栅极和沟道区域之间的非二氧化硅绝缘层相结合的半导体器件的剖面图。这是用于第二组数字模拟的器件结构。
图4b是示出在K/Tins比值保持恒定、对于各个K值驱动电流ID和栅极电压VG之间的经模拟的关系的对数曲线图。
图4c是用和图4b相同数据的线性曲线图。
图5是在离子注入以后半导体衬底的剖面图。
图6是在绝缘层生长和栅图形形成以后半导体衬底的剖面图。
图7是在侧壁氧化层生长以后半导体衬底的剖面图。
图8是在产生金属硅化物源极和漏极以后半导体衬底的剖面图。
图9是由图10概述的工艺步骤产生的半导体器件的剖面图。
图10是概述用于制造根据本发明的用于调节电流的器件的工艺流程的流程图。
在各个附图中相同的参考标记指示相同的元件。
具体实施方式
参考图2,半导体器件200包括一个源极220和漏极230形成在其中的衬底210。衬底210可以由硅构成,或可以是硅-绝缘体(SOI)衬底。源220和/或漏230可以部分或全部由稀土硅化物构成。源极220和/或漏极230可以部分或全部由硅化铂,硅化钯或硅化铱构成。因为源极和漏极部分由金属构成,因此它们和衬底210形成肖特基接触或类肖特基区域270、275,其中“肖特基接触”由金属和半导体之间的接触定义,“类肖特基区域”是由半导体和金属的紧密靠近形成的区域。肖特基接触或类肖特基区域270、275可以通过用金属硅化物形成源极和/或漏极而形成。肖特基接触或类肖特基区域270、275在相邻于形成在源极220和漏极230之间的沟道区域的区域中。源极220和漏极230中的任何一个或两者之间的全部界面都可以和衬底210形成肖特基接触或类肖特基区域270、275。沟道区域240可以被掺杂,该掺杂可以是常规的非均匀掺杂,或可以是如共同待批的美国专利申请09/465,357和美国专利申请09/777,536中叙述的那样的均匀掺杂。
绝缘层250形成在沟道区域240顶部,并可以形成在部分或全部源极220和漏极230之上。绝缘层250由其介电常数大于二氧化硅的介电常数,例如介电常数大于3.9的材料构成。例如,绝缘层250可以由金属氧化物构成,诸如其介电常数约为25的TaO2,其介电常数约为50-60的TiO2,其介电常数约为15-20的HfO2,或其介电常数约为15-20的ZrO2构成。绝缘层250可以由带有适度K值(例如5-10)的电介质,诸如氮化物/氧化物或氮氧化物堆,中度K值(例如10-20)的电介质,诸如一元氧化物Ta2O3,TiO2,ZrO2,HfO2,Y2O3,La2O3,Gd2O3,Sc2O3,或硅化物ZrSiO4,HfSiO4,LaSiO4,TiSiO4,或高度K值(例如大于20)的电介质,诸如无定形LaAlO3,ZrTiO4,SnTiO4,或SrZrO4,或单晶LaAl3O4,BaZrO3,Y2O3,La2O3。可任选地,为了改进和过渡金属有关的制造性能问题,绝缘层250可以由一层以上构成。绝缘层250可以用“双层”法形成,可以用多于一种的电介质构成,例如Si3N4顶部的TiO2。栅极260位于绝缘层250的顶部。薄绝缘层225包围栅极260。
通过形成带有(1)和衬底110形成肖特基接触或类肖特基区域270、275的源极220或漏极230;和(2)具有较高介电常数绝缘层250,就能够得到对于较大的K有较大的驱动电流ID,但K/Tins恒定。
参考图3a-c,在图3a的MOSFET器件结构305上对各个绝缘层309厚度Tins和绝缘层介电常数K进行了全面的二维静电模拟。该模拟假设如下:
1)P型MOS半导体器件305,300K金属源极301/漏极303。
2)金属源极301/漏极303曲率半径R311为10nm。
3)沟道长度L313为25nm,漏极电压VD为1.2V。
4)在硅衬底315中没有明显的电荷,包括固定电荷和移动电荷。
5)漏极电流ID仅由半导体器件305的源极301端的发射过程限定。
6)源极301的发射过程的电流密度对电场(J对E)的特性在铂硅-硅肖特基接触之后进行模型模拟。肖特基势垒高度假设为0.187eV,在硅中空穴有效质量为0.66mo,费米能级5.4eV,温度300K。对于在源极301中一特定点处给定的电场强度,假定一维锐角三角形势垒,通过对薛定谔方程的完全非近似解,计算电流密度。量子隧道和反射效应被完全包括在内。因为全部电流密度是对状态密度的积分,故可计算出因场发射,热发射和热辅助的场发射而引起的电流。J对E的关系按照用于纯热发射情况(E=0)的实验数据被校准。
这些假设在短沟道(<25nm)和非掺杂(或轻掺杂)衬底的实际情况下是有效的。虽然经计算的源极301发射电流的绝对值未为E>0进行校准,但它们是基于一些实验数据和第一原理的计算。为了本发明的目的,因为主要关心是绝缘层309的厚度(Tins)307和介电常数(K)对源极301发射电流的影响,计算的J对E的数据是足够的。源极301发射电流随Tins与K的相对变化在本例中比电流的绝对值更相关。然而,漏电流和驱动电流二者的计算值和实际晶体管的测量数据很好地符合。
模拟在恒定的K/Tins比为0.156情况下进行。结果示于图3b-c中。从图3c开始,工作向上进行,曲线350表示绝缘层介电常数为3.9(Tins=25埃)的半导体器件中栅电压VG和驱动电流ID之间的关系。曲线360、370和380表示半导体器件中VG和ID的比,该半导体器件的源极220和漏极230和衬底形成肖特基接触或类肖特基区域270、275,绝缘层介电常数分别为10(Tins=64.1埃),25(Tins=160.3埃),和50(Tins=320.5埃)。参考图3b,曲线355表示绝缘层介电常数为3.9(Tins=25埃)的半导体器件中栅极电压VG和驱动电流ID的对数关系。曲线365、375和385表示半导体器件中VG和ID的对数比,该半导体器件的源极220和漏极230和衬底形成肖特基接触或类肖特基区域270、275,绝缘层介电常数分别为10(Tins=64.1埃)、25(Tins=160.3埃)和50(Tins=320.5埃)。可以预料,不考虑曲率半径R311,沟道长度313和漏极电压VD将得到相似的结果。分别对于曲线350/355、360/365、370/375和380/385,驱动电流和漏电流之比为35、38、53和86。通过在衬底中加入适当的掺杂(控制体击穿电流)或通过降低工作温度,漏电流可以至少降低到1/10,而不牺牲驱动电流。这样,通过应用和衬底形成肖特基接触或类肖特基区域的源极301和漏极303,以及通过增加K同时保持恒定的K/Tins比,驱动电流ID显著增加(从VG为1.2V的稍许超过300μA/μm到大约为1300μA/μm)。这样,对于要求的驱动电流,器件需要的工作电压将比现有技术要求的电压低得多。因为功耗随着电压的平方变化,本发明提供了显著低的功率应用。
为了验证曲率半径R311的变化不会改变已观测到的对ID的巨大改进,在稍许变化的器件几何尺寸上重复全二维的静电模拟。参考图4a-c,图4a的半导体器件405的结构被模拟为两绝缘层409厚度Tins407和绝缘层介电常数K,使得K/Tins比恒定。除了器件的几何尺寸以外,模拟假设和上述相同:
1)沟道长度L413为27nm。
2)源极和漏极的宽度402和高度404分别为100nm和30nm。
3)栅极的宽度412和高度413分别为67nm和108nm。
4)栅极的曲率半径Rg414对全部模拟都为10nm。
5)源极和漏极的曲率半径R411为1nm或10nm。
模拟在0.205的恒定的K/Tins比情况下进行。结果示于图4b-c。从图4c开始,曲线451和461示出半导体器件中栅极电压Vg和驱动电流ID之间的关系,该器件的曲率半径R411为10nm,绝缘层介电常数分别为3.9(Tins=25埃)和50(Tins=240埃)。继续参考图4c,曲线471和481示出半导体器件中栅极电压Vg和驱动电流ID之间的关系,该器件的曲率半径R411为1nm,绝缘层介电常数分别为3.9(Tins=25埃)和50(Tins=244埃)。参考图4b,曲线455和465示出半导体器件中栅极电压Vg和驱动电流ID之间的对数关系,该器件分别的曲率半径R411为10nm,绝缘层介电常数分别为3.9(Tins=25埃)和50(Tins=244埃)。继续参考图4b,曲线475和485示出半导体器件中栅极电压Vg和驱动电流ID之间的关系,该器件的曲率半径R411为1nm,绝缘层介电常数分别为3.9(Tins=25埃)和50(Tins=244埃)。图4b-c表示,通过应用和衬底形成肖特基接触或类肖特基区域的源极401或漏极403,以及通过增加K,同时保持恒定的K/Tins比,对于具有10nm的曲率半径R411的器件,驱动电流ID显著增加(对1.2V的Vg来说,从约650mA/mm到约1700mA/mm)。对从K=50到K=3.9情况来说,驱动电流之比为1700/650=2.6。同样,对于具有1nm的曲率半径R411的器件,驱动电流显著增加(对1.2V的Vg来说,从约570mA/mm到约2340mA/mm)。在该情况下,对从K=50到K=3.9来说,驱动电流之比为2340/570=4.1。该结果表明,对于更小的曲率半径R411,驱动电流ID的相对改善变得更大。另外,这些结果编码,与恒定的K/Tins比的情况相比,增加K/Tins比将导致驱动电流ID的更大改善。对于具有恒定的K/Tins比的K=3.9和K=50情况来说,常规的掺杂源极和漏极器件有大体相同的驱动电流ID
源极和漏极的角区域的剖面扫描电子显微图表明,和沟道区域相邻的源极421的顶角和漏极422的顶角的曲率半径接近1nm而不是10nm。图4a-c的模拟预测表明,对于所需要的驱动电流,通过应用和衬底形成肖特基接触或类肖特基区域的源极401和漏极403,以及通过应用高K介电栅绝缘材料,器件将比现有技术需要显著更低的电压工作。因为功耗随着电压的平方变化,本发明提供了显著低的功率应用。
上述用于调节电流的器件,例如平面P型或N型MOSFET,可以用图5-9所示的工艺形成并在图10中叙述。(注意平面MOSFET不需要在水平方向的平面,但可以假设为任何的平面取向。)参考图5和10,硅衬底310上生长一薄屏栅氧化层(screen oxide)323,衬底310有互相电气隔离晶体管的手段(905)。薄屏栅氧化层的可选厚度是200埃,其功能是作为沟道区域掺杂的注入掩模。然后把合适的沟道掺杂物种(例如对P型和N型器件分别为砷和铟)通过该屏栅氧化层323离子注入到硅中至预先确定的深度(例如1000埃)(910)。
参考图6和10,图5的屏栅氧化层323用氢氟酸除去(915),薄绝缘层450被生长或淀积在沟道区域340的至少一部分上(920)。该绝缘层可以由TiO2,TaO2或任何其他有如上所述的高介电常数的化合物构成。紧接该绝缘层的生长或淀积,淀积在原地重掺杂硅薄膜(930)。该硅薄膜最后将构成栅极。对于N型器件,该硅薄膜可以用磷掺杂,对P型器件,可用硼掺杂。然后用光刻技术和对绝缘层450有高度选择性的硅刻蚀使栅极形成图形(935)。
参考图7和10,一个可选厚度为约100埃的薄氧化层被形成在栅极的顶表面和侧壁(940)。然后部分氧化层通过各向异性的刻蚀被除去,以在水平平面510上暴露硅,同时在垂直表面上保留硅(945)。该步骤的作用是产生一栅极侧壁氧化层525并且电激活器件的栅极和沟道区域340中的掺杂剂。
参考图8和10,在全部表面上淀积金属为匀厚的薄膜,其可选厚度约为400埃(950)。该淀积的特定金属将取决于器件是N型或P型。对P型器件可用铂,对N型器件可用铒。然后把半导体器件600在规定的时间和规定的温度下退火,例如在400℃下45分钟。此温度大大低于通常形成掺杂源极和漏极所需的温度,该温度通常要高于800℃。在金属直接接触硅的地方,退火过程引起一个化学反应,将金属转化为金属的硅化物606。不和硅接触的金属不参加反应。
参考图9和10,用湿化学刻蚀除去未反应的金属616(960)。例如,如果淀积的金属为铂或铒,分别可用王水和硝酸来除去之。保留的硅化物电极就是源极620和漏极630。至此,用于调节电流的带有高介电常数绝缘层的肖特基器件完成,并用于对栅极460,源极620和漏极630的电接触。因为在本工艺中形成肖特基或类肖特基源极和漏极所需的温度大大低于形成掺杂源极和漏极区域620,630所需的温度,用于栅极绝缘层450的高K材料就极少有可能和相邻的材料反应,因此使该工艺比现有技术有高得多的可制造性。
已经叙述了本发明的若干实施例。但是,应该理解的是,可以进行各种修改而不背离本发明的精神和范围。例如,在权利要求中说明的半导体器件仅作为实例。应该理解的是,本发明的概念可用各种剖面应用到半导体器件中去。还有,虽然本发明对平面硅MOS晶体管进行了说明,但本发明可同样地应用到其他用于调节电流的器件中去。例如,建立在其他半导体衬底,诸如砷化镓GaAs,磷化铟InP,碳化硅SiC等上的器件。另外,该器件不要求对源极和漏极角有任何特定的曲率半径。还有,本发明不限制于任何特定的K/Tins比。因此,其他的实施例也在下述权利要求的范围内。
虽然结合较佳实施例对本发明进行了叙述,但在本技术领域熟练的人士将认识到,可在形式和细节上做出各种变化而不背离本发明的精神和范围。

Claims (20)

1.一种制造用于调节电流的器件的方法,其特征在于,所述方法包括:
提供半导体衬底;
提供和该半导体衬底相接触的电绝缘层,该绝缘层具有大于4.0的介电常数;
提供和该绝缘层的至少一部分相接触的栅极;和
提供和该半导体衬底相接触并靠近该栅极的源极和漏极,其中一沟道被限定于源极和漏极之间,并且至少源极和漏极中一电极和半导体衬底形成一个肖特基接触或类肖特基区域。
2.如权利要求1所述的方法,其特征在于,所述绝缘层具有大于7.6的介电常数。
3.如权利要求1所述的方法,其特征在于,所述绝缘层具有大于15的介电常数。
4.如权利要求1-3中的任何一项所述的方法,其特征在于,所述源极和漏极用由硅化铂,硅化钯和硅化铱和多个稀土硅化物构成的组中的一个形成。
5.如权利要求1-3中的任何一项所述的方法,其特征在于,所述绝缘层用由多个金属氧化物和多个氮氧化物构成的组中的一个形成。
6.如权利要求1-3中的任何一项所述的方法,其特征在于,所述肖特基接触或类肖特基区域至少在与沟道相邻的区域中形成。
7.如权利要求1-3中的任何一项所述的方法,其特征在于,掺杂剂被引入沟道区域。
8.如权利要求1-3中的任何一项所述的方法,其特征在于,所述绝缘层包括一个以上的层次。
9.如权利要求1-3中的任何一项所述的方法,其特征在于,提供和半导体衬底相接触的源极和漏极在低于800℃的工艺温度下进行。
10.如权利要求1-3中的任何一项所述的方法,其特征在于,所述源极和漏极由下述步骤提供:
在靠近栅极的一个或多个区域暴露半导体衬底;
在暴露的半导体衬底的至少一部分上制备一金属薄膜;和
将该金属和暴露的半导体衬底反应,使得在半导体衬底上形成肖特基或类肖特基源极和漏极。
11.如权利要求1-3中的任何一项所述的方法,其特征在于,所述栅极由下述步骤提供:
在绝缘层上淀积一个导电薄膜;
对该导电薄膜加图形并刻蚀以形成栅极;和
在该栅极的一个或多个侧壁上形成一层或多层薄绝缘层。
12.一种用于调节电流的器件,其特征在于,所述器件包括:
半导体衬底;
栅极;
位于栅极和半导体衬底之间的电绝缘层,该绝缘层具有大于4.0的介电常数;和
和半导体衬底相接触并靠近栅极的源极和漏极,其中一沟道被限定于源极和漏极之间,并且至少源极和漏极中一电极和半导体衬底形成肖特基接触或类肖特基区域。
13.如权利要求12所述的器件,其特征在于,所述绝缘层具有大于7.6的介电常数。
14.如权利要求12所述的器件,其特征在于,所述绝缘层具有大于15的介电常数。
15.如权利要求12到14中的任何一项所述的器件,其特征在于,所述源极和漏极用由硅化铂,硅化钯和硅化铱和多个稀土硅化物构成的组中的一个形成。
16.如权利要求12到14中的任何一项所述的器件,其特征在于,所述绝缘层用由多个金属氧化物和多个氮氧化物构成的组中的一个形成。
17.如权利要求12到14中的任何一项所述的器件,其特征在于,所述至少源极和漏极中一电极和半导体衬底之间的全部界面和半导体衬底形成肖特基接触或类肖特基区域。
18.如权利要求12到14中的任何一项所述的器件,其特征在于,所述肖特基接触或类肖特基区域至少在与沟道相邻的区域中形成。
19.如权利要求12到14中的任何一项所述的器件,其特征在于,掺杂剂被引入沟道区域。
20.如权利要求12到14中的任何一项所述的器件,其特征在于,其中绝缘层包括一个以上的层。
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US8022459B2 (en) 2011-09-20
JP2004538650A (ja) 2004-12-24
US20070007605A1 (en) 2007-01-11
US20050106821A1 (en) 2005-05-19
US6949787B2 (en) 2005-09-27
US7674680B2 (en) 2010-03-09
WO2003015181A1 (en) 2003-02-20
US20100213556A1 (en) 2010-08-26
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US20040171240A1 (en) 2004-09-02
US20030034532A1 (en) 2003-02-20

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