KR940002400B1 - 리세스 게이트를 갖는 반도체장치의 제조방법 - Google Patents

리세스 게이트를 갖는 반도체장치의 제조방법 Download PDF

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KR940002400B1
KR940002400B1 KR1019910007881A KR910007881A KR940002400B1 KR 940002400 B1 KR940002400 B1 KR 940002400B1 KR 1019910007881 A KR1019910007881 A KR 1019910007881A KR 910007881 A KR910007881 A KR 910007881A KR 940002400 B1 KR940002400 B1 KR 940002400B1
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gate
nitride film
forming
semiconductor substrate
semiconductor device
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신형순
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금성일렉트론 주식회사
문정환
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Priority to KR1019910007881A priority Critical patent/KR940002400B1/ko
Priority to JP4081426A priority patent/JP2826924B2/ja
Priority to DE4212829A priority patent/DE4212829C2/de
Priority to US07/883,857 priority patent/US5270257A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

내용 없음.

Description

리세스 게이트를 갖는 반도체장치의 제조방법
제1도는 종래의 GOLD(Gate Overlappde LDD) 소자의 단면도.
제2a-e도는 본 발명에 따른 리세스 게이트(Recessde Gate)를 갖는 반도체장치의 제조공정도.
* 도면의 주요부분에 대한 부호의 설명
11 : 반도체기판 12 : 절화막
13 : 게이트산화막 14 : 게이트용 폴리실리콘
15 : 산화막, 16n-형 불순물층 17 : 측벽
18 : 에피택셜층
본 발명은 반도체 장치에 관한 것으로, 특히 쇼트채널(Short Channel) 효과를 줄일 수 있는 리세스 게이트를 갖는 반도체 장치의 제조방법에 관한 것이다.
종래에는, 제1도에 도시한 바와 같이 n-형 불순물층(2)이 게이트(1)와 전체 오버랩된 GOLD 소자를 사용하였으며, 이는 핫캐리어(Hot Carrier) 감소에 있어서 부분 오버랩된 LDD에 비하여 우수하며, 또한 동작 전류가 크다. 3은 측벽을 나타내며, 4는 n+형 불순물층을 나타낸다.
그러나 이와같은 GOLD소자는 현재의 초미세화 추세에 따라 제한되는 레이아우트 면적내에서 GOLD 구조를 형성하기 매우 어려우며, 채널 이온주입에 의한 n-도핑보상(Compensation) 효과를 막을 수 없는 문제점이 있었다.
본 발명은 이와같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 n- 영역을 게이트와 전체 오버랩시킴과 동시에 리세스 게이트를 갖도록한 반도체장치의 제조방법을 재공하는 것이다.
이하, 본 발명을 첨부도면에 의하여 상세히 설명한다.
제2a-e도는 본 발명에 다른 반도체 장치의 제조공정도로서, 우선 제2a도에 도시한 바와같이 기판(11)상에 질화막(12)을 도포하고 게이트마스크(도시하지 않음)를 이용하여 질화막(12)과 일정 깊이의 반도체기판(11)을 식각하여 트랜치를 형성한 후 식각된 부분에 질화막(12)을 마스크로 하여 임계전압 또는 펀치스루우(Punch Through) 스톱용 불순물을 이온주입한 다음. 제2b도와 같이 전표면에 게이트산화막(13)을 성장시키고 그 위에 트랜치를 완전히 메울수 있도록 두꺼운 게이트용 폴리실리콘(14)을 도포하고 예치백한다.
그후, 제2c도에 도시한 바와같이 질화막(12)과 질화막(12)상의 게이트산화막(13)을 제거하고 남아있는 게이트산화막(13)의 양 질화를 위해 노출된 부분의 게이트용 폴리실리콘(14)을 일정 두께만 산화하여 산화막(15)을 형성한 후 반도체 기판(11)에 n-형 불순물을 이온주입하여 n-형 불순물층(16)을 형성한다. 여기서, n-형 불순물층(16)의 형성은 제2a도의 질화막(12)의 도포 이전에 n-형 불순물을 이온주입하고 게이트 형성영역의 반도체 기판(11)의 식각기 n-형 불순물의 이온주입부분을 제거하여 얻을 수도 있다.
그다음, 제2d도에 도시한 바와 같이 게이트측면에 산화막 측벽(17)을 형성한 후, 제2e도와 같이 선택적으로 에피택셜층(18)을 성장하여 n+형 소오스 및 드레인 영역을 형성한다. 여기서, n+형 소오스 및 드레인영역 형성은 에피택셜 성장시 인시투(In-situ) 도핑을 하거나 에피택셜 성장후 n+형 불순물의 이온 주입을 하여도 좋다. 또한, 측벽(17)은 n+형 소오스 및 드레인영역과 게이트의오버랩 커패시턴스를 줄일수가 있음을 유의하여야 한다.
이상 설명한 바와같이, 본 발명에 따르면 채널 이온주입과 n-형 불순물층이 분리되어 도핑 보상효과가 없고 정선 커패시턴스를 줄일 수 있는 이점이 있으며, n-형 불순물층이 게이트와 전체 오버랩되어 기존의 GOLD 구조와 유사한 효과를 얻을 수 있으며, 게이트가 n-형 불순물층보다 아래에 형성되므로 쇼트채널 효과를 줄일 수 있다.
또한, n-형 불순물층 부분만 얇은 게이트산화막을 갖고 n+형 불순물 영역은 두꺼운 산화막 측벽으로 게이트와 분리되므로 오버랩 커패시턴스를 줄일 수 있으며, n+형 정선과 리세스 게이트의 깊이 차이를 이용하므로 레이아우트 면적을 줄일 수 있는 효과가 있다.

Claims (3)

  1. 반도체기판상에 질화막을 도포하고 게이트 형성영역의 상기 질화막 및 일정 깊이의 상기 반도체기판을 식각하여 트랜치를 형성한 후 상기 반도체기판에 임계전압 또는 펀치스루우 스톱용 불순물을 이온주입하는 공정과, 전면에 게이트산화막을 성장시키고 상기 트랜치를 게이트용 폴리실리콘으로 메우는 공정과, 상기 질화막과 상기 질화막상의 상기 게이트산화막을 제거하고 게이트용 폴리실리콘의 노출된 부분을 일정 두께만 산화한 후 반도체기판에 소정 도전형의 저농도 불순물을 이온주입하는 공정과, 게이트측면에 산화막 측벽을 형성시키는 공정과, 노출된 상기 반도체기판의 표면에 애피택셜층을 성장시키고 소오스 및 드레인영역을 형성시키는 공정으로 이루어진 리세스 게이트를 갖는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 소오스 및 드레인 형성공정은 에피택셜층의 성장시 인시투 도핑을 실시함으로 이루어지는 리세스 게이트를 갖는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 소정 도전형의 저농도 불순물의 이온주입공정은 상기 질화막의 도포이전에 미리 실시함을 특징으로 하는 반도체장치의 제조방법.
KR1019910007881A 1991-05-15 1991-05-15 리세스 게이트를 갖는 반도체장치의 제조방법 KR940002400B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019910007881A KR940002400B1 (ko) 1991-05-15 1991-05-15 리세스 게이트를 갖는 반도체장치의 제조방법
JP4081426A JP2826924B2 (ja) 1991-05-15 1992-03-04 Mosfetの製造方法
DE4212829A DE4212829C2 (de) 1991-05-15 1992-04-16 Verfahren zur Herstellung von Metall-Oxid-Halbleiter-Feldeffekttransistoren
US07/883,857 US5270257A (en) 1991-05-15 1992-05-15 Method of making metal oxide semiconductor field effect transistors with a lightly doped drain structure having a recess type gate

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KR1019910007881A KR940002400B1 (ko) 1991-05-15 1991-05-15 리세스 게이트를 갖는 반도체장치의 제조방법

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