KR950030305A - 반도체 장치의 소자격리방법 - Google Patents

반도체 장치의 소자격리방법 Download PDF

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Publication number
KR950030305A
KR950030305A KR1019940008914A KR19940008914A KR950030305A KR 950030305 A KR950030305 A KR 950030305A KR 1019940008914 A KR1019940008914 A KR 1019940008914A KR 19940008914 A KR19940008914 A KR 19940008914A KR 950030305 A KR950030305 A KR 950030305A
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South Korea
Prior art keywords
pattern
oxide film
polysilicon
forming
nitride film
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KR1019940008914A
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KR970003715B1 (en
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배용태
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김광호
삼성전자 주식회사
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Priority to KR94008914A priority Critical patent/KR970003715B1/ko
Publication of KR950030305A publication Critical patent/KR950030305A/ko
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Publication of KR970003715B1 publication Critical patent/KR970003715B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체 기판의 선택산화 방법에 관한 것으로, 소자분리를 위한 필드영역 형성시 활성영역으로의 측면산화에 의한 버즈비크 현상이 발생하는 것을 방지하기 위해, 반도체 기판중 활성영역이 형성될 부분에 패드산화막, 질화막, CVD 산화막으로 된 패턴을 형성하고, 상기 패턴의 측면에 질화막 측벽스페이서를 형성시킨 후, 상기 패턴이 형성되지 않은 기판영역에만 폴리실리콘을 형성시켜, 상기 폴리실리콘을 산화시킴으로서 분리영역을 형성시키는 방법이다.
상기와 같은 방법은 패턴의 측면에 형성된 측벽스페이서에 의해 버즈비크의 크기가 감소되며 두꺼운 필드영역을 형성시킬 수 있으므로 반도체 소자의 고집적화에 적용할 수 있다.

Description

반도체 장치의 소자격리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3B도는 본 발명에 대한 시뮬레이션 단면도이다.

Claims (4)

  1. 반도체 기판의 전면에 패드산화막, 제1질화막, CVD 산화막을 형성하는 단계; 상기 제1질화막 및 CVD 산화막을 선택적으로 제거하여 반도체 기판중 활성영역이 형성될 부분에 패턴을 형성하는 단계; 결과물 전면에 제2질화막을 형성하고, 이를 에치하여 상기 패턴의 측면에 측벽스페이서를 형성한 후 노출된 패드산화막을 제거하는 단계; 결과물 전면에 폴리실리콘을 증착한 후, 상기 폴리실리콘의 표면이 상기 CVD 표면과 평탄화되도록 폴리싱하는 단계; 및 상기 폴리실리콘을 열산화하여 필드영역을 형성하는 단계를 포함하는 반도체 장치의 소자격리방법.
  2. 제1항에 있어서, 노출된 패드산화막을 제거한 후 필드영역 하부에 채널스톱영역 형성을 위한 이온주입공정을 실시함을 특징으로 하는 반도체 장치의 소자격리방법.
  3. 제1항에 있어서, 상기 폴리실리콘을 폴리싱하기 전 또는 후에 필드영여 하부에 채널스톱 영역을 형성하기 위한 이온주입공정을 실시함을 특징으로 하는 반도체 장치의 소자격리방법.
  4. 제1항에 있어서, 상기 패턴형성 단계에서 노출된 패드산화막을 제거하는 단계를 더 포함함을 특징으로 하는 반도체 장치의 소자격리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR94008914A 1994-04-27 1994-04-27 Method of isolation of the elements on the semiconductor device KR970003715B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94008914A KR970003715B1 (en) 1994-04-27 1994-04-27 Method of isolation of the elements on the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR94008914A KR970003715B1 (en) 1994-04-27 1994-04-27 Method of isolation of the elements on the semiconductor device

Publications (2)

Publication Number Publication Date
KR950030305A true KR950030305A (ko) 1995-11-24
KR970003715B1 KR970003715B1 (en) 1997-03-21

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KR94008914A KR970003715B1 (en) 1994-04-27 1994-04-27 Method of isolation of the elements on the semiconductor device

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KR970003715B1 (en) 1997-03-21

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