KR970054268A - 반도체 에스 오 아이 소자의 제조방법 - Google Patents

반도체 에스 오 아이 소자의 제조방법 Download PDF

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Publication number
KR970054268A
KR970054268A KR1019950066069A KR19950066069A KR970054268A KR 970054268 A KR970054268 A KR 970054268A KR 1019950066069 A KR1019950066069 A KR 1019950066069A KR 19950066069 A KR19950066069 A KR 19950066069A KR 970054268 A KR970054268 A KR 970054268A
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South Korea
Prior art keywords
forming
silicon substrate
oxide film
gate
film
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KR1019950066069A
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English (en)
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KR100197656B1 (ko
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고요환
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김주용
현대전자산업 주식회사
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Priority to KR1019950066069A priority Critical patent/KR100197656B1/ko
Priority to US08/696,163 priority patent/US5899712A/en
Priority to TW085109796A priority patent/TW323388B/zh
Priority to GB9626975A priority patent/GB2308739B/en
Priority to JP8358680A priority patent/JP2936536B2/ja
Priority to DE19654711A priority patent/DE19654711C2/de
Publication of KR970054268A publication Critical patent/KR970054268A/ko
Application granted granted Critical
Publication of KR100197656B1 publication Critical patent/KR100197656B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 SOI 구조를 갖는 반도체소자에 있어서, 필드산화막 하부에 일정두께의 실리콘막을 형성하고, 상기 실리콘막에 이온을 주입하여 도핑영역을 형성하여 반도체기판의 콘택을 형성하므로서, 반도체소자의 특성을 향상한다.

Description

반도체 에스 오 아이 소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3A도 내지 제3B도는 본 발명의 실시예에 따른 SOI MOSFET의 제조 공정도.

Claims (2)

  1. 제1실리콘기판의 상부에 제1실리콘산화막을 형성하는 단계와, 상기 제1실리콘산화막 상부에 제2실리콘기판을 형성하는 단계와, 상기 제2실리콘기판의 상부에 패드산화막을 형성하고, 상기 패드산화막의 상부에 질화막을 형성하는 단계와, 소자분리영역을 노출하는 식각마스크를 사용하여 상기 질화막과, 패드산화막을 식각하여 질화막패턴과, 패드산화막패턴을 형성하는 단계와, 노출된 제2실리콘기판을 산화하되, 상기 제2실리콘기판의 일정두께가 남아 있을 때까지만 산화하여 필드산화막을 형성하는 단계와, 상기 질화막패턴과, 패드산화막패턴을 제거하는 단계와, 채널 스탑 임플랜트를 상기 필드산화막 하부의 제2실리콘기판에 실시하여 도핑영역을 형성하는 단계와, 상기 제2실리콘기판의 상부에 게이트산화막과, 폴리실리콘층을 차례로 형성한 후, 상기 폴리실리콘층을 패터닝하여 게이트를 형성하는 단계와, 상기 게이트를 마스크로 상기 제2실리콘기판에 저농도의 이온을 주입하여 저농도 이온주입영역을 형성하는 단계와, 상기 구조의 전 표면에 제2산화막을 형성한 후, 전면식각하여 상기 게이트의 측벽에 제2산화막스페이서를 형성하는 단계와, 상기 게이트와 제2산화막스페이서를 마스크로 상기 제2실리콘기판에 고농도의 이온을 주입하여 고농도 이온주입영역을 형성하는 단계와, 상기 구조의 전 표면에 절연막을 형성하고, 콘택홀을 형성하기 위한 식각 마스크를 사용하여 상기 절연막을 게이트 또는 상기 제2실리콘기판이 노출된 때까지 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 매립하는 금속패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 제조방법.
  2. 제1항에 있어서, 상기 필드산화막을 형성할 때, 상기 제2실리콘기판 두께의 50 내지 90% 정도까지 산화하는 것을 특징으로 하는 반도체소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950066069A 1995-08-21 1995-12-29 반도체 에스.오.아이.소자의 제조방법 KR100197656B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950066069A KR100197656B1 (ko) 1995-12-29 1995-12-29 반도체 에스.오.아이.소자의 제조방법
US08/696,163 US5899712A (en) 1995-08-21 1996-08-13 Method for fabricating silicon-on-insulator device
TW085109796A TW323388B (ko) 1995-08-21 1996-08-13
GB9626975A GB2308739B (en) 1995-12-29 1996-12-27 Semiconductor device and a manufacturing method for the same
JP8358680A JP2936536B2 (ja) 1995-12-29 1996-12-27 半導体デバイスおよびその製造方法
DE19654711A DE19654711C2 (de) 1995-12-29 1996-12-30 Halbleitereinrichtung und Verfahren zu deren Herstellung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066069A KR100197656B1 (ko) 1995-12-29 1995-12-29 반도체 에스.오.아이.소자의 제조방법

Publications (2)

Publication Number Publication Date
KR970054268A true KR970054268A (ko) 1997-07-31
KR100197656B1 KR100197656B1 (ko) 1999-07-01

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KR1019950066069A KR100197656B1 (ko) 1995-08-21 1995-12-29 반도체 에스.오.아이.소자의 제조방법

Country Status (4)

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JP (1) JP2936536B2 (ko)
KR (1) KR100197656B1 (ko)
DE (1) DE19654711C2 (ko)
GB (1) GB2308739B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4054557B2 (ja) * 2001-10-10 2008-02-27 沖電気工業株式会社 半導体素子の製造方法
JP4139105B2 (ja) 2001-12-20 2008-08-27 株式会社ルネサステクノロジ 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
US4435895A (en) * 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
EP0157780B1 (en) * 1983-09-30 1988-05-18 Hughes Aircraft Company High density mosfet with field oxide aligned channel stops and method of fabricating the same
NL8501720A (nl) * 1985-06-14 1987-01-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een siliciumplak plaatselijk wordt voorzien van veldoxide met kanaalonderbreker.

Also Published As

Publication number Publication date
GB2308739B (en) 2000-06-28
JP2936536B2 (ja) 1999-08-23
DE19654711A1 (de) 1997-07-03
GB2308739A8 (en) 1998-01-22
GB2308739A (en) 1997-07-02
DE19654711C2 (de) 2003-05-22
GB9626975D0 (en) 1997-02-12
JPH1012894A (ja) 1998-01-16
KR100197656B1 (ko) 1999-07-01

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