KR960002690A - 저저항 게이트전극을 갖는 반도체소자의 제조방법 - Google Patents

저저항 게이트전극을 갖는 반도체소자의 제조방법 Download PDF

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KR960002690A
KR960002690A KR1019940012853A KR19940012853A KR960002690A KR 960002690 A KR960002690 A KR 960002690A KR 1019940012853 A KR1019940012853 A KR 1019940012853A KR 19940012853 A KR19940012853 A KR 19940012853A KR 960002690 A KR960002690 A KR 960002690A
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layer
forming
silicide layer
polysilicon
polysilicon layer
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KR0141195B1 (ko
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박영훈
서영우
이용희
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김광호
삼성전자 주식회사
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Priority to DE19516339A priority patent/DE19516339B4/de
Priority to TW084104599A priority patent/TW260813B/zh
Priority to US08/440,954 priority patent/US5545578A/en
Priority to JP16148295A priority patent/JP3544750B2/ja
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

저저항 게이트전극을 갖는 반도체소자의 제조방법이 개시되어 있다. 반도체기판 상에 게이트 절연막을 형성하고, 게이트 절연막 상에 폴리실리콘층 및 실리사이드층을 차례로 형성한다. 사진식각 공정으로 실리사이드층을 식각하고, 계속해서 실리사이드층을 과도 식각하여 폴리실리콘층에 단차부를 형성한다. 실리사이드층 및 폴리실리콘층 단차부의 측벽에 산화 방지 스페이서를 형성한다. 산화 방지 스페이서를 식각 마스크로 사용하여 폴리실리콘을 식각함으로써, 실리사이드층 및 폴리실리콘층으로 이루어진 게이트전극을 형성한다. 게이트 절연막 및 폴리실리콘층의 노출된 부분을 열적 산화시킨 후 결과물에 소오스와 드레인을 형성하기 위한 제1불순물 이온을 주입한다. 실리사이드층의 산화를 방지하고 폴리실리콘층의 측벽부위만 산화시켜서, 게이트전극의 모서리 부위에서 발생하는 프린지 전계를 최소화시킬 수 있다.

Description

저저항 게이트전극을 갖는 반도체소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4H도는 본 발명의 제1실시예에 의한 반도체소자의 제조방법을 설명하기 위한 단면도들.

Claims (11)

  1. 반도체기판 상에 게이트 절연막을 형성하는 단계; 상기 게이트 절연막 상에 폴리실리콘층을 형성하는 단계; 상기 폴리실리콘층 상에 실리사이드층을 형성하는 단계; 사진식각 공정으로 실리사이드층을 식각하는 단계; 상기 실리사이드층을 과도 식각하여 상기 폴리실리콘층에 단차부를 형성하는 단계; 상기 실리사이드층 및 폴리실리콘층 단차부의 측벽에 산화 방지 스페이서를 형성하는 단계; 상기 산화 방지 스페이서를 식각 마스크로 사용하여 폴리실리콘을 식각함으로써, 상기 실리사이드층 및 폴리실리콘층으로 이루어진 게이트전극을 형성하는 단계; 상기 게이트 절연막 및 폴리실리콘층의 노출된 부분을 열적 산화시키는 단계; 및 상기 결과물에 소오스와 드레인을 형성하기 위한 제1불순물 이온을 주입하는 단계를 구비하는 것을 특징으로 하는 반도체소자의 제조방법.
  2. 제1항에 있어서, 상기 실리사이드층을 형성하는 단계 후, 상기 실리사이드층 상에 산화방지막을 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체소자의 제조방법.
  3. 제2항에 있어서, 상기 산화방지막을 구성하는 물질로서 질화물을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.
  4. 제1항에 있어서, 상기 실리사이드층을 형성하는 단계 후, 상기 실리사이드층 상에 절연층을 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체소자의 제조방법.
  5. 제4항에 있어서, 상기 절연층을 구성하는 물질로서 산화물을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.
  6. 제1항에 있어서, 상기 실리사이드층을 형성하는 단계 후, 상기 실리사이드층 상에 산화방지막 및 절연층을 차례로 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체소자의 제조방법.
  7. 제6항에 있어서, 상기 산화방지막을 구성하는 물질로는 질화막을 사용하고, 상기 절연층을 구성하는 물질로는 산화물을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.
  8. 제1항에 있어서, 상기 실리사이드층을 구성하는 물질로서 텅스텐 실리사이드를 사용하는 것을 특징으로 하는 반도체소자의 제조방법.
  9. 제1항에 있어서, 상기 산화 방지 스페이서를 구성하는 물질로서 질화물을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.
  10. 제1항에 있어서, 상기 제1불순물 이온을 주입하는 단계 후, 상기 산화 방지 스페이서의 측벽에 스페이서를 형성하는 단계; 및 상기 결과물에 소오스와 드레인을 형성하기 위한 제2불순물 이온을 주입하는 단계를 더 구비하는 것을 특징으로 하는 반도체소자의 제조방법.
  11. 반도체기판 상에 게이트 절연막을 형성하는 단계; 상기 게이트 절연막 상에 폴리실리콘층, 실리사이드층 및 절연층을 차례로 형성하는 단계; 사진식각 공정으로 상기 절연층을 식각하고, 계속해서 상기 실리사이드층을 언더컷 식각하는 단계; 상기 실리사이드층을 과도 식각하여 상기 폴리실리콘층에 단차부를 형성하는 단계; 상기 절연층, 실리사이드층 및 폴리실리콘층 단차부의 측벽에 산화 방지 스페이서를 형성하는 단계; 상기 산화 방지 스페이서를 식각 마스크로 사용하여 폴리실리콘을 식각함으로써, 상기 실리사이드층 및 폴리실리콘층으로 이루어진 게이트전극을 형성하는 단계; 상기 게이트 절연막 및 폴리실리콘층의 노출된 부분을 열적산화시키는 단계; 및 상기 결과물에 소오스와 드레인을 형성하기 위한 제1불순물 이온을 주입하는 단계를 구비하는 것을 특징으로 하는 반도체소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940012853A 1994-06-08 1994-06-08 저저항 게이트전극을 갖는 반도체소자의 제조방법 KR0141195B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019940012853A KR0141195B1 (ko) 1994-06-08 1994-06-08 저저항 게이트전극을 갖는 반도체소자의 제조방법
DE19516339A DE19516339B4 (de) 1994-06-08 1995-05-04 Verfahren zur Herstellung eines Halbleiterbauelementes mit niederohmiger Gateelektrode
TW084104599A TW260813B (en) 1994-06-08 1995-05-09 Method of manufacturing a semiconductor device having low-resistance gate electrode
US08/440,954 US5545578A (en) 1994-06-08 1995-05-15 Method of maufacturing a semiconductor device having a low resistance gate electrode
JP16148295A JP3544750B2 (ja) 1994-06-08 1995-06-05 低抵抗ゲート電極を有する半導体素子の製造方法

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KR1019940012853A KR0141195B1 (ko) 1994-06-08 1994-06-08 저저항 게이트전극을 갖는 반도체소자의 제조방법

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KR960002690A true KR960002690A (ko) 1996-01-26
KR0141195B1 KR0141195B1 (ko) 1998-07-15

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US (1) US5545578A (ko)
JP (1) JP3544750B2 (ko)
KR (1) KR0141195B1 (ko)
DE (1) DE19516339B4 (ko)
TW (1) TW260813B (ko)

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JP3544750B2 (ja) 2004-07-21
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US5545578A (en) 1996-08-13

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