KR980005435A - 티타늄 질화막 적층 구조의 게이트 전극을 갖춘 반도체 장치 및 그 제조 방법 - Google Patents

티타늄 질화막 적층 구조의 게이트 전극을 갖춘 반도체 장치 및 그 제조 방법 Download PDF

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KR980005435A
KR980005435A KR1019960020358A KR19960020358A KR980005435A KR 980005435 A KR980005435 A KR 980005435A KR 1019960020358 A KR1019960020358 A KR 1019960020358A KR 19960020358 A KR19960020358 A KR 19960020358A KR 980005435 A KR980005435 A KR 980005435A
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conductive layer
insulating layer
semiconductor device
forming
layer pattern
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KR1019960020358A
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KR100207472B1 (ko
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염계희
이덕형
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김광호
삼성전자 주식회사
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Priority to JP11389097A priority patent/JP3693081B2/ja
Priority to US08/853,806 priority patent/US6091120A/en
Publication of KR980005435A publication Critical patent/KR980005435A/ko
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Priority to US09/539,058 priority patent/US6544873B1/en
Priority to US10/239,958 priority patent/US20050208486A1/en

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Abstract

본 발명은 티타늄 질화막 적층 구조의 게이트 전극을 갖춘 반도체 장치 및 그 제조 방법에 관한 것으로, 본 발명에 따른 반도체 장치는 반도체 기판상에서 게이트 산화막을 개재하여 제1 도전 물질층과 제2 도전 물질층이 순차 적층된 게이트 전극을 포함하고, 상기 제1 도전 물질층은 상기 제2 도전 물질층보다 작은 폭을 갖는다. 이와 같은 구조를 갖는 본 발명에 따른 반도체 장치를 제조하기 위하여 제1 도전층에 대하여 소정의 식각액을 이용하여, 일부 식각된 게이트 산화막의 식각된 단차 부분에서의 손상 부분을 피할 수 있을 정도의 두께 만큼 상기 제1 도전층의 측벽을 소정 시간 동안 식각하여 변형된 제1 도전층 패턴을 형성한다.
본 발명에 의하면, 게이트 전극용 물질로 티타늄 질화막을 이용하는 반도체 장치에서 선폭 감소에 따른 저항 증가를 최소화할 수 있고, 신뢰성을 향상시킬 수 있는 반도체 장치를 비교적 단순한 공정으로 제조할 수 있다.

Description

티타늄 질화막 적층 구조의 게이트 전극을 갖춘 반도체 장치 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 내지 제5도는 본 발명에 따라 게이트 전극으로 티타늄 질화막을 사용하는 반도체 장치의 제조 방법을 설명하기 위한 단면도이다.

Claims (10)

  1. 반도체 기판상에서 게이트 산화막을 개재하여 제1 도전물질층과 제2 도전 물질층이 순차 적층된 게이트 전극을 포함하는 반도체 장치에 있어서, 상기 제 1도전 물질층은 상기 제2 도전 물질층보다 작은 폭을 갖는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 제1 도전 물질층은 티타늄 질화막인 것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 상기 제2 도전 물질층은 텅스텐, 구리 및 티타늄 실리사이드로 이루어진 군에서 선택된 적어도 어느 하나인 것을 특징으로 하는 반도체 장치.
  4. 반도체 기판 상에 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막이 형성된 기판의 전면에 제1 도전층, 제2 도전층, 제1 절연층을 순차적으로 형성하는 단계와, 사진 식각 공정을 이용하여 상기 제1 절연층을 패터닝하여 제1 절연층 패턴을 형성하는 단계와, 상기 제 1절연층 패턴을 식각 마스크로 하여 상기 제2 도전층 및 제1 도전층을 차례로 식각하여 제2 도전층 패턴 및 제1 도전층 패턴을 형성하는 단계와, 소정의 식각액을 이용하여, 상기 제1 도전층 패턴의 측벽을 소정 시간 동안 식각하여 변형된 제1 도전층 패턴을 형성하는 단계와, 상기 결과물 전면에 제2 절연층을 형성하는 단계와, 상기 제2 절연층을 식각하여 상기 변형된 제1 도전층 패턴, 상기 제2 도전층 패턴, 및 제1 절연층 패턴의 측벽에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  5. 제4항에 있어서, 상기 소정의 식각액은 과산화수소 또는 과산화수소수와 황산의 혼합액으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조 방법.
  6. 제5항에 있어서, 상기 과산화수소수와 황산의 혼합액은 과산화수소수:황산이 6:1인 것을 특징으로 하는 반도체 장치의 제조 방법.
  7. 제4항에 있어서, 상기 제1 도전층은 티타늄 질화막으로 구성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  8. 제4항에 있어서, 상기 제2 도전층은 텅스텐, 구리 및 티타늄 실리사이드로 이루어진 군에서 선택된 적어도 어느 하나로 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  9. 제4항에 있어서, 상기 제1 절연층, 제2 절연층은 실리콘 산화막 또는 실리콘 질화막으로 구성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  10. 반도체 기판 상에 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막이 형성된 기판의 전면에 제1 도전층, 제2 도전층, 제1 절연층을 순차적으로 형성하는 단계와, 사진 식각 공정을 이용하여 상기 제1 절연층을 패터닝하여 제1 절연층 패턴을 형성하는 단계와, 상기 제1 절연층 패턴을 식각 마스크로 하여 상기 제2 도전층 및 제1 도전층을 차례로 식각하여 제2 도전층 패턴 및 제1 도전층 패턴을 형성하는 단계와, 상기 결과물 상기 1절연층 패턴을 마스크로 1차 이온 주입하여 저농도 소스/드레인 영역을 형성하는 단계와, 소정의 식각액을 이용하여, 상기 1 도전층 패턴의 측벽을 소정 시간동안 식각하여 변형된 제1 도전층 패턴을 형성하는 단계와, 상기 결과물 전면에 제2 절연층을 형성하는 단계와, 상기 제2 절연층을 식각하여 상기 변형된 제1 도전층 패턴, 상기 제2 도전층 패턴, 및 제1 절연층 패턴의측벽에 스페이서를 형성하는 단계와, 상기 결과물 전면에 상기 스페이서를 마스크로 2차 이온 주입하여 고농도 소스/드레인 영역을 형성하는 단를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960020358A 1996-06-07 1996-06-07 티타늄 질화막 적층 구조의 게이트 전극을 갖춘 반도체장치 및 그 제조 방법 KR100207472B1 (ko)

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JP11389097A JP3693081B2 (ja) 1996-06-07 1997-05-01 半導体装置のｍｏｓトランジスター及びその製造方法
US08/853,806 US6091120A (en) 1996-06-07 1997-05-09 Integrated circuit field effect transisters including multilayer gate electrodes having narrow and wide conductive layers
US09/539,058 US6544873B1 (en) 1996-06-07 2000-03-30 Methods of fabricating integrated circuit field effect transistors including multilayer gate electrodes having narrow and wide conductive layers
US10/239,958 US20050208486A1 (en) 1996-06-07 2001-03-23 Brca-1 regulators and methods of use

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