KR970003803A - 소자분리막 제조방법 - Google Patents

소자분리막 제조방법 Download PDF

Info

Publication number
KR970003803A
KR970003803A KR1019950017476A KR19950017476A KR970003803A KR 970003803 A KR970003803 A KR 970003803A KR 1019950017476 A KR1019950017476 A KR 1019950017476A KR 19950017476 A KR19950017476 A KR 19950017476A KR 970003803 A KR970003803 A KR 970003803A
Authority
KR
South Korea
Prior art keywords
device isolation
film
forming
silicon
oxide film
Prior art date
Application number
KR1019950017476A
Other languages
English (en)
Other versions
KR0166499B1 (ko
Inventor
송태식
장세억
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950017476A priority Critical patent/KR0166499B1/ko
Publication of KR970003803A publication Critical patent/KR970003803A/ko
Application granted granted Critical
Publication of KR0166499B1 publication Critical patent/KR0166499B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 작은 버즈빅 길이와 큰 체적비를 갖는 소자분리막 제조하기위하여 소자분리 마스크 패턴의 측벽에 실리콘막 스페이서를 사용하고, 노출된 실리콘기판을 일정깊이를 식각하여 하부모서리가 라운드된 홈을 형성하고, 다시 홈의 측벽에 질화막 스페이서를 형성함으로서, 후속의 산화공정으로 소자분리산화막을 형성할 때 홈 측면으로 산소가 확산되는 것을 억제하여 패드산화막 부분에서 형성되는 버즈빅을 최소화 하는 것이다.

Description

소자분리막 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제9도는 본 발명의 실시예에 의한 소자분리막을 형성하는 단계를 도시한 단면도.

Claims (2)

  1. 소자분리막 제조방법에 있어서, 실리콘기판상부에 패드산화막과 제1질화막을 적층하고, 소자분리마스크를이용한 식각공정으로 상기 제1질화막과 패드산화막을 국부적으로 식각하는 단계와, 상기 제1질화막 패턴 측벽에 실리콘막스페이서를 형성하는 단계와, 노출된 실리콘기판을 습식식각하여 상기 실리콘막 스페이서를 제거하는 동시에 하부 모서리가 라운드된 홈을 형성하는 단계와, 상기 홈 측면에 제2질화막 스페이서를 형성하는 단계와, 습식산화 공정으로 노출된실리콘기판을 산화시켜 소자분리산화막을 형성하는 단계로 이루어지는 소자분리막 제조방법.
  2. 제1항에 있어서, 상기 실리콘막 스페이서는 다결정 실리콘 또는 비정질 실리콘으로 형성하는 것을 특징으로 하는 소자분리막 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950017476A 1995-06-26 1995-06-26 소자 분리막 제조방법 KR0166499B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950017476A KR0166499B1 (ko) 1995-06-26 1995-06-26 소자 분리막 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950017476A KR0166499B1 (ko) 1995-06-26 1995-06-26 소자 분리막 제조방법

Publications (2)

Publication Number Publication Date
KR970003803A true KR970003803A (ko) 1997-01-29
KR0166499B1 KR0166499B1 (ko) 1999-02-01

Family

ID=19418320

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950017476A KR0166499B1 (ko) 1995-06-26 1995-06-26 소자 분리막 제조방법

Country Status (1)

Country Link
KR (1) KR0166499B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437010B1 (ko) * 1997-09-12 2004-07-16 삼성전자주식회사 트랜치 식각 방법 및 그를 이용한 트랜치 격리의 형성 방법
KR100515034B1 (ko) * 1998-05-30 2005-12-09 삼성전자주식회사 트렌치 격리 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437010B1 (ko) * 1997-09-12 2004-07-16 삼성전자주식회사 트랜치 식각 방법 및 그를 이용한 트랜치 격리의 형성 방법
KR100515034B1 (ko) * 1998-05-30 2005-12-09 삼성전자주식회사 트렌치 격리 제조 방법

Also Published As

Publication number Publication date
KR0166499B1 (ko) 1999-02-01

Similar Documents

Publication Publication Date Title
KR900001000A (ko) 단일 폴리실리콘 자기-정합 트랜지스터 및 이의 제조 방법
KR880011930A (ko) 반도체장치의 제조방법
KR970003803A (ko) 소자분리막 제조방법
KR980006032A (ko) 반도체 소자의 격리영역 형성방법
KR950021396A (ko) 필드산화막 제조방법
KR970003810A (ko) 소자분리막 제조방법
KR100190036B1 (ko) 반도체 소자의 분리 방법
KR970003780A (ko) 반도체소자의 소자분리 산화막 제조방법
KR960019513A (ko) 반도체 소자의 콘택 형성 방법
KR930014896A (ko) 디램 셀의 제조방법
KR880013236A (ko) 반도체 장치의 제조방법
KR950015712A (ko) 반도체소자의 소자분리막 제조방법
KR920010752A (ko) 반도체 소자의 격리막 형성방법
KR920013600A (ko) 반도체 장치의 플래이너 격리영역 형성방법
KR960026620A (ko) 보이드(Void)를 이용한 반도체 소자분리 방법
KR970003778A (ko) 반도체소자의 소자분리 산화막 제조방법
KR950027993A (ko) 반도체소자의 소자분리산화막 제조방법
KR920008923A (ko) 반도체 집적회로의 소자격리영역 형성방법
KR930001435A (ko) 소자분리 산화막 제조방법
KR950021400A (ko) 필드산화막 제조방법
KR970003520A (ko) 미세 반도체 소자의 콘택홀 형성방법
KR950021399A (ko) 반도체소자의 소자분리막 제조방법
KR950024299A (ko) 반도체장치 및 그 제조방법
KR970052189A (ko) 반도체 소자의 필드 산화막 형성방법
KR970053488A (ko) 반도체 소자의 필드 산화막 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060818

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee