KR880011930A - 반도체장치의 제조방법 - Google Patents
반도체장치의 제조방법 Download PDFInfo
- Publication number
- KR880011930A KR880011930A KR1019880003123A KR880003123A KR880011930A KR 880011930 A KR880011930 A KR 880011930A KR 1019880003123 A KR1019880003123 A KR 1019880003123A KR 880003123 A KR880003123 A KR 880003123A KR 880011930 A KR880011930 A KR 880011930A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon
- layer
- manufacturing
- semiconductor device
- silicon layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims 5
- 238000007254 oxidation reaction Methods 0.000 claims 5
- 238000002844 melting Methods 0.000 claims 3
- 230000008018 melting Effects 0.000 claims 3
- 239000012535 impurity Substances 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 229910021332 silicide Inorganic materials 0.000 claims 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
내용없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3A도 내지 제3E도는 본 발명에 따른 반도체장치의 제조방법에 의한 제조공정을 나타낸 단면도로서,
제3A도는 실리콘기판상에 소자분리영역의 형성과 제1절연막의 형성 및 인이 주입된 제1다결정실리콘층이 전표면상에 형성되는 과정을 나타낸 단면도,
제3B도는 제1다결정실리콘층의 표면을 산화시켜 제2절연막을 형성시키는 공정과 제2다결정실리콘층을 형성시키는 공정 및 실리콘질화막을 형성시키는 공정을 나타낸 단면도,
제3C도는 실리콘질화막과 제2다결정실리콘층, 제2절연막, 제1다결정실리콘층이 자기정합 방법중 RIE방법에 의해 선택적으로 에칭되는 과정을 나타낸 단면도,
제3D도는 제3절연막이 제1, 제2다결정실리콘층의 측면부분에 형성되는 과정을 나타낸 단면도,
제3E도는 실리콘질화막을 제거시키고, 제3다결정실리콘층을 전표면상에 형성시키며, 인을 제3다결정실리콘층으로 확산시키는 공정을 나타낸 단면도이다.
Claims (9)
- 실리콘기판(17)의 주표면상에 소자분리영역(18)을 형성시키는 공정과, 이 소자분리영역(18)에 의해 분리된 상기 실리콘기판(17)의 소자영역상에 제1절연먁(19)을 형성시키는 공정, 상기 제1절연막(19)과 소자분리 영역(18)에 불순물을 도핑시켜 제1실리콘층(20)을 형성시키는 공정, 제1실리콘층(20)상에 제2절연막(21)을 형성시키는 공정, 상기 제2절연막(21)상에 제2실리콘층(22)을 형성시키는 공정, 상기 제2실리콘층(22)상에 내산화성막(23)을 형성시키는 공정, 산기 내산화성막(23)과 제2실리콘층(22), 제2절연막(21) 및 제1실리콘층(20)을 설정된 패턴을 가진 마스크를 사용해서 선택적으로 에칭시키는 공정, 상기 내산화막(23)을 마스크로서 선택산화시켜 상기 제1, 제2실리콘층(20,22)의 측벽부에 제3절연막(24)을 형성 지키는 공정 및, 상기 제2실리콘층(22)과 소자분리영역(18)상에 도전층(25)을 형성시키는 공정을 구비하여 2층이상의 실리콘층을 사용한 것을 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 내산화성막(23)은 실리콘질화막으로 이루어지게 됨을 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 도전층(25)은 실리콘으로 이루어지게 됨을 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 도전층(25)은 고융점금속으로 이루어지게 됨을 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 도전층(25)은 고융점속의 실리사이드로 이루어지게 됨을 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 도전층(25)은 고융점금속의 실리사이드와 실리콘의 적층구조로 이루어지게 됨을 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 제1실리콘층(20,22:절연막)은 산화막으로 이루어지게됨을 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 제1실리콘층(20)에 도핑된 불순물은 인인 것은 특징으로 하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 내산화성막(23)은 상기 도전층(25)의 형성전에 제거됨을 특징으로 하는 반도체장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62068255A JP2633555B2 (ja) | 1987-03-23 | 1987-03-23 | 半導体装置の製造方法 |
JP62-68255 | 1987-03-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880011930A true KR880011930A (ko) | 1988-10-31 |
KR910001426B1 KR910001426B1 (ko) | 1991-03-05 |
Family
ID=13368463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880003123A KR910001426B1 (ko) | 1987-03-23 | 1988-03-23 | 반도체장치의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4935378A (ko) |
EP (1) | EP0283991A3 (ko) |
JP (1) | JP2633555B2 (ko) |
KR (1) | KR910001426B1 (ko) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5168465A (en) * | 1988-06-08 | 1992-12-01 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
US5198380A (en) * | 1988-06-08 | 1993-03-30 | Sundisk Corporation | Method of highly compact EPROM and flash EEPROM devices |
JPH088312B2 (ja) * | 1989-03-02 | 1996-01-29 | 三菱電機株式会社 | 半導体装置の製造方法 |
US4966864A (en) * | 1989-03-27 | 1990-10-30 | Motorola, Inc. | Contact structure and method |
IT1235690B (it) * | 1989-04-07 | 1992-09-21 | Sgs Thomson Microelectronics | Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia. |
JPH0821638B2 (ja) * | 1989-12-15 | 1996-03-04 | 株式会社東芝 | 不揮発性半導体記憶装置およびその製造方法 |
US5266509A (en) * | 1990-05-11 | 1993-11-30 | North American Philips Corporation | Fabrication method for a floating-gate field-effect transistor structure |
US5065225A (en) * | 1990-07-31 | 1991-11-12 | Sgs-Thomson Microelectronics, Inc. | Tunneling diffusion barrier for local interconnect and polysilicon high impedance device |
US5180688A (en) * | 1990-07-31 | 1993-01-19 | Sgs-Thomson Microelectronics, Inc. | Method of forming tunneling diffusion barrier for local interconnect and polysilicon high impedance device |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
HU223343B1 (hu) * | 1991-05-20 | 2004-06-28 | Novartis Ag. | Allil-amin-származékot tartalmazó gyógyászati készítmények és eljárás azok előállítására |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5252503A (en) * | 1991-06-06 | 1993-10-12 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5539216A (en) * | 1994-10-27 | 1996-07-23 | Motorola, Inc. | Monolithic semiconductor body with convex structure |
US5445984A (en) * | 1994-11-28 | 1995-08-29 | United Microelectronics Corporation | Method of making a split gate flash memory cell |
JP3719026B2 (ja) * | 1998-12-28 | 2005-11-24 | 富士通株式会社 | 磁気記録媒体とその製造方法 |
DE69832083D1 (de) * | 1998-12-29 | 2005-12-01 | St Microelectronics Srl | Selektives Silizidierungsverfahren in nichtflüchtigen Halbleiterspeichern |
US6306707B1 (en) * | 2000-11-20 | 2001-10-23 | Adanced Micro Devices, Inc. | Double layer hard mask process to improve oxide quality for non-volatile flash memory products |
JP4282359B2 (ja) * | 2003-04-11 | 2009-06-17 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US8642441B1 (en) | 2006-12-15 | 2014-02-04 | Spansion Llc | Self-aligned STI with single poly for manufacturing a flash memory device |
US7763928B2 (en) * | 2007-05-31 | 2010-07-27 | United Microelectronics Corp. | Multi-time programmable memory |
KR20090004155A (ko) * | 2007-07-06 | 2009-01-12 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 형성방법 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288256A (en) * | 1977-12-23 | 1981-09-08 | International Business Machines Corporation | Method of making FET containing stacked gates |
US4228256A (en) * | 1978-09-18 | 1980-10-14 | Cy/Ro Industries | Transparent blends of resinous copolymers and grafted elastomers |
US4519849A (en) * | 1980-10-14 | 1985-05-28 | Intel Corporation | Method of making EPROM cell with reduced programming voltage |
JPS58158970A (ja) * | 1982-03-16 | 1983-09-21 | Nec Corp | 半導体装置の製造方法 |
US4697330A (en) * | 1983-02-23 | 1987-10-06 | Texas Instruments Incorporated | Floating gate memory process with improved dielectric |
US4458407A (en) * | 1983-04-01 | 1984-07-10 | International Business Machines Corporation | Process for fabricating semi-conductive oxide between two poly silicon gate electrodes |
US4701776A (en) * | 1983-08-29 | 1987-10-20 | Seeq Technology, Inc. | MOS floating gate memory cell and process for fabricating same |
KR930007195B1 (ko) * | 1984-05-23 | 1993-07-31 | 가부시끼가이샤 히다찌세이사꾸쇼 | 반도체 장치와 그 제조 방법 |
JPS61136274A (ja) * | 1984-12-07 | 1986-06-24 | Toshiba Corp | 半導体装置 |
US4635347A (en) * | 1985-03-29 | 1987-01-13 | Advanced Micro Devices, Inc. | Method of fabricating titanium silicide gate electrodes and interconnections |
-
1987
- 1987-03-23 JP JP62068255A patent/JP2633555B2/ja not_active Expired - Fee Related
-
1988
- 1988-03-18 US US07/170,253 patent/US4935378A/en not_active Expired - Lifetime
- 1988-03-21 EP EP88104463A patent/EP0283991A3/en not_active Ceased
- 1988-03-23 KR KR1019880003123A patent/KR910001426B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPS63233569A (ja) | 1988-09-29 |
KR910001426B1 (ko) | 1991-03-05 |
EP0283991A3 (en) | 1989-04-05 |
JP2633555B2 (ja) | 1997-07-23 |
US4935378A (en) | 1990-06-19 |
EP0283991A2 (en) | 1988-09-28 |
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