KR970030640A - 반도체 장치의 소자 분리막 형성방법 - Google Patents

반도체 장치의 소자 분리막 형성방법 Download PDF

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KR970030640A
KR970030640A KR1019950042466A KR19950042466A KR970030640A KR 970030640 A KR970030640 A KR 970030640A KR 1019950042466 A KR1019950042466 A KR 1019950042466A KR 19950042466 A KR19950042466 A KR 19950042466A KR 970030640 A KR970030640 A KR 970030640A
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region
device isolation
width
nitride film
forming
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KR100214068B1 (ko
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박인옥
정영석
김의식
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김주용
현대전자산업 주식회사
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Priority to US08/747,024 priority patent/US5712205A/en
Priority to JP30967296A priority patent/JP3205775B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

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  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 0.5μm이하의 소자분리 간격을 갖는 고집적 반도체소자에 적합하도록 소자분리영역의 폭이 좁은 영역과 넓은 영역을 분리하여 소자분리공정을 행함으로써 소자분리 특성을 향상시킬 수 있도록 한 반도체장치의 소자분리방법에 관한 것으로, 이를 위해 소자분리영역의 폭이 상대적으로 좁은 영역과 소자분리영역의 폭이 상대적으로 넓은 영역을 포함하는 반도체기판상에 패드산화막과 질화막을 차례로 형성하는 공정과, 상기 소자분리영역의 폭이 상대적으로 좁은 영역의 상기 질화막과 패드산화막을 선택적으로 식각하고 이에 따라 노출되는 기판 부위를 식각하여 트렌치를 형성하는 공정, 기판 전면에 절연막을 두껍게 형성하는 공정, CMP공정에 의해 상기 절연막을 식각하여 트렌치 내부에만 남기는 공정, 상기 소자분리영역의 폭이 상대적으로 넓은 영역의 상기 질화막을 선택적으로 제거하는 공정, 산화공정을 진행하여 상기 질화막이 제거된 부분에 소자분리 절연막을 형성하는 공정을 포함하여 이루어지는 반도체장지의 소자분리방법을 제공한다.

Description

반도체 장치의 소자 분리막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 반도체장치의 소자분리방법을 공정순서에 따라 도시한 단면구조도.

Claims (9)

  1. 소자분리영역의 폭이 상대적으로 좁은 영역과 소자분리영역의 폭이 상대적으로 넓은 영역을 포함하는 반도체기판상에 패드산화막과 질화막을 차례로 형성하는 공정과, 상기 소자분리영역의 폭이 상대적으로 좁은 영역의 상기 질화막과 패드산화막을 선택적으로 식각하고 이에 따라 노출되는 기판부위를 식각하여 트렌치를 형성하는 공정, 기판 전면에 절연막을 두껍게 형성하는 공정, CMP공정에 의해 상기 절연막을 식각하여 트렌치 내부에만 남기는 공정, 상기 소자분리영역의 폭이 상대적으로 넓은 영역의 상기 질화막을 선택적으로 제거하는 공정, 및 산화공정을 진행하여 상기 질화막이 제거된 부분에 소자분리 절연막을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 소자분리방법.
  2. 제1항에 있어서, 상기 소자분리영역의 폭이 상대적으로 좁은 영역은 셀영역임을 특징으로 하는 반도체장치의 소자분리방법.
  3. 제2항에 있어서, 상기 셀영역은 소자분리영역 간격이 0.5μm이하임을 특징으로 하는 반도체장치의 소자분리방법.
  4. 제1항에 있어서, 상기 소자분리영역의 폭이 상대적으로 넓은 영역은 주변회로부임을 특징으로 하는 반도체장치의 소자분리방법.
  5. 제1항에 있어서, 상기 트렌치는 상기 소자분리영역의 폭이 상대적으로 좁은 영역의 소자분리영역에 형성되는 것을 특징으로 하는 반도체장치의 소자분리방법.
  6. 제1항에 있어서, 상기 절연막은 CVD산화막임을 특징으로 하는 반도체장치의 소자분리방법.
  7. 제1항에 있어서, 상기 소자분리 절연막 형성을 위한 산화공정이 진행되는 동안 상기 절연막이 조밀하게 되는 것을 특징으로 하는 반도체장치의 소자분리방법.
  8. 제1항에 있어서, 상기 CMP공정 진행시 상기 질화막이 식각저지층으로 작용하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  9. 제1항에 있어서, 상기 트렌치를 형성하는 공정과, 상기 소자분리 영역의 폭이 상대적으로 넓은 영역의 상기 질화막을 선택적으로 제거하는 공정후에 각각 필드 이온주입공정을 행하는 것을 특징으로 하는 반도체장치의 소자분리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950042466A 1995-11-21 1995-11-21 반도체 장치의 소자분리막 형성방법 Expired - Fee Related KR100214068B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950042466A KR100214068B1 (ko) 1995-11-21 1995-11-21 반도체 장치의 소자분리막 형성방법
US08/747,024 US5712205A (en) 1995-11-21 1996-11-07 Semiconductor isolation method
JP30967296A JP3205775B2 (ja) 1995-11-21 1996-11-20 半導体装置の素子分離膜形成方法

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Application Number Priority Date Filing Date Title
KR1019950042466A KR100214068B1 (ko) 1995-11-21 1995-11-21 반도체 장치의 소자분리막 형성방법

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KR100214068B1 KR100214068B1 (ko) 1999-08-02

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KR20000041419A (ko) * 1998-12-22 2000-07-15 김영환 트렌치 형성 공정 및 로코스 공정을 이용한 반도체 소자의 소자분리막 형성 방법

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KR100253078B1 (ko) 1997-12-23 2000-04-15 윤종용 반도체 장치의 트렌치 격리 형성 방법
JP2000058802A (ja) 1998-01-13 2000-02-25 Stmicroelectronics Srl Ｓｏｉウェハの製造方法
US6004862A (en) * 1998-01-20 1999-12-21 Advanced Micro Devices, Inc. Core array and periphery isolation technique
KR100286736B1 (ko) 1998-06-16 2001-04-16 윤종용 트렌치 격리 형성 방법
KR100292616B1 (ko) 1998-10-09 2001-07-12 윤종용 트렌치격리의제조방법
US6060348A (en) * 1998-11-02 2000-05-09 Vanguard International Semiconducter Corporation Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology
US6140240A (en) * 1999-01-07 2000-10-31 Vanguard International Semiconductor Corporation Method for eliminating CMP induced microscratches
KR100338767B1 (ko) 1999-10-12 2002-05-30 윤종용 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법
US6509604B1 (en) * 2000-01-26 2003-01-21 Advanced Micro Devices, Inc. Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation
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JP2001230315A (ja) * 2000-02-17 2001-08-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
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KR100713316B1 (ko) 2005-12-28 2007-05-04 동부일렉트로닉스 주식회사 반도체소자의 듀얼 소자분리 방법
US8211778B2 (en) * 2008-12-23 2012-07-03 Micron Technology, Inc. Forming isolation regions for integrated circuits
US8680617B2 (en) * 2009-10-06 2014-03-25 International Business Machines Corporation Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS
KR101116358B1 (ko) * 2009-12-30 2012-03-09 주식회사 하이닉스반도체 매립게이트를 구비하는 반도체장치 제조 방법

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KR100214068B1 (ko) 1999-08-02
JPH09172007A (ja) 1997-06-30
US5712205A (en) 1998-01-27
JP3205775B2 (ja) 2001-09-04

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