KR960019574A - 반도체 소자의 유전체막 형성방법 - Google Patents

반도체 소자의 유전체막 형성방법 Download PDF

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Publication number
KR960019574A
KR960019574A KR1019940030593A KR19940030593A KR960019574A KR 960019574 A KR960019574 A KR 960019574A KR 1019940030593 A KR1019940030593 A KR 1019940030593A KR 19940030593 A KR19940030593 A KR 19940030593A KR 960019574 A KR960019574 A KR 960019574A
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South Korea
Prior art keywords
forming
semiconductor device
polysilicon
oxide film
etching process
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KR1019940030593A
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English (en)
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KR0150669B1 (ko
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양태흠
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김주용
현대전자산업 주식회사
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Priority to KR1019940030593A priority Critical patent/KR0150669B1/ko
Publication of KR960019574A publication Critical patent/KR960019574A/ko
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Publication of KR0150669B1 publication Critical patent/KR0150669B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 유전체막 형성방법에 관한 것으로, 상부산화막을 형성하기 위하여 폴리실리콘을 증착한 후 식각하여 열산화시키므로써 하부전극 양측부의 단차를 개선시켜 후속공정에서의 평탄화를 용이하게 하며 충분한 두께의 상부산화막을 형성하여 데이타 보존능력을 향상시킬 수 있도록 한 반도체 소자의 유전체막 형성방법에 관한 것이다.

Description

반도체 소자의 유전체막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2E도는 본 발명에 따른 반도체 소자의 유전체막 형성방법을 설명하기 위한 소자의 단면도.

Claims (4)

  1. 반도체 소자에서 하부산화막-질화막-상부산화막 구조의 유전체막 형성방법에 있어서, 실리콘기판상에 형성된 하부전극상에 상기 하부산화막 및 상기 질화막을 순차적으로 형성시키는 단계와, 상기 단계로부터 상기 질화막상에 폴리실리콘을 증착하는 단계와, 상기 단계로부터 상기 폴리실리콘이 일부 남도록 전면식각하여 잔여 폴리실리콘을 형성하는 단계와, 상기 단계로부터 산화공정으로 상기 잔여 폴리실리콘을 산화시켜, 그로 인하여 상기 상부산화막이 형성되는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 유전체막 형성방법.
  2. 제1항에 있어서, 상기 잔여 폴리실리콘을 형성하기 위한 전면식각공정은 건식식각공정 및 습식식각공정을 순차적으로 진행하는 것을 특징으로 하는 반도체 소자의 유전체막 형성방법.
  3. 제1항 또는 2항에 있어서, 상기 잔여 폴리실리콘을 형성하기 위한 전면식각공정은 상기 잔여 폴리실리콘의 두께가 30 내지 100Å 정도의 두게가 될 때까지 실시하는 것을 특징으로 하는 반도체 소자의 유전체막 형성방법.
  4. 제1항에 있어서, 상기 하부전극의 측벽에는 전면식각공정으로 잔여 폴리실리콘이 스페이서를 이루는 것을 특징으로 하는 반도체 소자의 유전체막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940030593A 1994-11-21 1994-11-21 반도체 소자의 유전체막 형성방법 KR0150669B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940030593A KR0150669B1 (ko) 1994-11-21 1994-11-21 반도체 소자의 유전체막 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940030593A KR0150669B1 (ko) 1994-11-21 1994-11-21 반도체 소자의 유전체막 형성방법

Publications (2)

Publication Number Publication Date
KR960019574A true KR960019574A (ko) 1996-06-17
KR0150669B1 KR0150669B1 (ko) 1998-12-01

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KR1019940030593A KR0150669B1 (ko) 1994-11-21 1994-11-21 반도체 소자의 유전체막 형성방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100889545B1 (ko) * 2006-09-12 2009-03-23 동부일렉트로닉스 주식회사 플래쉬 메모리 소자의 구조 및 동작 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100889545B1 (ko) * 2006-09-12 2009-03-23 동부일렉트로닉스 주식회사 플래쉬 메모리 소자의 구조 및 동작 방법

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KR0150669B1 (ko) 1998-12-01

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