KR950001986A - 필드산화막 제조방법 - Google Patents

필드산화막 제조방법 Download PDF

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Publication number
KR950001986A
KR950001986A KR1019930011363A KR930011363A KR950001986A KR 950001986 A KR950001986 A KR 950001986A KR 1019930011363 A KR1019930011363 A KR 1019930011363A KR 930011363 A KR930011363 A KR 930011363A KR 950001986 A KR950001986 A KR 950001986A
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South Korea
Prior art keywords
silicon
oxide film
film
field oxide
silicon layer
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KR1019930011363A
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English (en)
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KR100245097B1 (ko
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양홍선
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김주용
현대전자산업 주식회사
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Priority to KR1019930011363A priority Critical patent/KR100245097B1/ko
Publication of KR950001986A publication Critical patent/KR950001986A/ko
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Publication of KR100245097B1 publication Critical patent/KR100245097B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 고집적 반도체 소자의 필드산화막 제조방법에 관한 것으로, 절연막 스페이서를 필드지역의 홈측벽에 형성하는 식각공정에서 홈 저부에 있는 실리콘층이 손상되지 않도록 하고, 절연막 스페이서를 식각할 때 질화막과 실리콘층의 계면이 노출되어 에찬트가 침입되는 것을 방지하고 결함발생을 억제시킬수 있는 필드산화막 제조방법에 관한 것이다.

Description

필드산화막 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제 2F도는 본 발명의 실시예에 의해 필드산화막 제조단계를 도시한 단면도이다.

Claims (4)

  1. 반도체 소자의 필드산화막 제조방법에 있어서, 실리콘기판 상부에 실리콘산화막, 제 1 실리콘층, 실리콘질화막을 순차적으로 적층하는 단계와, 소자분리 마스크공정 및 식각공정으로 필드지역의 실리콘질화막을 식각하여 홈을 형성하고, 홈과 실리콘질화막 상부에 제 2 실리콘층과 절연막을 적층하는 단계와, 상기 절연막을 건식식각하여 홈 측벽에 절연막 스페이서를 형성하고, 불순물을 필드지역의 실리콘기판으로 임플란트시켜 채널스토퍼를 형성하는 단계와, 상기 절연막 스페이서를 절연막 에찬트에서 식각한다음, 열산화공정으로 노출된 제 2 실리콘층과 필드지역의 제 1 실리콘층과 실리콘기판을 산화시켜 필드산화막을 형성하는 단계와, 필드산화막 측면에 있는 실리콘질화막과 제 1 실리콘층을 식각하는 단계를 포함하는 필드산화막 제조방법.
  2. 제 1 항에 있어서, 상기 제 2 실리콘층의 300Å정도의 두께의 다결정실리콘 또는 비정질실리콘으로 형성하는 것을 특징으로 하는 필드산화막 제조방법.
  3. 제 1 항에 있어서, 상기 제 2 실리콘층 상부에 형성하는 절연층은 TEOS막, CVD산화막 또는 질화막으로 형성하는 것을 특징으로 하는 필드산화막 제조방법.
  4. 제 1 항에 있어서, 상기 실리콘기판 상부에 실리콘산화막과 실리콘질화막만 적층한 상태에서 후공정단계를 실시하여 필드산화막을 형성하는 것을 특징으로 하는 필드산화막 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930011363A 1993-06-22 1993-06-22 필드산화막 제조방법 KR100245097B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930011363A KR100245097B1 (ko) 1993-06-22 1993-06-22 필드산화막 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930011363A KR100245097B1 (ko) 1993-06-22 1993-06-22 필드산화막 제조방법

Publications (2)

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KR950001986A true KR950001986A (ko) 1995-01-04
KR100245097B1 KR100245097B1 (ko) 2000-03-02

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KR1019930011363A KR100245097B1 (ko) 1993-06-22 1993-06-22 필드산화막 제조방법

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