KR920018977A - 반도체 디바이스 및 집적회로와 그 제조 방법 - Google Patents

반도체 디바이스 및 집적회로와 그 제조 방법 Download PDF

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KR920018977A
KR920018977A KR1019920004898A KR920004898A KR920018977A KR 920018977 A KR920018977 A KR 920018977A KR 1019920004898 A KR1019920004898 A KR 1019920004898A KR 920004898 A KR920004898 A KR 920004898A KR 920018977 A KR920018977 A KR 920018977A
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oxide layer
oxide
disposed
sidewalls
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민-리앙 첸
치티페디 사일레시
국태호
앨린 포웰 리챠드
쿠머 로이 프라딥
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마이클 제이 어바노
아메리칸 텔리폰 앤드 텔레그라프 캄파티
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

내용 없음

Description

반도체 디바이스 및 집적회로와 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도내지 제7도는 본 발명의 일실시예에 따른 순차적인 제조 단계를 보인 LDD MOSFET의 단면도.

Claims (12)

  1. 측벽을 갖는 구조적 특징과, 상기 측벽에 인접하게 형성된 스페이서를 구비하는 반도체 디바이스로써, 상기 스페이서가 제1의 성장 산화물 층과, 상기 제1의 산화물층 사이에 배치된 산소 투과 유전층과 그리고 상기 측벽과 상기 제1산화물 층 사이에 배치된 제2의 성장 산화물 층으로 이루어지는 복합의 다중층으로된 베이스층을 포함하는 것을 특징으로 하는 반도체 디바이스.
  2. 제1항에 있어서, 상기 유전층상에 배치된 에칭저항 캡 층을 더 포함하는 것을 특징으로 하는 반도체 디바이스.
  3. 제1항에 있어서, 상기 베이스층은 L자형이며, 상기 L자형 베이스층의 레그사이에 배치된 TEOS 충전영역을 더 포함하는 것을 특징으로 하는 반도체 디바이스.
  4. 기판과, 상기 기판상의 한쌍의 공간 이격된 필드 산화물 영역과, 상기 기판상에 게이트 유전을 갖고 그리고 폴리실리콘 측벽을 갖는 게이트 스택과, 상기 측벽 각각에 하나씩 배치된 한쌍의 스페이서와, 상기 기판에서 상기 필드 산화물 영역과 상기 게이트 스택 사이에 배치된 도핑영역을 구비하며, 상기 스페이서 각각이 제1의 성장산화물 층과, 상기 제1의 성장 산화물층에 배치된 산소 투과 유전층과 그리고 상기 적어도 하나의 측벽과 상기 제1의 성장 산화물 층 사이에 배치된 제2의 성장 산화물 층으로 이루어지는 베이스 층을 포함하는 것을 특징으로 하는 집적 회로.
  5. 제4항의 있어서, 상기 스페이서 부분이 상기 스택하부로 침투하여 게이트 유전의 에지에 버드의 비크구조가 형성되고 그리고, 상기 제1및 제2의 성장 산화물층의 두께가 상기 버드의 비크 구조의 크기를 제어하도록 서로 조정되는 것을 특징으로 하는 집적 회로.
  6. 제4또는 5항에 있어서, 상기 스페이서 각각이 상기 제2산화물 층에 배치된 습윤 에칭 저항 캡층을 더 포함하는 것을 특징으로 하는 집적 회로.
  7. 단결정 실리콘 기판상에 게이트 유전을 비롯하여, 폴리실리콘 측벽을 갖는 게이트 스택을 형성시키는 단계와, 적어도 하나의 상기 측벽에 인접한 베이스층을 갖는 스페이서를 형성시키는 단계를 포함하는 집적 회로 제조방법으로써, 상기 베이스층 형성 단계가, 상기 측벽에 제1산화물층을 열적으로 형성시키는 단계와, 상기 제1산화물층에 산소 투과 유전층을 증착시키는 단계와, 그리고 산소가 상기 유전층 상기 제1산화물을 통해 침투하도록 하기에 충분한 압력 및 온도에서 상기 층을 산소 주변에 노출시킴으로써 상기 게이트 스택과 상기 제1산화물층 사이에 제2산화물 층을 열적으로 성장시키는 단계를 포함하는 것을 특징으로 하는 집적 회로 제조방법.
  8. 제7항에 있어서, 상기 유전층을 TEOS의 CVD증착에 증착하고, 상기 제2산화물 층이 상기 유전층을 밀도있게 하기에 충분한 온도에서 성장시키는 단계를 포함하는 것을 특징으로 하는 집적회로 제조방법.
  9. 제8항에 있어서, 상기 열적 성장 단계는 상기 게이트 유전층의 에지에 버드의 비크 구조를 형성시키고 그리고 상기 제1및 제2산화물 층의 두께는 상기 버드의 비크 구조의 크기를 제어하도록 상호 조정되는 것을 특징으로 하는 집적 회로 제조 방법.
  10. 제7, 8 또는 9항에 있어서, 상기 스페이서 형성 단계가 상기 제2산화물 층에 습윤에칭 저항 캡 층을 형성시키는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  11. 제10항에 있어서, 상기 스페이서 형성 단계가 쿼드런트형 스페이서를 형성하도록 함과 아울러 상기 스택상에서 그리고 소오스 및 드레인이 형성될 영역 상에서 상기 층이 제거되도록 하기 위해 층을 비등방성으로 에칭하는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  12. 제11항에 있어서, 상기 스택 및 상기 영역상에 실리사이드 층을 형성시키는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920004898A 1991-03-27 1992-03-26 반도체 장치 및 집적 회로와 그 제조 방법 KR970002266B1 (ko)

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US67856191A 1991-03-27 1991-03-27
US678,561 1991-03-27

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KR970002266B1 KR970002266B1 (ko) 1997-02-27

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US (1) US5573965A (ko)
EP (1) EP0506287B1 (ko)
JP (1) JP2644414B2 (ko)
KR (1) KR970002266B1 (ko)
DE (1) DE69217682T2 (ko)
ES (1) ES2099207T3 (ko)
HK (1) HK119597A (ko)
TW (1) TW203148B (ko)

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US5573965A (en) 1996-11-12
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EP0506287B1 (en) 1997-03-05
EP0506287A1 (en) 1992-09-30
KR970002266B1 (ko) 1997-02-27
HK119597A (en) 1997-09-05
JP2644414B2 (ja) 1997-08-25
DE69217682T2 (de) 1997-09-18

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