SE9904310D0 - Method in the fahrication of a silicon bipolar transistor - Google Patents

Method in the fahrication of a silicon bipolar transistor

Info

Publication number
SE9904310D0
SE9904310D0 SE9904310A SE9904310A SE9904310D0 SE 9904310 D0 SE9904310 D0 SE 9904310D0 SE 9904310 A SE9904310 A SE 9904310A SE 9904310 A SE9904310 A SE 9904310A SE 9904310 D0 SE9904310 D0 SE 9904310D0
Authority
SE
Sweden
Prior art keywords
layer
silicon
base
emitter window
dielectric
Prior art date
Application number
SE9904310A
Other languages
English (en)
Other versions
SE517833C2 (sv
SE9904310L (sv
Inventor
Ted Johansson
Hans Norstroem
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9904310A priority Critical patent/SE517833C2/sv
Publication of SE9904310D0 publication Critical patent/SE9904310D0/sv
Priority to TW088122941A priority patent/TW478161B/zh
Priority to CNB008162395A priority patent/CN1171292C/zh
Priority to EP00980191A priority patent/EP1232523A1/en
Priority to JP2001540834A priority patent/JP2003515927A/ja
Priority to PCT/SE2000/002296 priority patent/WO2001039264A1/en
Priority to AU17487/01A priority patent/AU1748701A/en
Priority to US09/718,423 priority patent/US6440810B1/en
Publication of SE9904310L publication Critical patent/SE9904310L/sv
Publication of SE517833C2 publication Critical patent/SE517833C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
SE9904310A 1999-11-26 1999-11-26 Metod vid tillverkning av en bipolär kiseltransistor för att bilda basområden och öppna ett emitterfönster samt bipolär kiseltransistor tillverkad enligt metoden SE517833C2 (sv)

Priority Applications (8)

Application Number Priority Date Filing Date Title
SE9904310A SE517833C2 (sv) 1999-11-26 1999-11-26 Metod vid tillverkning av en bipolär kiseltransistor för att bilda basområden och öppna ett emitterfönster samt bipolär kiseltransistor tillverkad enligt metoden
TW088122941A TW478161B (en) 1999-11-26 1999-12-24 Method in the fabrication of a silicon bipolar transistor
CNB008162395A CN1171292C (zh) 1999-11-26 2000-11-22 在制造硅双极晶体管时制作基极区和开发射极窗口的方法及硅双极晶体管
EP00980191A EP1232523A1 (en) 1999-11-26 2000-11-22 Method in the fabrication of a silicon bipolar transistor
JP2001540834A JP2003515927A (ja) 1999-11-26 2000-11-22 シリコン・バイポーラ・トランジスタの製造方法
PCT/SE2000/002296 WO2001039264A1 (en) 1999-11-26 2000-11-22 Method in the fabrication of a silicon bipolar transistor
AU17487/01A AU1748701A (en) 1999-11-26 2000-11-22 Method in the fabrication of a silicon bipolar transistor
US09/718,423 US6440810B1 (en) 1999-11-26 2000-11-24 Method in the fabrication of a silicon bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9904310A SE517833C2 (sv) 1999-11-26 1999-11-26 Metod vid tillverkning av en bipolär kiseltransistor för att bilda basområden och öppna ett emitterfönster samt bipolär kiseltransistor tillverkad enligt metoden

Publications (3)

Publication Number Publication Date
SE9904310D0 true SE9904310D0 (sv) 1999-11-26
SE9904310L SE9904310L (sv) 2001-05-27
SE517833C2 SE517833C2 (sv) 2002-07-23

Family

ID=20417885

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9904310A SE517833C2 (sv) 1999-11-26 1999-11-26 Metod vid tillverkning av en bipolär kiseltransistor för att bilda basområden och öppna ett emitterfönster samt bipolär kiseltransistor tillverkad enligt metoden

Country Status (8)

Country Link
US (1) US6440810B1 (sv)
EP (1) EP1232523A1 (sv)
JP (1) JP2003515927A (sv)
CN (1) CN1171292C (sv)
AU (1) AU1748701A (sv)
SE (1) SE517833C2 (sv)
TW (1) TW478161B (sv)
WO (1) WO2001039264A1 (sv)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10134089A1 (de) * 2001-07-13 2003-01-30 Infineon Technologies Ag Verfahren zur Herstellung eines Bipolartransistors mit Polysiliziumemitter
US6597022B1 (en) * 2002-02-04 2003-07-22 Newport Fab, Llc Method for controlling critical dimension in an HBT emitter and related structure
DE10205712A1 (de) * 2002-02-12 2003-08-28 Infineon Technologies Ag Polysilizium-Bipolartransistor und Verfahren zur Herstellung desselben
US6586307B1 (en) * 2002-02-14 2003-07-01 Newport Fab, Llc Method for controlling an emitter window opening in an HBT and related structure
US6891227B2 (en) 2002-03-20 2005-05-10 International Business Machines Corporation Self-aligned nanotube field effect transistor and method of fabricating same
SE522916C2 (sv) * 2002-05-08 2004-03-16 Ericsson Telefon Ab L M Förfarande för att formera basområden och emitterfönster i bipolära kiseltransistorer
KR100518561B1 (ko) * 2003-03-06 2005-10-04 삼성전자주식회사 단결정 실리콘층에의 저메인 가스 전처리를 포함하는바이폴라 소자 제조 방법 및 이에 의한 바이폴라 소자
US6858485B2 (en) * 2003-05-07 2005-02-22 International Business Machines Corporation Method for creation of a very narrow emitter feature
DE102004013478B4 (de) * 2004-03-18 2010-04-01 Austriamicrosystems Ag Verfahren zur Herstellung eines Bipolartransistors mit verbessertem Basisanschluss
GB2425400A (en) * 2005-04-18 2006-10-25 X Fab Semiconductor Foundries Improvements in transistor manufacture
EP1900034B1 (en) * 2005-06-27 2011-08-10 Nxp B.V. Bipolar transistor and method of manufacturing the same
JP2007243140A (ja) 2006-02-09 2007-09-20 Renesas Technology Corp 半導体装置、電子装置および半導体装置の製造方法
US7772060B2 (en) * 2006-06-21 2010-08-10 Texas Instruments Deutschland Gmbh Integrated SiGe NMOS and PMOS transistors
US7947552B2 (en) * 2008-04-21 2011-05-24 Infineon Technologies Ag Process for the simultaneous deposition of crystalline and amorphous layers with doping
CN102456571B (zh) * 2010-10-21 2013-06-12 上海华虹Nec电子有限公司 发射极掺杂多晶硅的制造方法
CN103389616B (zh) * 2012-05-11 2016-02-10 上海华虹宏力半导体制造有限公司 能够改善发射极窗口尺寸均匀性的SiGe器件制造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4641416A (en) * 1985-03-04 1987-02-10 Advanced Micro Devices, Inc. Method of making an integrated circuit structure with self-aligned oxidation to isolate extrinsic base from emitter
US4704785A (en) * 1986-08-01 1987-11-10 Texas Instruments Incorporated Process for making a buried conductor by fusing two wafers
JP2592277B2 (ja) * 1988-01-11 1997-03-19 富士通株式会社 バイポーラ半導体装置の製造方法
US5028557A (en) * 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
US5266504A (en) * 1992-03-26 1993-11-30 International Business Machines Corporation Low temperature emitter process for high performance bipolar devices
US5643806A (en) * 1993-02-28 1997-07-01 Sony Corporation Manufacturing method for making bipolar device
JP2803548B2 (ja) * 1993-12-28 1998-09-24 日本電気株式会社 半導体装置の製造方法
JP3223693B2 (ja) * 1994-03-18 2001-10-29 株式会社日立製作所 バイポーラ素子
JP2654540B2 (ja) * 1994-06-21 1997-09-17 日本電気株式会社 半導体装置の製造方法
US5541121A (en) * 1995-01-30 1996-07-30 Texas Instruments Incorporated Reduced resistance base contact method for single polysilicon bipolar transistors using extrinsic base diffusion from a diffusion source dielectric layer
JP3444002B2 (ja) * 1995-02-14 2003-09-08 ソニー株式会社 半導体装置およびその製造方法
US5593905A (en) * 1995-02-23 1997-01-14 Texas Instruments Incorporated Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link
US5592017A (en) * 1995-03-23 1997-01-07 Texas Instruments Incorporated Self-aligned double poly BJT using sige spacers as extrinsic base contacts
US5866462A (en) * 1995-09-29 1999-02-02 Analog Devices, Incorporated Double-spacer technique for forming a bipolar transistor with a very narrow emitter
SE508635C2 (sv) * 1995-11-20 1998-10-26 Ericsson Telefon Ab L M Förfarande för selektiv etsning vid tillverkning av en bipolär transistor med självregistrerande bas-emitterstruktur
KR970054343A (ko) * 1995-12-20 1997-07-31 이준 규소/규소게르마늄 쌍극자 트랜지스터 제조방법
US5943564A (en) * 1996-02-13 1999-08-24 National Semiconductor Corporation BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures
JPH10256269A (ja) * 1997-03-17 1998-09-25 Sony Corp 半導体装置の製造方法
JP3321553B2 (ja) * 1997-10-08 2002-09-03 松下電器産業株式会社 Ｂｉ−ＣＭＯＳ集積回路装置の製造方法
US6248650B1 (en) * 1997-12-23 2001-06-19 Texas Instruments Incorporated Self-aligned BJT emitter contact
FR2795233B1 (fr) * 1999-06-18 2001-08-24 St Microelectronics Sa Procede de fabrication autoaligne de transistors bipolaires

Also Published As

Publication number Publication date
JP2003515927A (ja) 2003-05-07
AU1748701A (en) 2001-06-04
WO2001039264A1 (en) 2001-05-31
SE517833C2 (sv) 2002-07-23
CN1399793A (zh) 2003-02-26
TW478161B (en) 2002-03-01
CN1171292C (zh) 2004-10-13
US6440810B1 (en) 2002-08-27
SE9904310L (sv) 2001-05-27
EP1232523A1 (en) 2002-08-21

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