KR960026540A - 반도체 소자의 절연 방법 - Google Patents

반도체 소자의 절연 방법 Download PDF

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Publication number
KR960026540A
KR960026540A KR1019940032384A KR19940032384A KR960026540A KR 960026540 A KR960026540 A KR 960026540A KR 1019940032384 A KR1019940032384 A KR 1019940032384A KR 19940032384 A KR19940032384 A KR 19940032384A KR 960026540 A KR960026540 A KR 960026540A
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KR
South Korea
Prior art keywords
layer
etching
forming
nitride film
porous silicon
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Application number
KR1019940032384A
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English (en)
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KR0137820B1 (ko
Inventor
권영정
Original Assignee
문정환
Lg 반도체주식회사
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Priority to KR1019940032384A priority Critical patent/KR0137820B1/ko
Publication of KR960026540A publication Critical patent/KR960026540A/ko
Application granted granted Critical
Publication of KR0137820B1 publication Critical patent/KR0137820B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Weting (AREA)

Abstract

본 발명은 반도체 소자의 절연 방법에 관한 것으로서, 종래의 문제점이었던 절연공간이 넓어지는 문제점을 해결하기 위하여 반도체 기판상에 매립층을 형성시키고 에피층을 형성시킨 후, 식각작업을 하여 절연영역을 정의하고, 이렇게 식각된영역을 통하여 에피층하부의 매입층을 다공화시킨 후 산화층을 형성시키므로써 절연영역을 필요한 만큼만 형성시키는 것을 특징으로 한다.

Description

반도체 소자의 절연 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 반도체 소자의 절연 방법을 설명한 도면.

Claims (4)

  1. 반도체 소자의 절연방법에 있어서, 1) 반도체 기판상에 고농도 매입층을 형성시킨 뒤, 그 상부에 저농도 에피층을 형성시키는 단계와, 2) 상기 저농도 에피층의 상부에 질화막을 형성시키고, 상기 질화막을 사진식각하여 절연부와 소자부의 패턴을 형성시키는 단계와, 3) 상기 에피층 하부의 상기 고농도 매입층이 드러날때까지 상기 질화막을 마스크로 하여 상기 저농도 에피층을 식각시키는 단계와, 4) 상기 반도체 기판을 상기 질화막 패턴을 마스크로 15-48wt% HF수용액내에서 HF양극반응을 수행하여 상기 고농도 매입층을 다공질 실리콘으로 전환시키는 단계와, 5) 상기 다공질 실리콘층이 형성된 반도체 기판을 고온으로 열산화하여 다공질 실리콘층을 산화 다공질 실리콘층으로 전환시키면서 질화막의 상부까지 산화막을 성장시키는 단계로 이루어져 반도체 기판상의 소자간 및 기판과의 절연층을 형성시키는 것을 특징으로 하는 반도체 소자의 절연 방법.
  2. 제1항에 있어서, 상기 3)단계의 상기 에피층 식각을 건식식각으로 수행함을 특징으로 하는 반도체 소자의 절연 방법.
  3. 제2항에 있어서, 상기 에피층의 식각시에 식각의 두께를 에피층 두께의 120%로 하여 수행하는 특징으로 하는 반도체 소자의 절연 방법.
  4. 제1항에 있어서, 상기 4)단계의 HF양극 반응시에 약 30wt% HF수용액내에서 수행하는 것을 특징으로 하는 반도체 소자의 절연 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940032384A 1994-12-01 1994-12-01 반도체 소자의 절연방법 KR0137820B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940032384A KR0137820B1 (ko) 1994-12-01 1994-12-01 반도체 소자의 절연방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940032384A KR0137820B1 (ko) 1994-12-01 1994-12-01 반도체 소자의 절연방법

Publications (2)

Publication Number Publication Date
KR960026540A true KR960026540A (ko) 1996-07-22
KR0137820B1 KR0137820B1 (ko) 1998-06-01

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KR1019940032384A KR0137820B1 (ko) 1994-12-01 1994-12-01 반도체 소자의 절연방법

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KR (1) KR0137820B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100976792B1 (ko) * 2007-12-21 2010-08-19 주식회사 동부하이텍 다공성 저 유전층을 갖는 반도체 소자의 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100976792B1 (ko) * 2007-12-21 2010-08-19 주식회사 동부하이텍 다공성 저 유전층을 갖는 반도체 소자의 제조 방법

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Publication number Publication date
KR0137820B1 (ko) 1998-06-01

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