TWI546906B - 晶圓級扇出晶片的封裝結構及封裝方法 - Google Patents

晶圓級扇出晶片的封裝結構及封裝方法 Download PDF

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Publication number
TWI546906B
TWI546906B TW103109545A TW103109545A TWI546906B TW I546906 B TWI546906 B TW I546906B TW 103109545 A TW103109545 A TW 103109545A TW 103109545 A TW103109545 A TW 103109545A TW I546906 B TWI546906 B TW I546906B
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Taiwan
Prior art keywords
wafer
wafers
package
insulating
carrier
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TW103109545A
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English (en)
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TW201535624A (zh
Inventor
謝智正
許修文
葉俊瑩
冷中明
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尼克森微電子股份有限公司
帥群微電子股份有限公司
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Priority to TW103109545A priority Critical patent/TWI546906B/zh
Priority to US14/574,405 priority patent/US9299592B2/en
Publication of TW201535624A publication Critical patent/TW201535624A/zh
Application granted granted Critical
Publication of TWI546906B publication Critical patent/TWI546906B/zh

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Description

晶圓級扇出晶片的封裝結構及封裝方法
本發明是有關於一種晶片的封裝結構及方法，且特別是有關於一種晶圓級扇出晶片的封裝結構及封裝方法。
隨著電子產品的普及化，可攜帶式與穿戴式的電子產品成為人們生活中必備的工具。而開發具有高效能、小體積、高運算速度、高品質以及多功能的電子產品及元件，成為必要的趨勢。就外觀而言，輕、薄、短、小的電子產品成為必然的趨勢，而為了配合趨勢的要求，晶圓級(Wafer Level Chip Scale Package,WLCSP)的封裝工藝成為必要的選擇之一。
晶圓級封裝與傳統的封裝技術主要的差異在於：晶圓級封裝的概念是直接在晶圓上完成積體電路的封裝，而非針對切割後的個別的晶片進行封裝製程。透過晶圓級的封裝，封裝後的晶片的尺寸與晶粒原有的尺寸相同。而這樣的晶圓級封裝的尺寸會限制住佈局扇出(Fan-Out)的範圍。
本發明的目的在於提供一種封裝成本低、產品封裝體厚度薄，機械支撐能力強化，具有良好散熱效果，提高產品使用壽命的圓片級扇出晶片封裝結構和封裝方法。
本發明的晶圓級扇出晶片的封裝方法包括：提供一載體，並配置多個晶片在載體上；形成多個黏著層在對應晶片的一主動面上；覆蓋一導電蓋體，使導電蓋體透過黏著層與晶片黏合，導電蓋體分別區隔晶片於多個封裝空間；接著，使該絕緣材料透過導電蓋體上的多個貫孔，填入封裝空間形成第一絕緣結構；最後，移除載體。
本發明另提出一種晶圓級扇出晶片的封裝結構，包括導電板、一晶片、第一絕緣結構、第二絕緣結構以及多個焊墊。導電板具有承載部以及至少一個突起部，晶片透過多個黏著層黏著在該承載部上。第一絕緣結構圍繞在該些晶片的周圍與承載部上。第二絕緣結構分別隔離多個電極窗。焊墊分別配置在電極窗中以形成多個電極。
基於上述，本發明的封裝方法透過以吸入(或填入)的方式，將絕緣材料完整的包覆晶片的周圍，以提高封裝後的晶片的可靠度。並且，透過本發明的晶圓級的封裝方法，封裝後的晶片可以透過晶圓級的測試機台進行測試，大幅降低生產流程的複雜度以及封裝成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉 實施例，並配合所附圖式作詳細說明如下。
S110~S160‧‧‧封裝方法的步驟
210‧‧‧載體
211‧‧‧剝離膜膠帶
221~222、321‧‧‧晶片
231、232‧‧‧黏著層
240‧‧‧導電蓋體
241‧‧‧隔板
300、410、420‧‧‧封裝結構
340‧‧‧導電板
370‧‧‧粘著層
400‧‧‧電源轉換電路
T1、T2‧‧‧側邊
H1、H2‧‧‧貫孔
Z1、Z2‧‧‧封裝空間
PM‧‧‧第一絕緣結構
GP‧‧‧玻璃基板
PL‧‧‧第二絕緣結構
W1~WN‧‧‧電極窗
PAD1~PADN‧‧‧焊墊
BA1~BAN‧‧‧焊球
A-A’、B-B’‧‧‧線段
3401‧‧‧承載部
3402‧‧‧突起部
M1~M5‧‧‧電晶體
DC‧‧‧汲極
S1、S2‧‧‧源極
G1、G2‧‧‧閘極
D1‧‧‧二極體
L1‧‧‧電感
GND‧‧‧接地端
C1‧‧‧電容
圖1繪示本發明一實施例的晶圓級扇出晶片的封裝方法的流程圖。
圖2A~圖2K繪示的本發明實施例的晶圓級扇出晶片的封裝方法的實施細節示意圖。
圖3A繪示本發明一實施例的晶圓級扇出晶片的封裝結構300的示意圖立體圖。
圖3B則繪示封裝結構300線段B-B’的剖面圖。
圖3C則繪示本發明另一實施例的晶圓級扇出晶片封裝結構的剖面圖。
圖4A~圖4C繪示的本發明實施例的封裝結構的應用的示意圖。
其製造流程與方法的一實施例請參見圖1，圖1繪示本發明一實施例的晶圓級扇出晶片的封裝方法的流程圖，並且請同時參照圖2A~圖2K繪示的本發明實施例的晶圓級扇出晶片的封裝方法的實施細節示意圖。在圖1以及圖2A中，步驟S110中提供一載體210，載體210表面覆蓋剝離膜膠帶211。在本實施例中，載 體210可以是一個與晶圓尺寸一致的圓形載體，例如6吋、8吋或是12吋的圓片。而關於材質方面，載體210則可以由如金屬、金屬合金、塑膠或是石英玻璃等材料所製作。載體210可以是導電的或絕緣的材料所構成。剝離膜膠帶211則可以是雙面粘性的膠帶。
接著，在步驟S120中，則將晶圓上切割下來的多個晶片配置在載體210上，在此晶片以垂直型金屬氧化半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)為例，當然其他如絕緣閘雙極電晶體(Insulated Gate Bipolar Transistor，IGBT)，雙載子接面電晶體(Bipolar Junction Transistor，BJT)，二極體(Diode)等都是可能應用，其中晶片第一主動面可設計包括源極、閘極兩個電極，。晶片背面，即第二主動面設計做為汲極。其中，在圖2B中，晶片221~222被配置在載體210，並且，晶片221~222的第一主動面與剝離膜膠帶211相接觸以進行黏合。在步驟S130中，形成多個黏著層在對應載體210上的多個晶片的221~222的第二主動面上，例如圖2C繪示的黏著層231及232。
關於黏著層231及232的形成方法，可以利用點膠或是網版塗佈方式，將具有導電性的黏著層231及232，適量的分別放置在晶片221~222的第二主動面上。黏著層231及232可以是銀膠、錫膏或銅膏等導電材。
在步驟S140中，則覆蓋導電蓋體240在晶片221~222及載體210的上方。導電蓋體240可透過黏著層231及232分別與 晶片221~222產生電性連接。並且，導電蓋體240的第一側邊T1具有多個隔板241。導電蓋體240可透過隔板241，將晶片221~222分別區隔於多個封裝空間Z1及Z2中。上述導電蓋體240可以是圓形的金屬框，並可以由銅、鐵鎳等具電氣傳導特性的材質所形成。導電蓋體240可以依照客戶需求設計形狀與尺寸，並使用蝕刻或者是衝模的方式製造。導電蓋體240可以配合所要封裝的晶片221~222的晶圓而製作為6吋、8吋或是12吋的圓片，或可製作為平板狀。舉例來說，導電蓋體240可以為25μm至100μm厚的銅合金片所製成。
此外，隔板241可以透過蝕刻的方式來形成，隔板241與剝離膜膠帶211接觸的平面，則可以與晶片221~222的第二主動面共平面。隔板241所形成的位置以及厚度則可以依據晶片221~222配置在剝離膜膠帶211上的位置來進行對應的調整。在導電蓋體240中，多個隔板241可以形成網狀的結構以分隔出多個陣列排列的封裝空間。
承上述，在步驟S150中，將絕緣材料透過導電蓋上的多個注膠孔(或貫孔)，填入封裝空間所留下的空洞Z1,Z2，形成第一絕緣結構。請同步參照圖1以及圖2E，可在導電蓋體240上對應封裝空間Z1以及Z2的位置分別形成貫孔H1以及H2，再請參照圖圖2F，透過提供液態物質的的絕緣材料，以使絕緣材料PM透過貫孔H1以及H2被填入或吸入至封裝空間Z1以及Z2中，在一實施例中被吸入的絕緣材料將會填滿封裝空間Z1以及Z2，以形 成第一絕緣結構PM。此外，在絕緣材料填滿封裝空間Z1以及Z2後，並對第一絕緣結構PM進行固化動作。
絕緣材料可以是絕緣模塑材料，並可以是任何合適的熱塑或熱固性材料，例如環氧基材料、矽膠或是光阻劑等等的樹脂。固化後的絕緣材料形成多個模塑體，並為提供保護晶片221~222的剛性結構。為使絕緣材料完全填滿封裝空間Z1以及Z2，本發明實施例可透過貫孔H1以及H2來進行抽真空的動作，並使封裝空間Z1以及Z2形成真空狀態，再施加液態的絕緣材料於貫孔H1以及H2上方，使液態的絕緣材料可以有效的被吸入至封裝空間Z1以及Z2中，並填滿封裝空間Z1以及Z2。如此一來，固化後的絕緣材料所產生的模塑體將不會因為內含多個孔洞而致使結構不堅固，並提升封裝的可靠度。
接著，在步驟S160，則移除載體210(如圖2G所示)，其中，載體210的移除可透過移除剝離膜膠帶211來達成。值得注意的是，圖2G所示，透過上述的工藝所完成的塑封圓片的結構平整，沒有翹曲或過厚及溢膠問題，無須進行減薄與清潔步驟，有效降低封裝方法的複雜度。
接著，在關於封裝後晶片的電極形成方式的部份，請參照圖2H~圖2J。在圖2H中，將完成的塑封圓片的導電蓋體240與玻璃基板GP結合，使玻璃基板GP直接接觸導電蓋體240的第二側邊T2。
並且在晶片221~222第一主動面塗佈一層高分子介電材 料以形成一絕緣層，此絕緣層目的在於增加鈍化層(passivation)的強度，對晶片形成一定程度上的絕緣隔離保護。然後透過部分蝕刻方式在絕緣層上形成多個電極窗W1~WN，其中電極窗W1~WN做為後續汲極、源極以及閘極接觸窗口，而剩餘絕緣層部份形成於除電極窗W1~WN位置的表面，使得第二絕緣結構PL分別將電極窗W1~WN做隔離。電極窗W1~WN形成於晶片221~222第一主動面的部分上與隔板上241的部分上，第二絕緣結構PL也覆蓋晶片221~222第一主動面的部分與隔板上241的部分。電極窗W1~WN用來接觸晶片221~222部分的第一主動面的裸露部分以及隔板241裸露部分。這些裸露出的表面上，亦即電極窗W1~WN中，則可分別形成多個焊墊PAD1~PADN，此焊墊稱為凸塊底層金屬(UBM)，作為後續直球或者凸塊作業金屬間的連接用。
在圖2I中，則分別形成多個焊球BA1~BAN在焊墊PAD1~PADN上，並形成多個電極。其中，焊球BA1可以做為晶片221中的電晶體的汲極，焊球BA2及BA3則分別可以作為電晶體的閘極以及源極。完成植球相關作業後，移除玻璃基板GP，如圖2J。
由圖2J可以得知，多個晶片221~222以晶圓級的方式完成封裝，並在當要對封裝後的晶片221~222晶片進行測試時，可以利用圖2J的晶圓級的封裝體透過晶圓級的測試機來完成測試。這樣一來可利用裸晶針測(Chip Probing,CP)將晶片上的晶粒根據設計的電性標準規格，以針測方式檢測藉以進行一次性的測 試，大幅降低測試成本以及測試所需的時間。當然也可以切割好，對分離完成的元件進行成品測試。
最終依據圖2J的線段A-A’的位置進行切割，所獲得切割後的封裝結構如圖2K所示。在圖2K中，晶片221的第一主動面與導電蓋體240電性連接，並透過焊球BA1以形成晶片221中電晶體的汲極，晶片221的第二主動面則電性連接至焊球BA2及BA3並分別形成晶片221中電晶體的閘極以及源極。
以下請同步參照圖3A以及圖3B，圖3A繪示本發明一實施例的晶圓級扇出晶片的封裝結構300的立體圖，圖3B則繪示封裝結構300線段B-B’的剖面圖。封裝結構300是依據本發明圖1實施例的封裝方法所產生的封裝結構。其中，封裝結構300包括導電板340(由導電蓋體240切割多個的其中一個)、晶片321、第一絕緣結構PM、第二絕緣結構PL以及多個焊球BA1~BA3。導電板340具有承載部3401以及突起部3402(對應2H圖隔板241)，承載部3401以及突起部3402相互接觸。其中，承載部3401用來承載晶片321，而突起部3402則用來形成焊球BA1。
晶片321透過黏著層370黏著在承載部3401上，黏著層370為可導電材質的黏著材料，晶片321則透過黏著層370來與導電板340電子連接。第一絕緣結構PM則圍繞在晶片321的周圍並覆蓋承載部3401未與晶片321的上表面接觸。第二絕緣結構PL隔離多個電極窗(參考第2H的W1~WN)，且第二絕緣結構PL覆蓋在部分晶片321的主動面上與部分導電板340的突起部3402上， 至於第一絕緣結構PM因無電極窗存在，故第二絕緣結構PL可以完全覆蓋第一絕緣結構PM。多個電極窗接觸到晶片321。而突起部3402上同樣具有多個電極窗。上述電極窗用來形成焊球BA1~BA3，其中，焊球BA1配置在突起部3402上的電極窗中，焊球BA2、BA3則配置在晶片321上的電極窗中。在本實施例中，焊球BA1可做為晶片321中電晶體的汲極，焊球BA2可做為晶片321中電晶體的閘極，焊球BA3則可做為晶片321中電晶體的源極。
值得注意的是，本發明實施例中的第一絕緣結構PM是透過原先為液態型態注入其所存在的空間中，並對液態型態的絕緣材料執行固化的動作。固化後的第一絕緣結構PM的上表面會與導電板340的突起部3402用來形成焊球BA1的上表面在相同的平面上。如此一來，固化後的第一絕緣結構PM可以在封裝結構300形成堅固的結構，有效達到保護晶片321的功效。
對應前述關於封裝方法的實施例中，本實施例的突起部3402即為前述實施例中導電蓋體上的隔板。本實施例的導電板340則為前述實施例中的導電蓋體或分割後一部分。而第一絕緣結構PM為固化後的狀態。
本實施例使用金屬連接在晶片汲極金屬層上，除強化機械強度外，還可以增加散熱效果，另外可連接到印刷電路板(Printed Circuit Board,PCB)上，利用印刷電路板上的銅箔，進一步降低熱阻係數，提高產品使用壽命，也因為汲極連接金屬，可以適合更 薄的晶片，如50um或更小之尺寸。圖3C為本發明另一實施例的晶圓級扇出晶片封裝結構的剖面圖。因此如圖3C，此應用可以置入兩顆相同或者不同規格的MOSFET。
關於晶片321，可參照圖4A~圖4C繪示的本發明實施例的封裝結構的應用的示意圖。其中，在圖4A中，晶片321可以包括一個或多個電晶體M1及M2。其中，電晶體M1及M2的汲極DC相互連接，並可透過焊球BA1形成電極，而電晶體M1及M2的源極S1及S2可分別透過不同的焊球BA3形成兩個相互隔離的源極，而電晶體M1及M2的閘極G1及G2可分別透過不同的焊球BA1形成兩個相互隔離的閘極。
在圖4B中，本發明的封裝結構亦可應用在電源轉換電路中。其中，圖4B中的電源轉換電路400包括封裝結構410。封裝結構410中的晶片包括電晶體M3以及二極體D1。電晶體M3的汲極與二極體D1的陽極可透過封裝結構410中的導電板相互耦接，並透過對應焊球所形成的電極被連接到電感L1，電晶體M3的源極可以透過對應的焊球所形成的電極被耦接到接地端GND，而電晶體M3的閘極可以透過對應的焊球所形成的電極來接收驅動電壓，例如為脈寬調變信號的驅動電壓。此外，二極體D1的陰極亦可透過對應的焊球所形成的電極被耦接至電容C1。
圖4C則為包括具有兩個電晶體M4~M5的封裝結構420的電路。在圖4C中，電晶體M4~M5共同耦接的汲極可透過封裝結構420上的電極被連接至電感L2，電晶體M4~M5的閘極以及 源極則可分別透過對應的電極來接收所需要的信號或電壓，來滿足電路運作的需求。
綜上所述，本發明透過將絕緣材料以吸入或填入的方式，使其包覆在晶片的周圍，藉以提高封裝後的晶片的可靠度。並且，透過晶圓級的封裝方法來減低生產流程的複雜度以及封裝成，有效提升產品的競爭力。
S110~S160‧‧‧封裝方法的步驟

Claims (9)

  1. 一種晶圓級扇出晶片的封裝方法，包括：提供一載體；配置多個晶片在該載體上；形成多個黏著層在對應該些晶片的一主動面上；覆蓋一導電蓋體，使該導電蓋體透過該些黏著層與該些晶片黏合，該導電蓋體並分別區隔該些晶片於多個封裝空間；使一絕緣材料透過該導電蓋體的多個貫孔，填入該些封裝空間形成一第一絕緣結構；以及移除該載體。
  2. 如申請專利範圍第1項所述的封裝方法，其中該導電蓋體的一第一側邊具有多個隔板，用以區隔出該些封裝空間。
  3. 如申請專利範圍第2項所述的封裝方法，其中移除該載體的步驟後更包括：提供一玻璃基板於該導電蓋體的一第二側邊；形成多數個電極窗，並以一第二絕緣結構分別隔離；以及形成多個焊墊在該些電極窗中以形成多個電極。
  4. 如申請專利範圍第3項所述的封裝方法，其中該第二絕緣結構覆蓋到部分該些晶片上與部分該些隔板上。
  5. 如申請專利範圍第1項所述的封裝方法，其中該絕緣材料為一液態物質，並使該絕緣材料透過該些貫孔，填入該些封裝空間形成該第一絕緣結構。
  6. 如申請專利範圍第1項所述的封裝方法，其中形成該些黏著層在該些晶片的表面上的步驟包括：利用一點膠或一網版塗佈的方式，在該些晶片的該主動面上形成該些黏著層，且該些黏著層具有導電性。
  7. 一種晶圓級扇出晶片的封裝結構，包括：一導電板，具有一承載部以及至少一突起部；一晶片，透過一黏著層黏著在該承載部上；一第一絕緣結構，圍繞在該晶片的周圍與該承載部上；一第二絕緣結構，覆蓋在部分的該晶片以及部分的該突起部上，以分別隔離出多個電極窗；以及多個焊墊，分別配置在該些電極窗中以形成多個電極。
  8. 如申請專利範圍第7項所述晶圓級扇出晶片的封裝結構，其中該第一絕緣結構的一表面與該突起部的一表面為共平面。
  9. 如申請專利範圍第7項所述晶圓級扇出晶片的封裝結構，其中該些黏著層為具有導電性，且該些晶片為至少一金屬氧化半導體場效電晶體(MOSFET)、一絕緣閘雙極電晶體(IGBT)、雙載子接面電晶體(BJT)、二極體(Diode)元件及其相互組合。
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